JPH11355177A - Delay profile detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a required time for a multi-bus component selection processing by calculating the power of respective multi-bus components contained in a reception signal, comparing the power peak values of the respective multi-bus components with a prescribed limiter value, outputting only the delay profile of the multi-bus component having the power peak value of more than the limiter value and accumulating it. SOLUTION: A reception signal is formed of a base band signal which is converted into an intermediate frequency and from a radio frequency band, is phase-modulated and directly diffused, and plural reception data having different delay times as the multi-bus components coexist in the signal. A limiter 2 is installed in the post stage of a correlation calculation part 1 and only a delay profile whose power peak value is more than the prescribed limiter value in the respective delay profiles outputted from the correlation calculation part 1 is selected and it is stored in a delay profile accumulation part 4. The limiter 2 compares the power peak value of the delay profile, which is obtained for every multi-bus component, with the limiter value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay profile detector, and more particularly to a delay profile detector for detecting a delay profile used for selecting a reception timing in CDMA.

[0002]

2. Description of the Related Art Generally, CDMA (Coded Division Mull)
In tiple access), for each multipath component included in a radio wave received through a multipath generated by reflection or diffraction, a signal power distribution, that is, a delay profile, with respect to a delay time at the time of arrival is detected and individually managed. It becomes important. For example, in the receiver,
With the configuration shown in FIG. 5, one of a plurality of multipath components having different delay times is selected and demodulated.

Here, first, a delay profile detector 5
2, the delay profile of each multipath component included in the received signal is detected. FIG. 6 is an explanatory diagram showing a delay profile. Since multipaths generated by reflection or diffraction have different propagation path lengths, radio waves transmitted from the same transmitter reach the receiver with a delay time corresponding to each propagation path length.

In FIG. 6, each multipath component 61-6
3 have delay times t1 to t3, respectively, and a delay profile is detected for each multipath component. The delay control unit 52 (see FIG. 5) controls the delay correction unit 53 based on the delay profile detected by the delay profile detector 52. As a result, the reception timing is selected, a desired multipath component is extracted, and is decoded and output by the decoding unit 54.

[0005]

However, such a conventional delay profile detector holds delay profiles for all detected multipath components, so that an optimum multipath component is obtained based on an error rate of a decoding result. When selecting a path component, there is a problem that the time required for the selection process increases because the number of delay profiles is large. Further, as the number of multipath components increases, the storage capacity required for holding increases, and there is a problem that the circuit scale increases. The present invention has been made to solve such a problem, and an object of the present invention is to provide a delay profile detector that can reduce the time required for multipath component selection processing and reduce the circuit scale.

[0006]

In order to achieve such an object, a delay profile detector according to the present invention comprises: a power calculating means for calculating the power of each multipath component included in a received signal; A limiter unit that compares the power peak value of the component with a predetermined limiter value and outputs only a delay profile of a multipath component having a power peak value equal to or greater than the limiter value, and accumulates a delay profile output from the limiter unit. And delay profile storage means.

Further, the power calculating means is constituted by a correlation calculating means for calculating the power of each multipath component by calculating and integrating the correlation between the received signal and the result of multiplication of the replica. Each of the multipaths is calculated by despreading the received signal using a predetermined spreading code and calculating and integrating the sum of squares of a complex signal component indicating the despread result. And a square sum calculating means for calculating the power of the component.

[0008]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a delay profile detector according to a first embodiment of the present invention.
A description will be given using DMA as an example. The received signal is a baseband signal that is QPSK (phase) modulated and directly spread from a radio frequency band converted to an intermediate frequency band, and a plurality of received data having different delay times as multipath components are mixed in the received signal. doing.

FIG. 2 is an explanatory diagram showing a format of received data. The received data is composed of a large number of slots provided continuously on the time axis, and a predetermined number of slots constitute one frame. Each slot has a pilot 21 at its head, and data 22 is stored thereafter.

In CDMA, information D _R to be received is encoded with a predetermined spreading code C _R and transmitted. That is, the received signal R _R is represented as R _R = D _R × C _R. Known information is stored in the pilot 21, and communication control information and the like are encoded and stored in the data 22.

[0011] Such received signal is a correlation calculating unit 1 is inputted (see FIG. 1), the received signal R _R to the replica R _R L (which pilot information D _PL encoded spreading code C _R) Is calculated. First, the received signal R _R is multiplied by the replica R _PL to obtain a multiplication result C _O.

C _O = R _R × R _PL = (D _R × C _R ) × (D _PL × C _R ) = D _R × D _PL × C _R ² where the square of the spreading code C _R is 1 By selecting so that C _O = D _R × D _PL .

[0013] Then, an orthogonal complex components of D _R and I _R, Q _R, when the orthogonal complex components of D _PL I _PL, and Q _PL, state received signal R _R and the replica R _PL is synchronized Then The correlation is obtained by integrating this D _R × D _PL for a specific period, and this becomes one sample of the delay profile.

As described above, in the correlation calculating section 1,
One sample of the correlation i.e. the delay profile of the received signal R _R and the replica R _PL, by obtaining some period, the actual delay profile is obtained. In the present invention,
A limiter is provided at the subsequent stage of the correlation calculation unit 1 and only the delay profile whose power peak value is equal to or more than a predetermined limiter value (threshold value) is selected from among the delay profiles output from the correlation calculation unit 1, and the delay profile is selected. This is stored in the storage unit 4.

FIG. 3 is an explanatory diagram showing the operation of the limiter. The limiter 2 compares the power peak values of the delay profiles 31 to 35 obtained for each multipath component with the limiter value 30 set by the limiter setting unit 3. Then, a delay profile with a limiter value of 30 or more, in this case, delay profiles 31 to 33 is selected and stored in the delay profile storage unit 4.

In the above description, an example has been described in which the present invention is applied to a case where a delay profile is obtained by correlation between a received signal and a replica. However, a delay profile is obtained by despreading a received signal and calculating power. Also applicable to cases. FIG. 4 is a block diagram showing a delay profile detector according to a second embodiment of the present invention.

Here, a despreading calculator 11 and a sum of squares calculator 12 are provided instead of the correlation calculator 1 in FIG. The despreading calculator 11 multiplies the received signal R _R by the spreading code C _R to obtain the despread result C _OR.
Get. _{C OR = R R × C R} = (D R × C R) × C R = D R × C R 2

Here, by selecting the spreading code C _{R so} that its square becomes 1, _COR = D _R , and _COR becomes a despread complex signal. continue,
In the square sum calculating section 12 calculates the power of the C _OR 2 squared to. If an orthogonal complex components D _R was I _R, Q _R, a ^{_{C OR 2 = I R 2 +}} Q R 2.

Then, a correlation is obtained by integrating this _COR for a specific period, which is one of the delay profiles.
Be a sample. In this way, the square sum calculation unit 12 obtains one sample of the delay profile for a certain period, thereby obtaining an actual delay profile. After that, a predetermined delay profile is selected by the limiter 2 based on the limiter value set by the limiter value setting unit 3 and stored in the delay profile storage unit 4 as described above.

[0020]

As described above, according to the present invention, the limiter is provided after the power calculating means for calculating the power of each multipath component included in the received signal, and the power peak value of each multipath component is determined. Compare with the predetermined limiter value,
Since only the delay profile of the multipath component having the power peak value equal to or higher than the limiter value is output,
Only a relatively effective delay profile having a large power peak value is held. Therefore, it is possible to reduce the time required for the multipath component selection process and reduce the circuit scale of the storage unit that holds the delay profile, as compared with the case where all delay profiles are held as in the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram of a delay profile detector according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a format of received data.

FIG. 3 is an explanatory diagram showing an operation of a limiter.

FIG. 4 is a block diagram of a delay profile detector according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a multipath component selection process.

FIG. 6 is an explanatory diagram showing a delay profile.

[Description of Signs] 1 ... Correlation calculation unit, 2 ... Limiter, 3 ... Limiter value setting unit, 4 ... Delay profile accumulation unit, 11 ... Despread calculation unit, 12 ... Square sum calculation unit, 21 ... Pilot, 22 ... data.

Claims (3)

[Claims] 1. A delay profile detector for detecting and outputting a delay profile of a plurality of multipath components included in a received signal, a power calculating means for calculating power of each multipath component included in the received signal, Limiter means for comparing the power peak value of the component with a predetermined limiter value and outputting only a delay profile of a multipath component having a power peak value equal to or greater than the limiter value; and accumulating the delay profile output from the limiter means. A delay profile detector comprising: a delay profile storage unit. 2. The delay profile detector according to claim 1, wherein the power calculating means calculates the power of each multipath component by calculating and integrating the correlation between the received signal and the replica and the result of the multiplication. 1. A delay profile detector comprising: a correlation calculating means. 3. The delay profile detector according to claim 1, wherein the power calculating means despreads the received signal using a predetermined spreading code, and calculates a complex signal component indicating a result of the despreading. A delay profile detector comprising a square sum calculator for calculating the power of each multipath component by calculating and integrating the power sum.