JPH11355066A - Error amplification circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To increase the operating range of in-phase input. A one input terminal 1a with the output end provided with a plurality of error amplifiers 10 ₁ ‥‥ 10 _n that are mutually connected
It was respectively connected to the respective DC shift circuit 12 ₁ ‥‥ through 12 _n of the plurality error amplifier 10 ₁ ‥‥ 10 _n one input terminal of each of the other input terminal 1b respectively DC shift circuit 14 ₁ ‥ ‥ 14 _n via the plurality of error amplifiers 10
It is obtained by respectively connected to the other input terminal of the ₁ ‥‥ 10 _n.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error amplifying circuit used for various signal processing, for example.

[0002]

2. Description of the Related Art Conventionally, an error amplifier circuit as shown in FIG. 3 is used for various signal processing. Referring to FIG. 3, in FIG.
a indicates one input terminal to which one signal is supplied, and connects the one input terminal 1a to the base of the npn transistor 2a.

Reference numeral 1b denotes another input terminal to which the other signal is supplied. The other input terminal 1b is connected to the base of an npn-type transistor 2b, and is connected to the emitters of the transistors 2a and 2b. Point to constant current source 3
, And the transistors 2a and 2b constitute a differential amplifier circuit.

[0004] connected to a power supply terminal 5 to the collector of the DC voltage V _CC of the transistor 4 is supplied with connecting collector of the transistor 2a to the emitter and base of the connection point of the diode-connected pnp-type transistor 4, the The base of the transistor 4 is
And the base of a pnp transistor 6 constituting a current mirror circuit, the collector of the transistor 6 is connected to the power supply terminal 5, and one output terminal 7a is led out from the emitter of the transistor 6.

The collector of the transistor 2b is connected to the connection point between the emitter and the base of the pnp transistor 8 which is diode-connected, the collector of the transistor 8 is connected to the power supply terminal 5, and the base of the transistor 8 is connected to the Connected to the base of a pnp transistor 9 forming a current mirror circuit with the transistor 8;
Connect the collector of this transistor 9 to the power supply terminal 5,
The other output terminal 7b from the emitter of this transistor 9
Is derived.

In such a conventional error amplifying circuit as shown in FIG. 3, one signal is inputted to one input terminal 1a and the other signal is inputted to the other input terminal 1b. output current I ₁ flows through the terminal 7a, when the output current I ₂ to the other output terminal 7b flows can be obtained I ₁ -I ₂ as an error signal.

[0007]

Operating range of the in-phase input斯Ru error amplifying circuit [SUMMARY OF THE INVENTION] is not a full range of power supply voltage V _CC and ground, narrower. Quite narrow for emitter voltage V _BE - particularly transistor base when constructed using bipolar transistors as shown in FIG. The operating range V _com of the common mode input in the error amplifier circuit of FIG.
_V be -α~V _CC -V be + α, and the particular power supply voltage V _CC is lower the operating range V _com narrows significantly the in-phase input.

For example, _Vbe is about 0.7 V, and when the power supply voltage _Vcc is 3 V, the operating range V of the common mode input is Vbe.
_com was about 1.2 V to 2.6 V, which was too narrow for some applications.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to expand the operating range of common mode input with a relatively simple configuration.

[0010]

The error amplification circuit according to the present invention comprises:
A plurality of error amplifiers whose output terminals are connected to each other are provided, and one input terminal is connected to one input terminal of each of the plurality of error amplifiers via a DC shift circuit, and the other input terminal is connected to each other. These are connected to the other input terminals of the plurality of error amplifiers via a DC shift circuit.

According to the present invention, one and the other input terminals are connected to one and the other input terminals of a plurality of error amplifiers via a DC shift circuit, respectively, and the output terminals of the plurality of error amplifiers are connected to each other. Because of the connection, the operating range of the common-mode input of the error amplifier circuit is the sum of the operating ranges of the common-mode inputs of the plurality of error amplifiers, and a wide operating range of the common-mode input can be realized.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an error amplifier circuit according to the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration example of an error amplifier circuit according to the present invention, and FIG. 2 shows a specific configuration example of the error amplifier circuit according to the present invention. 1 and 2
In the figure, the portions corresponding to those in FIG.

[0013] provided an error amplifier 10 ₁ ‥‥ 10 _n of structure shown in more example of n example 3 In one example figure, one and the other output of the n-number of the error amplifier 10 ₁ ‥‥ 10 _n The ends are connected in parallel, and one and the other output terminals 11a and 11b are derived from respective connection points.

In this embodiment, one input terminal 1a to which one signal is supplied is connected to a predetermined DC shift circuit 12 _1.
‥‥ 12 _n and a limiter circuit 13 ₁ ‥‥ 13 _n are connected to one input terminal of each of the _n error amplifiers 10 ₁ ‥‥ 10 _n via a series circuit, and the other is supplied with the other signal. Is connected to a predetermined DC shift circuit 14 ₁ ‥
These are connected to the other input terminals of the _n error amplifiers 10 ₁ ‥‥ 10 _n via a series circuit of # 14 _n and limiter circuits 15 ₁ ‥‥ 15 _n .

In this case, n error amplifiers 10 ₁ ‥‥ 1
DC shift circuits 12 ₁ ‥‥ 12 _n and 14 ₁ ‥‥ 14 _n connected to one and the other input terminals of 0 _{n respectively} have the same configuration and the same DC shift amount.

The n error amplifiers 10 ₁ ‥‥ 1
0 _n limiter circuit 13 ₁ ‥‥ 13 _n and 15 ₁ ‥‥ 15 _n that are connected to one and the other input terminal of each of the to prevent malfunction when there is an input exceeding the operating range of the in-phase input The n error amplifiers 10 ₁ ‥‥ 10 _n are provided so that their respective inputs fall within the operating ranges of the respective in-phase inputs.

In this case, n error amplifiers 10 ₁ ‥‥ 1
The limiter circuits 13 ₁ ‥‥ 13 _n and 15 ₁ ‥‥ 15 _n connected to one input terminal and the other input terminal of 0 _{n respectively} have the same configuration so that the limiter potentials are the same.

In the example shown in FIG. 1, one and the other input terminals 1a and 1b to which one and the other signals are supplied.
To the DC shift circuits 12 ₁ ‥‥ 12 _n and 14 ₁ ‥‥
14 _n , the n error amplifiers 10 ₁ ‥‥ 10
_Since the output terminals of the _n error amplifiers 10 ₁ ‥‥ 10 _n are connected in parallel and connected to one and the other input terminals of _n , the output terminals 11 a and 11 b are derived. The operating range of the in-phase input of the error amplifier circuit is the sum of the operating ranges of the in-phase inputs of the _n error amplifiers 10 ₁ ‥‥ 10 _n , and a wide operating range of the in-phase input can be realized.

FIG. 2 shows a specific example of the example shown in FIG. The example of FIG. 2 uses three error amplifiers having the configuration shown in FIG. 3, sets the power supply voltage V _CC to 3 V, and sets the operating range of the common mode input to 0.
An example in which V is set to V to 2.6 V is shown.

In the example shown in FIG. 2, three error amplifiers 10 ₁ , 10 ₂ and 10 ₃ are provided, and one and the other output terminals of the _three error amplifiers 10 ₁ , 10 ₂ and 10 ₃ are connected in parallel. And one and the other output terminals 11a and 11b are derived from the respective connection points.

The error amplifiers 10 ₁ , 10 ₂ and 10 ₃
Have the same configuration. That is, one input terminal to which one signal is supplied is connected to the base of npn transistor 2a, and the other input terminal to which the other signal is supplied is connected to the base of npn transistor 2b. And 2b are grounded via the constant current source 3 to connect the emitters of the transistors 2a and 2b.
And 2b constitute a differential amplifier circuit.

[0022] connected to a power supply terminal 5 to the collector of the DC voltage V _CC for example 3V of the transistor 4 is supplied with connecting collector of the transistor 2a to the emitter and base of the connection point of the diode-connected pnp type transistor 4 The base of the transistor 4 is connected to the base of a pnp transistor 6 forming a current mirror circuit with the transistor 4, the collector of the transistor 6 is connected to the power supply terminal 5, and the emitter of the transistor 6 is connected to one output terminal. Through one output terminal 11a
Connect to

The collector of the transistor 2b is connected to the connection point between the emitter and the base of the pnp transistor 8 which is diode-connected, the collector of the transistor 8 is connected to the power supply terminal 5, and the base of the transistor 8 is connected to the power supply terminal 5. The transistor 8 is connected to the base of a pnp transistor 9 constituting a current mirror circuit, the collector of the transistor 9 is connected to the power supply terminal 5, and the emitter of the transistor 9 is connected to the other output terminal 11b via the other output terminal. Connect to

[0024] In this example, the base of directly via one input terminal of the error amplifier 10 ₁ transistor 2a without the one input terminal 1a a DC shift providing a DC shift circuit or the DC shift circuit 0 connect, also connect the collector of the transistor 2a to the collector of the npn type transistor 20a constituting the limiter circuit 13 _1, and grounding the emitter of the transistor 20a through the constant current source 3, the base of the transistor 20a 1.
Grounded via a 4V battery 21. In this case, the limiter circuit 13 ₁ is as to limit the 1.4V or less.

Further, directly through the other input terminal of the error amplifier 10 ₁ connected to the base of the transistor 2b without the other input terminal 1b a DC shift providing a DC shift circuit or the DC shift circuit of 0, Further, n that constitute the limiter circuit 15 ₁ to the collector of the transistor 2b
The collector is connected to the collector of the pn transistor 20b, the emitter of the transistor 20b is grounded via the constant current source 3, and the base of the transistor 20b is grounded via the 1.4V battery 21. In this case, the limiter circuit 1
5 ₁ is as to limit the 1.4V or less.

The operating range V _com of the error amplifier 10 ₁ of the in-phase input is _{2V be -α~V CC -V be + α} , the power supply voltage V _CC and 3V, since the limit of 1.4V or less, 1. 4V to 2.6V.

In this embodiment, one input terminal 1a
Base DC shift amount of transistors - connected to the base of a pnp type transistor 22a constituting the DC shift circuit 12 ₂ of the emitter voltage V _be for example, about 0.7 V, the emitter grounded of the transistor 22a, the transistor 22a connecting the collector to the base of the transistor 2a to the collector of the transistor 22a through the one input terminal of the error amplifier 10 ₂ as well as connected to the power supply terminal 5 via a constant current source 23a.

The collector of the transistor 22a has a limiter circuit 13 with an upper limit of 1.4V and a lower limit of 0.7V.
₂ is connected to the collector of a pnp transistor 24a, the emitter of which is grounded,
The base of this transistor 24a is a battery 21 of 1.4V.
To ground via Also a collector connected to the error amplifier 10 _{and second} transistor 2a to the collector of the npn type transistor 25a constituting the limiter circuit 13 _2,
The emitter of the transistor 25a is grounded via the constant current source 3, the base of the transistor 25a is connected to the collector of the pnp transistor 26, and the collector of the transistor 26 is connected to the power supply terminal 5 via the constant current source 27. The emitter of the transistor 26 is grounded, and the base of the transistor 26 is connected to a 0.7 V battery 2
Ground via 8.

Further, the base DC shift input terminal 1b of the other transistor - connected to the base of a pnp type transistor 22b constituting the DC shift circuit 14 ₂ of the emitter voltage V _be for example about 0.7 V, the transistor grounding the emitter of 22b, the base of transistor 2b of the collector of the transistor 22b via the other input terminal of the error amplifier 10 ₂ with connecting collector of the transistor 22b to the power supply terminal 5 via a constant current source 23b Connecting.

The collector of the transistor 22b is connected to a limiter circuit 15 having an upper limit of 1.4V and a lower limit of 0.7V.
₂ is connected to the collector of a pnp transistor 24b, and the emitter of the transistor 24b is grounded.
The base of this transistor 24b is a battery 21 of 1.4V.
To ground via Also a collector connected to the error amplifier 10 _{and second} transistor 2b to the collector of the npn-type transistor 25b constituting the limiter circuit 15 _2,
The emitter of the transistor 25b is grounded via the constant current source 3, and the base of the transistor 25b is connected to the collector of the transistor 26.

The DC shift amount of the error amplifier 10 ₂ of one and the other DC shift circuit provided on the input side of the 12 ₂ and 14 ₂ are transistor base - emitter voltage V _be
About 0.7 V, since the upper limit of the limiter circuit 13 ₂ and 15 ₂ each of the limit is a lower limit at 1.4V is a 0.7 V, the operating range V _co of the error amplifier 10 _{and second-phase} input
_m is 0.7V to 1.4V.

In this embodiment, one input terminal 1
base DC shift amount of transistors a - DC shift circuit 1 twice for example about 1.4V emitter voltage V _be
Connected to the base of a pnp type transistor 29a constituting the two _3, by grounding the emitter of the transistor 29a,
The collector of this transistor 29a is connected to the base-emitter connection point of a diode-connected pnp transistor 30a. The collector of this transistor 30a is connected to the power supply terminal 5 via a constant current source 31a. It is connected to the base of the transistor 2a through one input terminal of 10 ₃ .

Further, pn to limit the collector of the transistor 29a constitutes a limiter circuit 13 ₃ of 0.7V
Connected to the collector of p-type transistor 32a, the emitter of transistor 32a is grounded, and the base of transistor 32a is grounded via 0.7V battery 28.

Further, the other input terminal 1b DC shift amount based transistor - p constituting the DC shift circuit 14 ₃ twice, for example about 1.4V emitter voltage V _be
The transistor 29b is connected to the base thereof, the emitter of the transistor 29b is grounded, the collector of the transistor 29b is connected to the base-emitter connection point of the diode-connected pnp transistor 30b, and the collector of the transistor 30b is connected to a constant current. the collector of the transistor 30b as well as connected to the power supply terminal 5 via a source 31b via the other input terminal of the error amplifier ₁₀₃ is connected to the base of transistor 2b.

Further, pn to limit the collector of the transistor 29b constitutes a limiter circuit 15 ₃ of 0.7V
Connected to the collector of p-type transistor 32b, the emitter of transistor 32b is grounded, and the base of transistor 32b is grounded via 0.7V battery 28.

The DC shift amount of the one of the error amplifier ₁₀₃ and provided to the other input side DC shift circuit 12 ₃ and 14 ₃ the base of the transistor - is 2-fold to about 1.4V emitter voltage V _be , the limiter circuit 13 ₃ and 15
Since the upper limit of ₃ of each limit is a 0.7 V, the operating range V _com of the common mode input of the error amplifier 10 ₃ 0.0
V to 0.7V.

The operating range V _com of the in-phase input of the error amplifier circuit shown in FIG. 2 is the three error amplifiers 10 ₁ , 1.
The sum of the operating ranges of the in-phase inputs of 0 ₂ and 10 ₃ (0.0V to
0.7V) + (0.7V-1.4V) + (1.4V-
2.6V), that is, 0.0V to 2.6V. Therefore, according to this example, a wide operating range of the common mode input can be realized.

This embodiment is advantageous when the power supply voltage V _CC is low as described above and this error amplifier circuit is constituted by using a bipolar transistor. This arrangement also has the advantage that no particularly complicated circuit is required. There is.

It is to be noted that the present invention is not limited to the above-described example, but may adopt various other configurations without departing from the spirit of the present invention.

[0040]

According to the present invention, one and the other input terminals are respectively connected to one and the other input terminals of a plurality of error amplifiers via a DC shift circuit, and the output terminals of the plurality of error amplifiers are connected to each other. , The operating range of the common-mode input of the error amplifier circuit according to the present invention is the sum of the operating ranges of the common-mode inputs of the plurality of error amplifiers, and there is an advantage that a wide common-mode input operating range can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating an example of an embodiment of an error amplifier circuit of the present invention.

FIG. 2 is a connection diagram showing a specific example of FIG.

FIG. 3 is a connection diagram illustrating an example of a conventional error amplifier circuit.

[Explanation of symbols]

1a, 1b input terminal, 10 ₁ ‥‥ 10 _n error amplifier, 11a, 11b output terminal, 12 ₁ ‥‥ 1
2 _n , 14 ₁ ‥‥ 14 _n ‥‥ DC shift circuit, 13 ₁ ‥
‥ 13 _n , 15 ₁ ‥‥ 15 _n ‥‥ limiter circuit

Claims (2)

[Claims] A plurality of error amplifiers having output terminals connected to each other are provided, and one input terminal is connected to one input terminal of each of the plurality of error amplifiers via a DC shift circuit. Wherein the input terminals are connected to the other input terminals of the plurality of error amplifiers via DC shift circuits, respectively. 2. The error amplifier circuit according to claim 1, wherein limiter circuits are provided between the DC shift circuit and one input terminal and the other input terminals of the plurality of error amplifiers, respectively. Error amplification circuit.