JPH11338833A - Multiprocessor type controller and scalable controller system - Google Patents

Abstract

(57) [Summary] To increase the independence between processors in interrupt notification, and to achieve both the commonality of programs in initialization processing and the independence between processors. In a multiprocessor controller having a plurality of processors and a shared memory, a comparison is made between a boundary register for holding a boundary of an area obtained by dividing the shared memory for each processor, and an access address of the shared memory and a boundary register. And a memory control unit for restricting the access of the processor based on the result of comparison by the comparator, an interrupt control unit for notifying an interrupt according to a mask register for masking an interrupt factor for each processor, and an identification for returning different values depending on the processor of the reading source. It has a register. According to the present invention, the interrupt selection notification increases the independence of the processor while protecting the area of the shared memory in the normal processing, and the startup processing can be shared by the identification register.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an industrial controller, and more particularly to a controller having a multiprocessor configuration.

[0002]

2. Description of the Related Art A conventional industrial controller has a configuration in which a plurality of network boards are connected to one CPU to perform data communication with a control target. The network board includes a network processor that performs network processing, and temporarily stores data from the network in a memory on the network board. Thereafter, the fetched data is transferred to the main memory of the CPU via the system bus, and an interrupt is given to the CPU to notify reception of data from the network. In transmission, a message or control data for a controlled node on the network is formed on the main memory of the CPU, and an interrupt is given to the network processor. The interrupted network processor fetches the data in the main memory into the network board and transmits the data to the network via the communication LSI.

In such a conventional industrial controller, a plurality of network boards are required to support a plurality of networks, and the controller is increased in size. It is conceivable to share the main memory of the network board and the memory of the network board. However, the CPU and the network processor are premised on single processor operation, and do not have a configuration control function, a cache coherency function, and an interrupt control function in a multiprocessor environment.

On the other hand, in a controller premised on use in a multiprocessor type, a plurality of processors access a shared memory. The shared memory is divided into areas accessed by each processor. A program executed by each processor accesses a predetermined area to realize exclusiveness between processors in a shared memory. Further, the interrupt generated by the controller is notified to each processor, and each processor executes an interrupt routine for determining the cause of the interrupt and performing a predetermined process. In the initialization of the controller, the processor executes an initialization program stored at a unique address. Since the initialization of the multiprocessor type controller is performed by the specified processor, the setting of the access area of the shared memory is performed after the initialization is completed.

[0005]

Since the current controller is operated on a single processor, it is difficult to operate the controller in a multi-processor configuration even if only a plurality of controllers are installed. In order for a single-processor controller to operate in a shared-memory multiprocessor configuration, the memory space used must be independent for each processor to prevent damage to other processors in the event of a failure. is there. On the other hand, when it is not convenient for each processor to perform processing independently, such as configuration control, or when a large number of similar processes are performed like a controller, the memory space is divided for each processor. It is necessary to coordinate each other's processing for the same processing. Further, in the case where functions are assigned to each processor, if an interrupt enters all processors, a heavy load is imposed on a controller performing critical processing, and a situation in which time constraints cannot be satisfied may occur.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems, to enhance the independence between processors in interrupt notification, and to make the initialization program compatible with independence between processors in initialization processing. And

[0007]

According to the present invention, there is provided a multiprocessor type comprising a plurality of processors for executing an initialization program from a specific address when a power is turned on, and a shared memory accessed by the plurality of processors. The controller divides the shared memory into areas that are occupied and accessed by each processor, and compares a plurality of boundary registers that hold the boundaries of the divided areas with the addresses at which the processors access the shared memory and the contents of the boundary registers. A memory controller that enables or disables access based on the result of address comparison by the comparator to limit access to each area of the shared memory from the processor, and masks an interrupt factor for each processor to generate an interrupt. A plurality of mask registers for setting information that determines And an interrupt control unit for notifying the processor of an interrupt in accordance with the information of the interrupt notification destination held in the register, and a means for reading out from all processors at the same address and returning different values depending on the read-out processor. .

[0008]

FIG. 1 shows an embodiment of a controller according to the present invention. In this embodiment, three processors 10
Communication LSI for controlling communication between 0, 101, 102, shared memory 112, and networks 140, 141, 142
109, 110, and 111, and a system control LSI 103 connected to them. The system control LSI 103 according to the present embodiment includes a processor control unit 104,
A register control unit 105, an interrupt control unit 106, a memory control unit 107, and a network control unit 108;
By controlling the communication LSIs 109, 110, and 111, communication is performed with other devices such as sensors and actuators and controllers via the networks 140, 141, and 142, and control information is exchanged. The control information is information from the sensor and a start command of the actuator. The controller obtains the state of the controlled device from the sensor as control information via the networks 140, 141, and 142, based on the information from the sensor, activates an actuator connected to the network, and receives information from another controller. Instructs to start network control. Upon receiving the instruction, the other controller acquires sensor information of the network under control, and performs processing control of the actuator.

The processor control unit 104 controls the processor 1
Access signal lines 113, 1 from 00, 101, 102
The register control unit 105 and the memory control unit 1 respond to requests for reading data and writing values by
07, reading of data and writing of values to the network control unit 108 are performed using the access signal lines 119, 120, and 1
21. The output destination is determined by the access signal line 11
The determination is made based on the address signals 3, 114 and 115. Responses from the register control unit 105, the memory control unit 107, and the network control unit 108 are received by the access signal lines 119, 120, and 121, and are output by the access signal lines to the access source processor to request the read data. Is returned to the selected processor.

[0010] The register control unit 105 is a memory control unit 10
7, connected to the network control unit 108, the interrupt control unit 106, and the interrupt factor lines 123, 125, 139,
A request to read data and a request to write a value from the processor control unit 104 is received by an access signal line 119,
Execution is performed on the internal register, and a response to the request is transmitted to the processor control unit 1 through the access signal line 119.
Return to 04. In addition, memory control unit, network control unit,
An interrupt notification from the outside is held in an internal register as an interrupt cause, an internally generated inter-processor interrupt cause is held, and an interrupt request is sent to the interrupt control unit 1.
Request 06.

The interrupt control unit 106 has an interrupt notification line 1
39, 132, 133, the register control unit 1
05, memory control unit 107, network control unit 108
Are connected, and the interrupt request is sent to the interrupt signal lines 116, 1
The information is transmitted to the processor through 17, 118. The interrupt notification lines 139, 132, and 133 are signal lines for transmitting an interrupt to the interrupt factor register, and transmit information from the interrupt source to the register. Also, the interrupt signal lines 116 and 11
Reference numerals 7 and 118 denote signal lines for transmitting the occurrence of an interrupt from the interrupt source to the interrupt control unit, and are signal lines for issuing an interrupt request to the processor.

When an interrupt occurs, the processor checks the source of the occurrence in the interrupt factor register in the register control unit, and then checks the detailed cause in the interrupt factor register in the source.

The memory control unit 107 is connected to the access signal line 1
30 and 120 respectively,
And a request to read data and write a value from the processor control unit 104, execute these requests to the shared memory 112 through the access signal line 131, and receive a response. Then, the data read from the shared memory is returned to the requesting network control unit 108 or the processor control unit 104. Further, it holds the cause of the interrupt generated inside the memory control unit, notifies the register control unit of the occurrence of the interrupt, and requests an interrupt to the interrupt control unit.

For an interrupt from outside the system, an interrupt factor line 122 is input to the register control unit 105 from outside the system control LSI 103, and an external interrupt notification line 138 is input to the interrupt control unit 106. .

The network control unit 108 reads data from the communication LSIs 109, 110, and 111 via the access signal line 134, and reads data from the memory control unit 107 via the access signal line 130 in response to a value write request. Request and write request of value. The data read by the read request is returned to the requested communication LSI. Further, the network control unit 108 receives a request and returns a response to the access from the processor control unit 104 via the access signal line 121. The communication LSI is controlled by writing and reading to and from the communication LSI, and the transmission and reception data of the network stored in the shared memory 112 is transmitted to each of the processors 100 and 10.
A communication LSI controlled by the communication controller 102 reads out from the shared memory 112 and outputs it to the network. The data received from the network is temporarily written into the shared memory by the communication LSI, and is read out by the processor. In addition, the interrupt notification lines 135, 136, and 137 accept the occurrence of an interrupt from the communication LSI, and hold the cause of the interrupt from the communication LSI and the cause of the interrupt generated in the network control unit.
It notifies the register control unit 105 of the occurrence of the interrupt and requests the interrupt control unit 106 for the interrupt.

The access signal lines 113, 114, 115,
Reference numerals 119, 120, 130, 131, and 134 transfer a request and a response between the units, and provide an address signal indicating the address of a read or write access.
In addition to the write data signal, it includes a signal indicating the type of access request (write or read), and a control signal such as authentication of the request being accepted. Further, the processor control unit 1
The access signals 119 and 120 from 04 include a signal indicating the requesting processor in addition to the above-described signals. Then, to the access signal 134 from the communication LSI, a signal indicating the request source communication LSI and a signal indicating the request destination communication LSI are added. An address signal, a signal indicating a type of request, data to be written, and a signal indicating a request source processor or a communication LSI are passed from the request source to the request destination. The signal passed from the request destination to the request source is a signal indicating the read data, the authentication signal, and the request destination communication LSI.

FIG. 2 shows the details of the register control unit 105. In the register control unit 105, the shared memory 112 from the plurality of processors 100, 101, and 102 connected thereto.
Control access to. Register control unit 105
Are the boundary registers 200 and 201 and the mask register 20
2, 203, 204, interrupt notification registers 205, 20
6, 207, an interrupt factor register 208 and an identification register 209.

From the processors 100, 101, 102,
Writing and reading of a value are performed on the access signal line 119, and the written value is
12 to the memory control unit 107. The processors 100, 101, and 102 divide the shared memory into areas for each processor and use them.

In order to set boundaries of individual dedicated areas for each processor on the shared memory, boundary registers are prepared by at least the number of processors 100, 101, and 102 connected to the system control LSI 103-1. In the present embodiment, at least two boundary addresses need to be set because three processors define three areas for exclusively using the shared memory. Therefore, a boundary address for each processor is set in the two boundary registers 200 and 201. These boundary registers 20
The values of 0 and 201 and the function of the memory control unit determine the processors for which access to the three areas is prohibited and the processors to which access is permitted. The boundary address signal lines 211 and 212 include signal lines indicating whether the value written in the boundary register is valid. This realizes exclusiveness between the processors with respect to access to the shared memory.

Each of the mask registers 202, 203 and 204 has the configuration shown in FIG. Mask register 20
Reference numerals 2, 203, and 204 include an interrupt mask bit 900 from the network control unit, an interrupt mask bit 901 from the memory control unit, an external interrupt mask bit 903, and a mask bit 904 for an inter-processor interrupt.
The mask registers 202, 203, and 204 correspond to the processors 100, 1 connected to the system control LSI 103.
01 and 102 are prepared, values are written and read from the processor control unit 104 by the access signal line 119, and the written values are written by the interrupt control unit 1 by the interrupt mask signal lines 213, 214 and 215.
06 is output. And each interrupt mask bit is 1
When, the interrupt of the corresponding interrupt factor for the processor corresponding to each mask register is masked.

Interrupt notification registers 205, 206, 20
Reference numeral 7 performs writing and reading on the access signal line 119. By writing a value to the interrupt notification registers 205, 206, and 207, the cause of the generated interrupt is notified to the interrupt factor register 208 through the interrupt factor lines 216, 217, and 218, and the interrupt request is sent to the interrupt request line 2
19, 220 and 221. These interrupt request lines 219, 220, and 221 form one interrupt request line 139 by a logical sum 210. Interrupt request line 13
9 outputs an interrupt request to the interrupt control unit 106 when at least one of the interrupt request lines 219, 220, and 221 requests an interrupt.

FIG. 3 shows details of the interrupt factor register 208. The interrupt factor register 208 stores the interrupt factor line 21
6, 217, 218, 122, 123, and 125 consist of interrupt factor bits corresponding to the information transmitted.
Network interrupt factor bit 300 is interrupt factor line 1
25, the memory controller interrupt factor bit 301 corresponds to the interrupt factor line 123, and the external interrupt factor bit 302 corresponds to the interrupt factor line 122 on a one-to-one basis. The interrupt between the processors is determined by the inter-processor interrupt factor bit 30.
3 and 304 correspond to the interrupt factor line 216, the inter-processor interrupt factor bits 305 and 306 correspond to the interrupt factor line 217, and the inter-processor interrupt factor bits 307 and 308 correspond to the interrupt factor line 218. I do. These interrupt factor bits 300 to 308 hold their values when the corresponding interrupt factor line becomes 1. The value of the interrupt factor bit of the interrupt factor register 208 can be written and read by the access signal line 119, and continues until the value 1 is written to the bit position to be cleared from the access signal line 119.

The identification register 209 is connected to the access signal line 1
19, writing and reading of a value are performed. The value read from the identification register 209 corresponds to the access signal line 11
Different values are output by the processors that read based on the signals that identify the reading sources of No. 9 respectively. For example,
The value 2 is output when read from the processor 100, and the value 1 when read from another processor 101.
Is output, and when it is read from another processor 102, the value 0 is read. Note that the value read from the identification register 209 may be any value as long as the processor can be uniquely specified by the read value.

FIG. 4 shows the details of the memory control unit 107.
The memory control unit 107 includes two comparators 400 and 401 corresponding to the boundary registers 200 and 201, an access control unit 402 that controls access to the shared memory 112 based on the comparison result of the comparators, and an interrupt factor register 403.
Consists of

The comparators 400 and 401 compare the address of the access signal line 120 from the processor control unit 104 with the addresses of the boundary address lines 143 and 124 which are signal lines from the boundary registers 200 and 201. Comparator 4
Reference numerals 00 and 401 denote a signal indicating invalidity when the boundary address line indicates that the set address is invalid, and a comparison result when the boundary address line indicates validity.
05 to the access control unit 402. Therefore, the comparison results output to the comparison result lines 404 and 405 are as follows: when the comparison is valid and the access address is greater than or equal to the boundary address, when the comparison is valid and the access address is smaller than the boundary address, and when the comparison is invalid. There are three types.

The access control unit 402 outputs a request for the shared memory to the access signal line 131, and outputs a response of the access signal line 131 from the shared memory to the access signal lines 120 and 130 according to the access source. The selection of the access signal lines 120 and 130 for outputting a response is performed by using the access signal line 130 when the network control unit 108 is the access source and by using the access signal line 120 when the processor control unit 104 is the access source.
Select Requests to the shared memory 112 are permitted or deterred according to the contents of the comparison result lines 404 and 405 and the information of the access source processor of the access signal line 120. The determination of permission and inhibition is shown in the table shown in FIG. When suppressing access to the shared memory 112, the access control unit 402 does not output the request to the access signal line 131 if the request of the access source processor is a write, and responds to the processor control unit by the access signal line 120. Is returned in place of the shared memory 112. In the case where access is inhibited and access is read, a read request is output to the access signal line 131 and the value of the shared memory 112 is read.

In this embodiment, the boundary address lines 143, 1
24 includes a signal indicating whether the contents of the boundary registers 200 and 201 are valid or invalid. The designation of a boundary address for distinguishing an accessible area for each processor indicates valid / invalid. Information is stored in the memory control unit 10
7 as a register, and it is also possible to instruct the validity or invalidity of the comparison result of the comparators 400 and 401 based on the value of this register. Further, instead of the method of indicating whether the boundary address is valid or invalid, the permission / inhibition determination function itself of the access control unit 402 can be made valid or invalid based on the information held in the register. Further, when all the bits of the two boundary addresses indicate 0, the access from the three processors 100, 101, and 102 is enabled in all the address areas of the shared memory 112.
The validity of the set address can be indicated by a special address.

The interrupt cause register 403 in FIG. 4 is constituted by interrupt cause bits corresponding to the cause of the interrupt. Maintain the cause of the failure. As a failure, the shared memory 11
2 has been inhibited or illegal data has been read from the shared memory 112 (parity error or E
(Detected by CC error). The interrupt is detected by the access control unit 402, and the occurrence of memory access inhibition of the processor 100 is performed by using the interrupt notification line 406, and the processors 101 and 102 use the interrupt notification lines 407 and 408, respectively. The interrupt notification line 409 is used to read the transmitted and correctable illegal data, and the interrupt notification line 410 is used to read the uncorrectable illegal data.

The access control unit 402 holds the address, data, and access source accessed when an interrupt occurs.
Each interrupt notification line 406, 407, 408, 409, 41
0 is ORed 411 into the interrupt notification line 123,
Interrupt notification lines 406, 407, 408, 409, 410
Becomes effective when notifying the interrupt, and is notified to the register control unit 104. When at least one of the interrupt bits in the interrupt notification register 403 indicates that an interrupt has occurred, the interrupt control unit 106
Request notification of an interrupt to the processor. The interrupt factor bit of the interrupt factor register 403 is cleared by the access signal line 120.

FIG. 6 shows details of the network control unit 108. The network control unit 108 controls the access control unit 60
1 and an interrupt factor register 600. In response to a data request from the processor control unit 104 via the access signal line 121, the access control unit 601 communicates via the access signal line 134 with the communication LSI 109, 110, 1
11 to the access signal line 1 for this request.
34 is returned to the access signal line 121.
In addition, the communication LSIs 109 and 11 via the access signal line 134
0, 111 outputs a request to the shared memory 112 to the access signal line 130, and returns a response from the memory control unit 107 to the requesting communication LSI via the access signal line 134. Each communication LSI has an access signal line 134
It is determined whether or not the request on the access signal line 134 is a request for itself from the signal indicating the request destination communication LSI.

The interrupt factor register 600 includes interrupt factor bits for the interrupt notification lines 135, 136, 137, and 125. When an interrupt is notified on the corresponding interrupt notification line, the corresponding interrupt factor bit becomes 1. The interrupt factors are an interrupt from the communication LSI and an illegal access in the access control unit 601. For the interrupt from the communication LSI, the detailed cause is held in the interrupt factor register in each communication LSI, and the processor that has accepted the interrupt reads the interrupt factor register in the communication LSI that generated the interrupt, and responds according to the contents. Perform the following processing. An illegal access in the access control unit 601 is notified to the interrupt factor register 600 and the register control unit 105 on the interrupt notification line 125 by a parity error of the access signal line 134. Reading and writing of the value of the interrupt factor register 600 and clearing of the bit are performed via the access signal line 121.

The interrupt control unit 106 includes the register control unit 1
05, memory control unit 107, network control unit 10
8, and the respective external interrupt request lines 139,
At 132, 133, and 138, an interrupt request is accepted. The accepted interrupt request is sent to the interrupt mask lines 126 and 12
7 and 128, the mask is performed using interrupt mask information for each processor input from the register control unit. The interrupt mask information of the interrupt line to the processor 100 is passed through an interrupt mask line 126, and the interrupt mask information 127 of the interrupt line to another processor 101 is the interrupt mask line 1
The interrupt mask information of an interrupt line to another processor 102 is passed on an interrupt mask line 128. Based on the masked interrupt request, interrupt line 11
6, 117, 118, the processors 100, 101, 1
02 is interrupted. Therefore, even if the masked interrupt is notified to and accepted by the interrupt control unit 106,
No interrupt to the processor occurs.

The processors 100 and 101 control the communication LSIs 109 and 110, respectively, and exchange of monitoring data that does not require real-time processing is performed by the processor 102. Interrupts in the system are mainly performed by the processor 10.
The interrupt processing performed in step 2 will be described. in this case,
Due to the functions of the interrupt mask registers 202 to 204 and the interrupt control unit 106, the interrupts of the network control unit 108 and the memory control unit 107 are provided only to the processor 102, and the external interrupt and the interrupt between the processors are provided to all processors. For this reason, the value 0 × 3 (allows only external interrupts and interrupts between processors) is set in the mask registers 202 and 203 of the register control unit 119, and the value 0 × F (all interrupts are set in the mask register 204). Notify the corresponding processor). With this setting, the external interrupt and the interrupt between the processors are notified to all the processors, and the memory control unit 107 and the network control unit 108 have the interrupt control unit 106
Are masked by the mask registers 202 to 204,
The interrupt request is notified only to the processor 102. With this setting, the processor 100 that controls the communication LSI,
When an interrupt occurs at 101, an external interrupt and an inter-processor interrupt occur. Then, the processors 100 and 101
Can concentrate on the control of the communication LSIs 109 and 110 that involve reading / writing from / to the shared memory 112, and are less likely to be affected by the time of failure processing performed by the other processors 102.

Generally, when an interrupt process is entered, the processor is occupied for the interrupt process. However, external interrupts are generally special, such as when the system is turned off.Inter-processor interrupts are used when another processor communicates with a processor whose interrupt is masked. Not large compared to interrupts from network control and memory control. Also, if there is almost no external interrupt, the process sharing between the processors is divided to make it difficult for interrupts between processors to occur. The execution time of the process can be accurately estimated. Therefore, the processor 100,
Since it is possible to accurately estimate the processing time of the communication LSIs 109 and 110 by the network 101, the network 140, 1
The hard real-time property of 41 processing can be guaranteed.

When an interrupt process from the memory control unit 107 or the network control unit 108 occurs, the processor 102 that has received the interrupt processes the processor control unit 10.
4 via the access signal line 120 to the memory controller 1
07, the comparators 404, 4
01, the instruction to invalidate the comparison result of the access address with the boundary registers 200 and 201 is given, and after the interruption processing, the instruction is given to the access control unit 402 to make the comparison result valid again. As a result, in the interrupt processing, processing common to the entire system, such as failure recovery, is not provided for each processor, and processing can be performed using a common memory area. When an interrupt occurs between the processors, the interrupt is not simply notified to the other processors, and the comparison result is kept valid, thereby maintaining the independence of the processing for each processor. Can be performed.

The independence of the shared memory area used between the processors by the boundary registers 200 and 201 is necessary mainly in normal processing, and the start-up processing is less necessary because common processing is executed between the processors. This is because there are many initialization processes commonly performed throughout the system, such as system configuration control, during the startup process.
Therefore, an initialization program composed of inter-processor common processing and processor-specific processing is arranged on the shared memory. It is assumed that the initialization program is arranged at an address where the processor first reads data after the power is turned on. Further, when accessing the shared memory 112, the boundary addresses are set in the boundary registers 200 and 201, and until the boundary address becomes valid, all processors can access the shared memory 112 without restriction according to the settings shown in FIG.

When the power is turned on, the processor reads the initialization program from the start address, and reads the identification register 209 by a process commonly performed between the processors.
Since a specific value is read for each processor by the function of 209, the process branches to processing uniquely executed by the processor according to the read value. The boundary register 20 restricts access to the shared memory 112 for each processor.
The settings of 0 and 201 are performed at the end of the processing commonly performed between the processors. Therefore, execution of the processing commonly performed between the processors can be executed by the same initialization program by each processor. The boundary register may be set after the processing of the entire initialization program is completed, or the initialization program may be assigned to another address map and a read-only memory dedicated to the initialization program may be used for the system. The dedicated memory is not required for each processor, and only one dedicated memory is required for the system.

In the system according to the present embodiment, the controller 1 for the controlled device using the network 141
After the process of 03 is completed, the control of the controlled device using the network by another controller is activated via the network 140. Therefore, the controller 103
Guaranteeing the real-time property of the processing of other controllers. Also, if the controlled device expands the conventional processing and needs new control after the control of another controller, another new controller for controlling the sensors and actuators related to the expanded processing can be added. Even if the system is expanded, it is possible to expand the system while guaranteeing the real-time performance of the entire system.

[0039]

As described above, the boundary register and the memory control unit, the mask register and the interrupt control unit protect the area of the shared memory in the normal processing, and notify the processor 100, 101, 102
Independence, and real-time processing of each processor can be guaranteed. By the identification register and the initialization program, common processing can be achieved between the processors at the time of startup.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing details of a register control unit of the present invention.

FIG. 3 is a diagram showing details of an interrupt factor register in the register control unit of the present invention.

FIG. 4 is a diagram showing details of a memory control unit of the present invention.

FIG. 5 is a diagram showing details of an access control unit in the memory control unit of the present invention.

FIG. 6 is a diagram showing details of a network control unit of the present invention.

FIG. 7 is a diagram showing details of a mask register in the register control unit of the present invention.

[Explanation of symbols]

100, 101, 102: Processor, 104: Processor control unit, 105: Register control unit, 106: Interrupt control unit, 107: Memory control unit, 108: Network control unit, 109, 110, 111: Communication LSI, 112
... Shared memory, 200, 201 ... Boundary register, 20
2, 203, 204: mask register, 205, 20
6,207 ... interrupt notification register, 209 ... identification register, 400,401 ... comparator, 208,403,600
... Interrupt factor register.

Continued on the front page (72) Inventor Koji Matsuda 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant, Hitachi, Ltd. (72) Inventor Kenichi Kurosawa 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture (72) Inventor Yoshiaki Takahashi 5-2-1, Omika-cho, Hitachi City, Ibaraki Pref.

Claims (4)

[Claims] A plurality of processors having a function of executing an initialization program of a specific memory address immediately after power-on; a shared memory accessed by the plurality of processors; and a shared memory for each of the plurality of processors. A plurality of boundary registers for setting an address to be divided into regions; a comparator for comparing an access address to the shared memory from the plurality of processors with a content of the plurality of boundary registers; A controller having a memory control unit for restricting access to the area of the shared memory from the plurality of processors; a plurality of mask registers for each of the plurality of processors for setting mask information for each interrupt factor; Masks the interrupt to the processor according to the mask information from the mask register. Includes an interrupt controller, the mask information set in the mask register, a multi-processor controller, characterized in that masks interrupts for said plurality of processors. 2. The multiprocessor type controller according to claim 1, further comprising an identification register for returning a different value for each processor in response to reading from a specific processor, wherein the processor stores the value in the shared memory after power-on. A multiprocessor-type controller for executing a specified initialization program and reading specific values of different processors from the identification register by the initialization program. 3. A system control LSI connected to a plurality of processors, a shared memory accessed by the plurality of processors, and a communication control means for connecting to a network, wherein: An identification register that returns a different value for each processor; a plurality of boundary registers for setting an address for dividing the shared memory into areas for the plurality of processors; an access address to the shared memory from the plurality of processors; A comparator for comparing the contents of the plurality of boundary registers with the contents of the plurality of boundary registers; a memory control unit for restricting access to the area of the shared memory from the plurality of processors based on a result of the comparator; A plurality of mask registers for each of the plurality of processors; According mask information from the register, with an interrupt control unit for masking an interrupt to the processor, the mask information set in the mask register, the system control LSI, characterized in that masks interrupts for said plurality of processors. 4. A plurality of multiprocessor controllers according to claim 2, a plurality of networks connected to the plurality of controllers, a personal computer having a display device, a plurality of sensors and a plurality of actuators, and a controlled object. In a control system including devices, the plurality of controllers are connected to the plurality of sensors and the plurality of actuators by at least one control network among the plurality of networks, and the plurality of controllers are connected to the plurality of controllers. The plurality of controllers are connected to each other by at least one inter-controller network, and the plurality of controllers are connected to the monitoring terminal by at least one monitoring network of the plurality of networks; The controller and the state of the sensor and the actuator connected to the controller are monitored by the monitoring terminal, and the network processing of the control network of the plurality of at least one controllers is completed, whereby the at least one controller is configured by the controller A control system in which at least one other controller of the controllers is notified by an inter-controller network, and activation of a control network of the at least one other controller is performed.