JPH11326458A - Semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pin electronics circuit of a semiconductor testing device in which a smooth change-over between a tester-pin driver and a high voltage driver circuit is realized. SOLUTION: In a pin electronics circuit of a semiconductor testing device, which is equipped with drivers of two systems, namely, a test waveform output from a high-speed tester-pin driver DR1 by which a normal test waveform is outputted and a high-voltage driver 50 by which a prescribed uniform high voltage is generated and outputted, and also which is equipped with an output form by which either of both drivers is switched on and supplied to an IC pin of DUT, a means, by which an output voltage, generated and outputted by the high-voltage driver 50 by which a prescribed uniform high voltage is generated and outputted, can be controlled from the outside, is installed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pin test circuit in a pin electronics circuit of a semiconductor test apparatus having a high voltage driver in the pin electronics. In particular, it relates to switching between a high-voltage driver and a normal high-speed driver.

[0002]

2. Description of the Related Art With regard to the prior art, an example of a conceptual configuration in which pin electronics of one tester channel having a high-voltage driver shown in FIG. 5 and a high-voltage driver are provided, and a switching operation of a control switch shown in FIG. This will be described below with reference to a chart. Since the semiconductor test apparatus is well-known and well-known in the art, the description of the configuration of the entire system is omitted.

The configuration shown in FIG. 5 will be described. In the configuration example of FIG. 5, the tester pin driver DR1, the matching resistor R1, the comparator CP2, and the control switch S2
And a high-voltage driver circuit 50. In this figure, the signal path output from the tester pin driver DR1 is the first line L2, the signal path connected to the DUT IC pin is the second line L4, and the signal on the first line L2 is An output waveform PAT1, a signal on the second line L4 is an output waveform PAT3, and a signal at an output terminal of the amplifier A11 is an output waveform PAT2.

A tester pin driver DR1 receives a test pattern from a pattern generator PG and supplies a high-speed predetermined pulse signal to a DUT, as is well known in a semiconductor test apparatus. A high-level signal is generated and a voltage waveform signal having a predetermined amplitude, which defines a low level of the output signal by setting VIL, is output. The matching resistor R1 connected in series to the output terminal is a resistor for matching with the line impedance.
Some are built into the driver DR1.

The comparator CP2 receives an output signal from the DUT and supplies a data signal converted to a logic level at a predetermined threshold voltage to a digital comparator, as is well known in a semiconductor test apparatus, and uses the data signal for quality determination. Is done.

A reed relay is generally used for the control switch S2 in consideration of the condition of the ON resistance and the condition of the capacitance.

The internal configuration of the high-voltage driver circuit 50 includes control switches S1 and S3 and an amplifier A11. This is provided corresponding to a DUT requiring a high voltage, and is used, for example, for a flash memory device test or the like. This high-voltage driver circuit 50 is, for example, +1
Although the driver can generate a high voltage of 5 V, the slew rate of the generated voltage does not require high speed. On the other hand, the voltage generated by the high-speed tester pin driver DR1 is a high-speed driver that can generate only a low voltage of, for example, about +8 V, but requires an ultra-high-speed operation. The amplifier A11 is an amplifier that amplifies the input signal by a factor of two and outputs the buffer, and the control switches S1 and S3 are connected to the first line L2 and the second line L4
And a control switch for separating the amplifier A11 from the amplifier A11.
When supplying a double amplified high voltage to the DUT,
The control switches S1 and S3 are turned on, and the control switch S2 is turned off.

Next, a switching operation and a problem at the time of switching will be described with reference to a time chart of FIG. Here, it is assumed that the high level of the output waveform PAT1 is 6V and the high voltage driver circuit 50 generates 12V.
Further, as an initial state, the control switch S2 is in an ON state,
It is assumed that the control switches S1 and S3 are off.

In FIG. 6A, the tester pin driver DR1 generates a pattern of the output waveform PAT1 so that a high level (6 V) is output constantly.

First, when the voltage output to the second line L4 is 6
A case where switching control is performed from V to 12 V will be described.
The condition in which both the output of the tester pin driver DR1 and the output of the high-voltage driver circuit 50 are connected to cause a short-circuit state is not preferable because a large short-circuit current flows. Therefore, the control switch S2 is first turned off from ON.
(See FIG. 6B), and after a predetermined time, for example, 5 milliseconds, the control switch S3 is controlled to be turned from OFF to ON (see FIG. 6E). This avoids the short condition. The control switch S1 is controlled so as to be turned on from OFF at a time earlier than the control of the control switch S2 in consideration of the settling time of the amplifier A11 (see FIG. 6D). As a result, the output waveform PAT2 of the amplifier A11 rises to a double amplitude after the settling time as shown in FIG. 6C. 6B, 6D, and 6E show ON / OFF states of the contacts of each control switch. Therefore, it goes without saying that the drive control of each control switch is controlled so as to be driven at a timing before a predetermined time in consideration of a time delay of a reed relay or the like. By the way, it is well known that the ON / OFF operation transition time of the reed relay contact varies among individual components.
It is about 5 milliseconds. Therefore, the operation timing of each contact cannot be adjusted.

As a result of the above control, the output waveform PAT3 output to the second line L4 is as shown in the first half of FIG. 6F. That is, it is found that there is a problem that an unstable indefinite voltage occurs during the transition from 6 V to 12 V, for example, a 0 V period (see FIG. 6H) in which both drivers are disconnected.

Second, when the voltage output to the second line L4 is 1
A case where switching control is performed from 2V to 6V will be described.
First, the control switch S3 is controlled to change from ON to OFF (see FIG. 6E), and after a predetermined time, for example, 5 milliseconds, the control switch S2 is controlled to change from OFF to ON (see FIG. 6B). The control switch S1 prevents the unexpected voltage of the amplifier A11 from being output to the second line L4.
After waiting for a predetermined time from the control of the control switch S3, control is performed so as to be changed from ON to OFF (see FIG. 6D). As a result, the output waveform PAT2 of the amplifier A11 falls as shown in FIG. 6C.

As a result of the above control, the output waveform PAT3 output to the second line L4 is as shown in the latter half of FIG. 6F. That is, it can be seen that there is a problem that an unstable indefinite voltage occurs during the transition from 12 V to 6 V, for example, a 0 V period (see FIG. 6K) due to the non-connection state of both drivers.

[0014]

As described above, in the prior art, first, a tester pin driver DR1 is used.
Useless 0 when switching from
A V period (see FIG. 6H) occurs, which is not preferable from the viewpoint of waveform quality. Secondly, when switching from the high voltage driver circuit 50 to the tester pin driver DR1, an unnecessary 0V period (see FIG. 6K) similarly occurs, which is not preferable from the viewpoint of waveform quality. From these viewpoints, conventional pin electronics circuits with high voltage drivers have practical difficulties. Therefore, an object of the present invention is to provide a pin electronics circuit of a semiconductor test device that realizes a smooth switching between a tester pin driver and a high voltage driver circuit.

[0015]

First, in order to solve the above-mentioned problems, in the configuration of the present invention, a test waveform output from a high-speed tester pin driver DR1 for outputting a normal test waveform and a predetermined constant A pin electronics circuit of a semiconductor test apparatus including two types of drivers including a high-voltage driver that generates and outputs a high voltage, and an output configuration that switches one of the two drivers and supplies the output to an IC pin of a DUT.
A semiconductor test apparatus comprising means capable of externally controlling an output voltage generated and output by a high voltage driver that generates and outputs a predetermined constant high voltage. According to the above-mentioned invention, a pin electronics circuit of a semiconductor test apparatus that realizes a smooth switching between the tester pin driver DR1 and the high voltage driver circuit 50 can be realized.

FIG. 1 shows a solution according to the present invention. Second, in order to solve the above problem, in the configuration of the present invention, a tester pin driver DR1 for outputting a normal test waveform, and a control switch for opening and closing between an output terminal of the tester pin driver DR1 and an IC pin of a DUT. S2, an amplifier A11 which is a high voltage driver for generating and outputting a predetermined constant high voltage, and an output terminal of the amplifier A11 and a DU.
A control switch S3 for opening and closing between IC pins of T is provided, and both control switches S2 and S3 provided at the output terminals of both drivers are switched to output any one of the output waveforms PAT to the IC pin of the DUT.
1. In a pin electronics circuit of a semiconductor test apparatus having an output mode for supplying PAT2, means capable of externally controlling an output voltage generated and output by an amplifier A11 for generating and outputting a predetermined constant high voltage (for example, a DA converter 12)
There is a semiconductor test apparatus characterized by comprising:

FIG. 3 shows a solution according to the present invention. The control switches S2 and S3 provided at the output terminals of both drivers are high-speed semiconductor switches (for example, high-speed MO switches).
S-type transistors T2n, T2p, T3n, T3p)
There is a pin electronics circuit of the semiconductor test device described above.

Further, as the high voltage driver circuit 50,
An amplifier A11 which is a high voltage driver and a DA converter 12
And a control switch S for opening and closing the output terminal of the high-voltage driver
3 is a pin electronic circuit of the semiconductor test apparatus described above.

FIG. 7 shows a solution according to the present invention. The high-voltage driver circuit 50 is a variable-voltage amplifier B that is a high-voltage driver and can vary the gain.
11, a control switch S1 for opening and closing the input terminal of the variable gain amplifier B11, and a control switch S3 for opening and closing the output terminal of the high-voltage driver.

The output voltage generated and output by the amplifier A11 or the variable gain amplifier B11 which is a high voltage driver for generating and outputting a predetermined constant high voltage is set and controlled to the same voltage as the output voltage generated and output by the tester pin driver DR1. There is provided a pin electronics circuit of the semiconductor test apparatus described above, further comprising control means for providing a transition period in which both control switches S2 and S3 provided at the output terminals of both drivers are in an ON state in a state.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

According to the present invention, an example of the configuration of the pin electronics provided with the high-voltage driver shown in FIG. 1, a time chart for explaining the switching operation of the control switch shown in FIG. 2, and the control switches S2 and S3 shown in FIGS. This will be described below with reference to a specific circuit example in the case of a semiconductor switch. still,
Elements corresponding to the conventional configuration are denoted by the same reference numerals.

The configuration of FIG. 1 is the same as the conventional one except for the high voltage driver circuit 50. The internal configuration of the high-voltage driver circuit 50 according to the present invention includes a control switch S3, a DA converter (DAC) 12, and an amplifier A11. Note that the control switch S3 and the amplifier A11 are the same as those in the related art. That is,
The control switch S3 uses a reed relay,
The amplifier A11 is a high-voltage driver using a double amplifier. This amplifier A11 is not a double amplifier,
An amplifier or buffer amplifier of a predetermined number may be used.

The DAC 12 is a DA converter that generates and outputs a desired analog voltage according to setting data from the outside.
This analog voltage is supplied to the input terminal of the amplifier A11.
Therefore, unlike the prior art, the output waveform PAT1 from the tester pin driver DR1 is not received as an input signal. If the D / A converter itself has a built-in buffer amplifier and can output directly to the end of the second line L4, the amplifier A11 may be omitted.

Next, the operation of the present invention will be described with reference to the time chart of FIG. Here, the high level of the output waveform PAT1 is 6V, and the high voltage driver circuit 50 is 12V.
Is assumed to occur. Further, as an initial state, the control switch S2 is turned on, and the control switch S3 is turned off.
Assume state. 2B and 2E show ON / OFF states of the contacts of each control switch. Therefore, it goes without saying that the drive control of each control switch is driven at a timing before the time considering a time delay of, for example, a reed relay or the like.

In FIG. 2A, the tester pin driver DR1 generates a pattern so that the output waveform PAT1 is at a high level, that is, 6V is constantly output.

First, when the voltage output to the second line L4 is 6
A case where switching control is performed from V to 12 V will be described.
Prior to the switching, the DAC 12 is set to V1 so that the output waveform PAT2 of the amplifier A11 generates and outputs 6V.
(See FIGS. 2D and 2C).

After a predetermined time, the control switch S2 is turned on.
In the state, the control switch S3 is controlled to be turned from OFF to ON (see FIG. 2E). That is, both control switches S2 and S3 are turned on. As a result, as shown in FIG. 2H, the output waveform PAT3 output to the second line L4 has the same output voltage of 6 V, but slightly increases since it is combined. However, this slight rise in voltage does not hinder practical use in device testing.

Thereafter, the control switch S2 is controlled to be turned off from ON after a predetermined time, for example, 5 milliseconds, in consideration of the operation variation time of the control switch (FIG. 2).
B). This means that an overlap period (see FIG. 2P) in which at least one output voltage of the output waveforms PAT1 and PAT2 is always connected to the second line L4 is provided. That is, it can be seen that there is a great advantage that an indefinite period in which both drivers are disconnected and temporarily become 0 V as in the related art can be eliminated. Therefore,
Even if the control switch has an operation variation time, it can be implemented without causing any trouble.

Thereafter, the setting of the DAC 12 is changed from V1 to V2.
(See FIGS. 2D and 2C), 12 V that has been raised to a desired high voltage is supplied to the second line L4 (see FIG. 2F).

Second, when the voltage output to the second line L4 is 1
A case where switching control is performed from 2V to 6V will be described.
First, by setting the setting of the DAC 12 from V2 to V1 (see FIG. 2C), the second line L4 drops from the high voltage 12V to 6V.

Then, the output terminal of the amplifier A11 becomes stable 6
After the settling time to reach V, the control switch S3 becomes O
The control switch S2 is controlled to be turned from OFF to ON while keeping the N state (see FIG. 2B). That is, both control switches S2 and S3 are turned on. As a result, the second
As shown in FIG. 2K, the output waveform PAT3 output to the line L4 has the same output voltage of 6 V, but slightly increases since it is combined. However, this slight increase in voltage does not hinder practical use, as described above. This means that among the output waveforms PAT1 and PAT2,
An overlap period (see FIG. 2Q) in which at least one output voltage is always connected to the second line L4 is provided.
That is, it can be seen that there is a great advantage that an indefinite period in which both drivers are disconnected and temporarily become 0 V as in the related art can be eliminated. Therefore, the present invention can be implemented so as not to cause a problem even if the operation time of the control switch varies.

Thereafter, the control switch S3 is turned from ON to OF.
F (see FIG. 2E),
The normal output waveform PAT1 is supplied from the driver DR1 to the DUT.

According to the configuration of the present invention described above, when the tester pin driver DR1 and the high voltage driver circuit 50 are switched, both control switches S are set in a state where both output voltages are set to the same voltage.
The pin electronics circuit of the semiconductor test apparatus that realizes a smooth switching between the tester pin driver DR1 and the high voltage driver circuit 50 without waveform distortion by providing a means for providing an overlap period in which both S2 and S3 are turned on. There are significant benefits that can be realized.

Next, a case where semiconductor switches are used as the control switches S2 and S3 will be described with reference to FIG.

The control switch S2 of FIG. 3 has a configuration in which an NMOS transistor T2n for a source current and a PMOS transistor T2p for a sink current are connected in parallel. These transistors use a high-speed output waveform PAT1 output from the tester pin driver DR1 so as to minimize the deterioration of the pass characteristics due to the insertion of the transistor. That is, a transistor having good high-frequency characteristics and having the smallest possible capacitance between the source and drain terminals of the transistor and the circuit ground terminal is used. In addition, the leakage current between the source and drain terminals and the leakage current to the gate terminal when turned off are minimized. still,
Since the ON resistance of the transistor in the ON state is on the order of several ohms, the value of the matching resistor R1 in FIG. 1 can be matched to the characteristic impedance of the line by using a resistor having a low resistance corresponding to the ON resistance of the transistor. To

The level converting means 60 includes driving means 61 and 6
2, 63 and 64, which drive the gate terminals of the transistors. This supplies positive and negative inversion control voltages to the gate terminals of the transistors T2n, T2p, T3n, T3p. The driving units 61 and 62 receive a switching signal 65 from the outside and supply predetermined high level and low level to the corresponding gate terminals of the transistors T2n and T2p. When the output level of the output waveform PAT1 is −3 V to +8 V, the high-level control voltage supplied to the gate terminal is, for example, +
10V is supplied, and the low-level control voltage is, for example, −5.
Drive means 61 and 62 capable of supplying V.

The other control switch S3 has a configuration in which an NMOS transistor T3n and a PMOS transistor T3p are connected in parallel. Others are the same as above. However, the driving means 63 and 64 are transistors T3n and T3p
Since the control voltage supplied to the gate terminal is high,
A corresponding control voltage is supplied. Since the high-voltage output waveform PAT2 is used only for supplying the source current in normal use, it can be practically used as a configuration in which the PMOS transistor T3p is omitted as shown in FIG. is there.

When the semiconductor switches described above are used as the control switches S2 and S3, the switching time of the transistors is about several tens of nanoseconds.
For this reason, if necessary, the control for giving the overlap period in which both the control switches S2 and S3 described in FIG. That is, both control switches S2,
S3 is simultaneously switched and controlled. First, both drivers may be short-circuited for a moment, for example, for several tens of nanoseconds, due to the simultaneous switching. However, since they are extremely short, there is no problem that the drivers are deteriorated. . Second, both drivers may be open momentarily, but because they are extremely short, they do not hinder practical use in device testing. Practically, it is desirable to use a method in which both drivers are driven so as to be short-circuited for a moment.

As described above, the control switch S2,
When a semiconductor switch is used as S3, the time when both the tester pin driver DR1 and the high voltage driver circuit 50 are short-circuited or opened when switching is performed is instantaneous. Therefore, there is obtained an advantage that a pin electronics circuit of a semiconductor test apparatus that realizes practically smooth switching between the tester pin driver DR1 and the high voltage driver circuit 50 can be realized.

The configuration of the present invention is not limited to the above embodiment. For example, in FIG. 1, one of the control switches S2 and S3 may be replaced with a semiconductor switch. Further, as shown in the configuration of FIG.
1 is replaced with a variable gain amplifier B11, and as shown in the time chart of FIG.
By controlling the variable gain amplifier B11 to be the same as the high level 6V of the output waveform PAT1 on the R1 side, a smooth switching can be realized in the same manner.

[0042]

According to the present invention, the following effects can be obtained from the above description. As described above, according to the present invention, as shown in the time chart of FIG. 2, when the tester pin driver DR1 and the high-voltage driver circuit 50 are switched, both control switches S2 are set in a state where both output voltages are set to the same voltage. , S3 as a means for providing an overlap period in which both are turned ON, the waveform quality supplied to the DUT is improved, and a smooth switching between the tester pin driver DR1 and the high voltage driver circuit 50 can be realized. There is a great advantage that the pin electronics circuit can be realized. Further, by using semiconductor switches capable of high-speed switching as the control switches S2 and S3,
The waveform quality to be supplied to the DUT is improved, and the advantage that practically smooth switching can be realized is obtained. In this case, as a result of the switching time being significantly shortened, there is obtained an advantage that the throughput of the device test can be improved by the time. Further, as shown in the configuration example of FIG. 7, a variable gain amplifier B11 is provided, and both control switches S
As a result of the configuration means having an overlap period in which both S3 and S3 are turned on, the waveform quality supplied to the DUT is similarly improved, and smooth switching between the tester pin driver DR1 and the high voltage driver circuit 50 can be realized. The following advantages are obtained. Therefore, the technical effect of the present invention is great,
Industrial economic effects are also great.

[Brief description of the drawings]

FIG. 1 is a configuration example of pin electronics including a high-voltage driver according to the present invention.

FIG. 2 is a time chart for explaining a switching operation of a control switch of FIG. 1;

FIG. 3 is a specific circuit example of the present invention when the control switches S2 and S3 are semiconductor switches.

FIG. 4 is another specific circuit example of the present invention where the control switches S2 and S3 are semiconductor switches.

FIG. 5 is a conceptual configuration example of a conventional pin electronics including a high-voltage driver.

FIG. 6 is a time chart for explaining a switching operation of the control switch of FIG. 5;

FIG. 7 is another configuration example of the pin electronics including the high-voltage driver according to the present invention.

[Explanation of symbols]

 DR1 Tester pin driver R1 Matching resistor S1, S2, S3 Control switch CP2 Comparator A11 Amplifier B11 Variable gain amplifier 12 DAC (DA converter) 50 High voltage driver circuit 60 Level conversion means T2n, T3n NMOS type transistor T2p, T3p PMOS type Transistor

Claims (6)

[Claims] 1. A high-speed driver that outputs a test waveform from a high-speed tester pin driver that outputs a normal test waveform and a high-voltage driver that generates and outputs a predetermined constant high voltage. In a pin electronics circuit of a semiconductor test apparatus having an output mode for switching and supplying to a DUT IC pin, a means for externally controlling an output voltage generated and output by a high voltage driver for generating and outputting a predetermined constant high voltage is provided. A semiconductor test apparatus characterized by the above-mentioned. 2. A tester pin for outputting a normal test waveform.
Driver, output terminal of the tester pin driver and DUT
An amplifier which is a high voltage driver for generating and outputting a predetermined constant high voltage, comprising a control switch for opening and closing between IC pins, and a control switch for opening and closing between an output terminal of the amplifier and an IC pin of the DUT. In a pin electronics circuit of a semiconductor test device having an output mode for supplying either output waveform to an IC pin of a DUT by switching both control switches provided at an output terminal, an output voltage generated and output by the amplifier can be externally controlled. A semiconductor test apparatus characterized by comprising various means. 3. The control switch provided at the output terminals of both drivers is a semiconductor switch.
The semiconductor test apparatus according to the above. 4. The semiconductor test according to claim 2, wherein the high-voltage driver circuit includes an amplifier that is a high-voltage driver, a D / A converter, and a control switch that opens and closes an output terminal of the high-voltage driver. apparatus. 5. The high-voltage driver circuit is a high-voltage driver and a variable gain amplifier capable of changing a gain, a control switch for opening and closing an input terminal of the variable gain amplifier, and opening and closing an output terminal of the high-voltage driver. 3. The semiconductor test apparatus according to claim 2, further comprising a control switch. 6. Both control switches provided at the output terminals of both drivers are turned on in a state where the output voltage generated and output by the amplifier which is a high voltage driver is set and controlled to the same voltage as the output voltage generated and output by the tester pin driver. 3. The semiconductor test apparatus according to claim 2, further comprising control means for setting a state.