JPH11317086A - Semiconductor storage device, storage erasing method thereof, and storage medium storing storage erasing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct an information control, that is easy to use and has a good efficiency, even though a memory cell array block dividing technique is used for the superior technology, in which plural data (bits) are stored in one memory cell that is called a multivalued storage to realize a higher integration and to increase the capacity of a semiconductor storage device. SOLUTION: In a flash memory (an EEPROM), a memory array is divided into plural memory cell blocks 12. Then, addresses (1) to (4) and (5) to (8) are stipulated to be continuous in the blocks 12 for every block 12 of the array. During a storage erasing, an erasing is independently and simultaneously conducted for every block 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-value storage type nonvolatile semiconductor memory device capable of storing data of two or more digits, a storage erasing method thereof, and a storage medium storing the storage erasing method. It is suitable to be applied when the information is binary data.

[0002]

2. Description of the Related Art In recent years, in a semiconductor memory device represented by a flash memory or the like, in response to a demand for divisional use of one memory cell, the memory cell array is not erased simultaneously when erasing the memory cell. A technique has been developed in which memory cells are divided into a plurality of memory cell blocks and erasing is performed independently for each memory cell block. Specifically, Japanese Patent Application Laid-Open No. Hei 8-263361 discloses a technique for simultaneously erasing a plurality of blocks while dividing the data into blocks. A technique for copying overwriting data to prevent overwriting is disclosed in Japanese Patent Application Laid-Open No. 8-266110 and
Japanese Patent Publication No. 175917 discloses a technique for managing a storage area in units of blocks so that the number of rewrites is hardly restricted.

[0003]

In recent years, semiconductor memory devices have been further integrated and increased in capacity. Such a highly integrated and large-capacity semiconductor memory device has been divided into blocks of a memory cell array. At present, no major attempt has been made to apply this technology.

Accordingly, an object of the present invention is to provide a multi-valued semiconductor memory device which is considered to be the most promising for higher integration and larger capacity, that is, a technique for storing a plurality of data (bits) in one memory cell. To provide a semiconductor memory device which is easy to use and enables efficient information management even when a technique of block partitioning of a memory cell array is applied. Further, a memory erasing method using the same and a memory erasing method using the same are provided. An object of the present invention is to provide a recording medium on which the method is recorded.

[0005]

According to the present invention, there is provided a semiconductor memory device comprising a plurality of multi-valued memory cells capable of storing, as storage information, one of three or more possible states. And a memory cell array which is divided into memory cell blocks each of which is composed of the predetermined memory cells, and is configured so that the storage information is independently erased for each of the memory cell blocks.

In one embodiment of the semiconductor memory device according to the present invention, a first selection circuit for selecting a predetermined memory cell block, and a first selection circuit in the memory cell block selected by the first selection circuit. A second selection circuit for selecting the memory cell of the above, wherein each data constituting the multi-valued storage information corresponds to the address of the data in the memory cell selected by the second selection circuit. And the addresses are successively allocated to the respective memory cells in the memory cell block.

In one embodiment of the semiconductor memory device according to the present invention, the addresses are allocated so as to be continuous for each of the memory cells.

In one embodiment of the semiconductor memory device according to the present invention, the addresses corresponding to the storage capacity are assigned to the respective memory cell blocks, and the addresses are stored in the respective memory cells of the memory cell block. The information is arbitrarily distributed to the respective data constituting the information and allocated to the respective memory cells.

In one embodiment of the semiconductor memory device of the present invention, the memory cell has a gate, a source, and a drain, and a tunnel insulating film formed on a channel region between the source and the drain. An island-shaped floating gate is provided between the gate and the gate via a dielectric film, and a threshold voltage is set by applying a predetermined voltage to each of the gate, the source, and the drain. The storage information corresponding to the threshold voltage is stored.

In one embodiment of the semiconductor memory device according to the present invention, an erasing transistor connected to the source of each of the memory cells of the memory cell block is provided for each of the memory cell blocks.

In one embodiment of the semiconductor memory device according to the present invention, the memory cell includes a memory capacitor for storing signal charges, and an access transistor for selecting the memory capacitor. A charge accumulation state is set by applying a predetermined reference voltage to the memory capacitor, and storage information corresponding to the reference voltage is stored.

In one embodiment of the semiconductor memory device according to the present invention, the storage information is binary data.

One embodiment of the semiconductor memory device of the present invention further includes a redundant memory circuit having a plurality of memory cells for relieving a defective memory cell of the memory cell.

According to a storage erasing method of a semiconductor memory device of the present invention, a plurality of multi-valued memory cells capable of storing storage information composed of data of three or more predetermined values are arranged, and the predetermined memory is provided. A memory erasing method for a semiconductor memory device including a memory cell array divided into memory cell blocks in which cells are aggregated, wherein at least one of a plurality of memory cell blocks is erased when erasing the storage information. A first step of selecting
And the second step of simultaneously erasing the storage information of each of the memory cells constituting the memory cell block selected in the step (b).

In one embodiment of the storage erasing method of the semiconductor memory device according to the present invention, each of the data forming the multi-valued storage information is stored in the memory cell corresponding to the address of the data, and the address is stored in the memory cell. The method further includes a third step of allocating the memory cells so as to be continuous in the memory cell block.

In one embodiment of the storage erasing method for a semiconductor memory device according to the present invention, the addresses are allocated so as to be continuous for each of the memory cells.

In one embodiment of the storage erasing method of the semiconductor memory device according to the present invention, the addresses corresponding to the storage capacity are assigned to the respective memory cell blocks, and the addresses are stored in the respective memory cells of the memory cell block. Arbitrarily distributed to the respective data constituting the stored information to be allocated to the respective memory cells.

In one embodiment of the storage erasing method for a semiconductor memory device according to the present invention, the memory cell has a gate, a source, and a drain, and is formed on a channel region between the source and the drain. An island-shaped floating gate is provided between the tunnel insulating film and the gate via a dielectric film, and a threshold voltage is set by applying a predetermined voltage to each of the gate, the source, and the drain. Then, storage information corresponding to the threshold voltage is stored.

In one embodiment of the storage erasing method for a semiconductor memory device according to the present invention, the memory cell includes a memory capacitor for storing signal charges and an access transistor for selecting the memory capacitor. The charge storage state is set by applying a predetermined reference voltage to the memory capacitor, and storage information corresponding to the reference voltage is stored.

In one embodiment of the storage erasing method for a semiconductor memory device according to the present invention, the storage information is binary data.

In the storage medium of the present invention, the first and second steps constituting the storage erasing method are stored so as to be readable by a computer.

[0022]

In the semiconductor memory device of the present invention, in addition to using multivalued data as storage information, the memory cell array is divided into memory cell blocks, and the storage information is independently erased for each memory cell block. Here, if the assignment of the address of the data to be stored in each memory cell is not taken into account, data will be scattered between different memory cell blocks, and when erasing and storing an arbitrary memory cell block, the physical address space will be reduced. In this case, the memory cells to be stored and erased are not gathered together and are extremely scattered, which poses a problem not only in convenience but also in information management. On the other hand, in the semiconductor memory device of the present invention, the addresses are continuously allocated to the respective memory cells in the memory cell block. The grouped parts are erased all at once, which is convenient and convenient for information management, and further suppresses the occurrence of errors and contributes to the improvement of reliability.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments to which the present invention is applied will be described below in detail with reference to the drawings. In the present embodiment, an EEPROM (flash memory) which is a nonvolatile semiconductor memory device in which storage information is binary data of, for example, four values (= 2 bits) will be described. FIG. 1 is a block diagram schematically showing a main configuration of the EEPROM of the present embodiment.

The main structure of the EEPROM of this embodiment is as shown in FIG. 1, and a memory cell array 1 in which a plurality of memory cells 11 are arranged in a matrix and a memory for selecting a predetermined memory cell 11 are shown. A decoder circuit 2 and a sub-decoder circuit 3, a sense amplifier 4 provided between the memory cell array 1 and the decoder circuit 2, and an address buffer 5 connected to the decoder circuit 2 and receiving an address signal;
And an input / output circuit 7 connected to the sense amplifier 4 via an I / O line 6 for inputting / outputting a binary data string.

The memory cell array 1 is divided into a plurality of memory cell blocks 12 each composed of several memory cells 11. As shown in FIG. 2, each memory cell block 12 has memory cells 11 arranged in a matrix and has an erasing transistor 13 connected to the source 103 of each memory cell 11.

Each memory cell 11 has, as shown in FIG.
On a p-type silicon semiconductor substrate 101, n such as phosphorus (P) or arsenic (As) is formed on a surface region of an element active region 102 defined by an element isolation structure such as a field oxide film.
103 and a drain 104, which are a pair of impurity diffusion layers formed by ion implantation of a type impurity, and a pattern formed via a tunnel oxide film 105 on a channel region C between the source 103 and the drain 104, respectively. It has an isolated island-shaped floating gate 106 and a control gate 108 which is patterned on the floating gate 106 via a dielectric film 107 such as an ONO film and is capacitively coupled to the floating gate 106. .

The decoder circuit 2 is a circuit for selecting a predetermined memory cell block 12 from a plurality of memory cell blocks 12 constituting the memory cell array 1. For example, a row decoder connected to a row sub-decoder described later And a column decoder connected to the column sub-decoder. The decoder circuit 2 is connected to the erasing transistor 13 of each memory cell block 12 and drives the erasing transistor 13 by the decoder circuit 2 so that the selected memory cell block 12 will be described later.
The storage information of the independent memory cell 11 can be simultaneously erased every time.

The sub-decoder circuit 3 includes a row sub-decoder connected to a plurality of word lines (control gates 8) of each memory cell block 12, and a column sub-decoder connected to a plurality of bit lines of the memory cell block 12. This is a circuit for selecting a predetermined memory cell 11 in the memory cell block 12 and writing and reading storage information.

A redundant memory circuit 14 is provided beside each memory cell block 12. The redundant memory circuit 14 includes a memory cell array having a plurality of memory cells for relieving the memory cells 11 when a plurality of memory cells 11 arranged in the memory cell block 12 become defective memory cells. I have.

For example, when a certain memory cell 11 of a certain memory cell block 12 becomes a defective memory cell, this defective memory cell is switched to a memory cell of the redundant memory circuit 14 by the switching means of the decoder circuit 12.
Replace the defective memory cell with a good memory cell.

That is, the memory cell of the redundant memory circuit 14 replaced with the defective memory cell functions as a virtual memory cell in the memory cell block 12 having the defective memory cell. Therefore, in the memory cell of the redundant memory circuit 14 replaced with the defective memory cell,
The stored data is erased together with the memory erase of the memory cell block 12 having the defective memory cell. At the time of erasing, the data is stored in correspondence with the address of the storage data of the memory cell 11 (including the virtual memory cell), and the address is continuously allocated to each memory cell in the memory cell block 12. That is, the address assigned to the defective memory cell is assigned to the memory cell of the redundant memory circuit 14.

FIG. 4 shows the main configuration of the reading means 3a in the sub-decoder circuit 3. The read means is connected to each memory cell 11 and includes reference transistors Tr1, Tr2, Tr3 having threshold voltages of 2.5 V, 3.5 V, and 1.5 V, respectively.
Here, the bit line of each memory cell 11 is connected to the sense amplifier 2
The transistor Tr1 is connected to the sense amplifier 21
, The bit line of each memory cell 11 is connected to the + terminal of the sense amplifier 22, and the transistors Tr2 and Tr3 are connected to the-terminals of the sense amplifier 22, respectively. In the circuit configuration of the reading means, first, the upper bits of the storage information are sequentially output from the output terminal D1, and then the lower bits of the storage information are sequentially output from the output terminal D0.

This EEPROM, as shown in FIG.
Each memory cell 11 has four values (1 V, 2 V, 3 V, 4 V)
The storage information corresponding to each of the threshold voltages can be stored, and the four values (“00”, “01”, “1”) are set so that the value of the storage information increases as the threshold voltage increases.
0 ”,“ 11 ”) can be stored.

In the EEPROM of the present embodiment, for each memory cell block 12 of the memory cell array 1, the address (address) is specified to be continuous in the memory cell block 12.

Some specific examples are shown in FIG. This figure 6
In the example, two multi-level (quaternary) memory cells 11 represent each memory cell block 12 and two memory cell blocks 1
2 represents the memory cell array 1. First, as a first method, as shown in FIG. 6A, in each memory cell block 12, each data (A) constituting storage information A, B, C, and D stored in each memory cell 11 is stored.
1, A2), (B1, B2), (C1, C2) and (D
1, D2) are assigned so that addresses 及 び and す る are consecutive for each memory cell 11 concerned. (A1,
A2) is quaternary data (00, 00) of one memory cell 11.
01, 10, 11). For example, when the data is “01”, A1 is 0 and A2 is 1
Becomes (B1, B2), (C1, C2) and (D1,
The same applies to D2).

Further, as a second method, as shown in FIG. 6B, addresses 〜 and 分 の corresponding to the storage capacity are assigned to each memory cell block 12, and the address is assigned to each memory of the memory cell block 12. Data (A1, A2), (B1, B2), (C
1, C2) and (D1, D2), and is allocated to each of the memory cells 11. Here, as an example, for each memory cell block 12, first, addresses (and, and) are allocated to lower bits of the memory cells 11, and the remaining addresses (and and) are allocated to upper bits. Of course, the allocation may be reversed between the lower bits and the upper bits.

Next, a method of using the EEPROM of this embodiment will be described. First, a writing method using the EEPROM will be described. At the time of writing, the memory cell block 12 is selected by the decoder circuit 2 according to the address signal from the address buffer 5, and the memory cell 11 is selected from the memory cell block 12 by the sub-decoder circuit 3. And the write operation of the memory cell 11 is performed as described below.

First, when writing the storage information "11",
The drain 104 of the memory cell is set to the ground potential, and the source 1
03 is opened, and about 22 V is applied to the control gate 108. At this time, electrons are injected from the drain 104 into the floating gate 106 through the tunnel oxide film 105, and the threshold voltage (V _T ) shifts in the positive direction. Then, the threshold voltage of the memory cell increases to about 4V. This storage state is set to “11”.

Next, when writing the storage information "10",
The drain 103 of the memory cell is set to the ground potential, the source 103 is opened, and about 20 V is applied to the control gate 108. At this time, electrons are injected from the drain 104 into the floating gate 106 through the tunnel oxide film 105, and the threshold voltage of the memory cell becomes about 3V. This storage state is set to “10”.

Next, when writing the storage information "01",
With the drain 104 of the memory cell at the ground potential, the source 103 is opened, and about 18 V is applied to the control gate 108. At this time, electrons are injected from the drain 104 into the floating gate 106 through the tunnel oxide film 105, and the threshold voltage of the memory cell becomes about 2V. This storage state is set to “01”.

Next, when writing the storage information "00",
Applying about 10 V to the drain 104 of the memory cell,
The source 103 is opened, and the control gate 108 is set to the ground potential. At this time, the electrons injected into the floating gate 106 are extracted from the drain 104, and the threshold voltage of the memory cell becomes about 1V. This storage state is set to “00”.

Next, a reading method using the EEPROM will be described. At the time of reading, the memory cell block 12 is selected by the decoder circuit 2 in accordance with the address signal from the address buffer 5, and subsequently the memory cell 11 is selected from the memory cell block 12 by the sub-decoder circuit 3, and as shown below. The read operation of the memory cell 11 is performed. FIG. 7 is a flowchart showing each step of the read operation.

As shown in FIG. 5, the stored information read from the selected memory cell 11 has four peaks (quaternary values) having a threshold voltage (V _T ) of about 1 V, about 2 V, about 3 V, and about 4 V. ) Is shown. In FIG. 5, when the threshold voltage _VT is detected in the range indicated by R1, the storage state is "00", and when the threshold voltage _VT is detected in the range indicated by R2. Has a storage state of “01”. When the threshold voltage _VT is detected in the range indicated by R3, the storage state is changed to "1".
0 ", and the threshold voltage V _T falls within the range indicated by R4.
Is detected, the storage state is "11".

Therefore, first, the storage state is "R1 or R1".
2 ”or“ R3 or R4 ”, that is, the upper bit of the storage information stored in the memory cell 11 is“ 0 ”.
The determination is made using the transistor Tr1. In this case, as shown in FIG. 7, the order of 5V is applied to the source 3 and drain 4 and a gate electrode 6 (step S1), the detecting the drain current in the sense amplifier 21, the threshold voltage V _T and the transistor Tr1 The magnitude relationship with the threshold voltage is determined (step S2). At this time, if the threshold voltage V _T is larger than the threshold voltage of the transistor Tr1, that is, if more current flowing through the channel region C of the memory cell current of the transistor Tr1 is large upper bit is "1" and it is determined, if the threshold voltage V _T is smaller than the threshold voltage of the transistor Tr1, that is, if when the current flowing through the memory cell 11 than the current flowing through the transistor Tr1 is larger upper bit is "0" It is determined and output from the output terminal D1 as the upper bit of the storage information prior to the lower bit (step S3, step S4).

[0045] Then, if the threshold voltage V _T is larger than the threshold voltage of the transistor Tr1, the transistor Tr2 with the same read operation, the memory cell 11
Comparing the current flowing through the current and the transistor Tr2 flows to (step S5), and if the threshold voltage V _T is smaller than the threshold voltage of the transistor Tr1 determines similar read operation using the transistor Tr3 (Step S6).

In step S5, the threshold voltage V _T
There greater than the threshold voltage of the transistors Tr1, the threshold voltage V _T is the transistor Tr in the aforementioned read operation
2, the memory cell 11
Is determined to be "1", and is output from the output terminal D0 (step S5).
7). Therefore, in this case, the storage information read from the memory cell 11 is “11”.

Meanwhile, in step S5, if the threshold voltage V _T is smaller than the threshold voltage of the transistor Tr2 is stored information stored in the memory cell 11 is "1
It is determined to be "0" and output from the output terminal D0 (step S8) .Therefore, in this case, the storage information read from the memory cell 11 is "10".

[0048] Further, in step S6, if the threshold voltage V _T is smaller than the threshold voltage of the transistor Tr1, that is, when the current of the memory cell 11 is greater than the current of the transistor Tr1, then transistor Tr3
If the threshold voltage of the memory cell 11 is higher than the threshold voltage of the memory cell 11, the lower bit is determined to be "1" and is output from the output terminal D0 as the lower bit of the storage information (step S9). Therefore, in this case, the storage information read from the memory cell 11 is “01”.

Meanwhile, when the threshold voltage V _T in the above reading operation is smaller than the threshold voltage of the transistor Tr1, i.e. the memory cell 1 than the current of the transistor Tr1
If the current of 1 is large, it is compared with the threshold voltage of the transistor Tr3. If the threshold voltage of the memory cell is small, the lower bit is determined to be "0" and output as the lower bit of the storage information. The signal is output from the terminal D0 (step S10). Therefore, in this case, the storage information read from the memory cell 11 is “00”.

Next, a storage erasing method using the EEPROM will be described. At the time of storage erasure, a predetermined memory cell block 12 is selected by the decoder circuit 2 in accordance with the address signal from the address buffer 5, and the erasing transistor 13 is driven to simultaneously store the storage information of each memory cell 11 of the memory cell block 12. To erase.
Note that the number of memory cell blocks 12 selected by the decoder circuit 2 at the time of memory erasure is not limited to one, and a plurality of memory cell blocks 12 may be selected to perform memory erasure at the same time.

Here, as described above, E of the present embodiment
In the EPROM, for example, as shown in FIGS. 6A and 6B, for each memory cell block 12 of the memory cell array 1, the address in the memory cell block 12 is defined to be continuous. Here, an example of the physical address space of the memory cell array 1 composed of the memory cell blocks 12 is shown in FIG. Here, the total storage capacity of the memory cell array 1 is 16 Mbits (2 Mbytes), and the storage capacity of each memory cell block 12 is 2 Mbits. As described above, when data is erased from a predetermined memory cell block 12, the addresses in the memory cell block 12 are continuous. R, and the memory cells 11 for 2M bits in the region R are not scattered.
Will be deleted all at once.

Here, as a comparative example of this embodiment, a case will be described in which address assignment is not considered as in this example. At present, no technique has been devised for applying divided storage and erasure for each memory cell block to a multi-valued memory, but if it exists, addresses will be allocated as shown in FIG. 9, for example. . That is, an address (〜) is first allocated to lower bits of each memory cell 11 over different memory cell blocks (in other words, over the entire memory cell array 1), and the remaining addresses (〜) are assigned to upper bits. Allocate to. Of course, the allocation may be reversed between the lower bits and the upper bits.

In the case of this comparative example, when data is erased from a predetermined memory cell block 12, memory cells 11 to be erased are scattered in the physical address space, which makes it extremely difficult for a user to use. Would.

That is, in the EEPROM of this embodiment, in addition to using multi-valued data as storage information, the memory cell array 1 is divided into memory cell blocks 12, and the storage information is independently erased for each memory cell block 12. Is made. Here, if the assignment of the address of the data to be stored in each memory cell 11 is not considered, the data is scattered between different memory cell blocks,
When an arbitrary memory cell block is stored and erased, the memory cells to be stored and erased in the physical address space are not united and are scattered, which is a problem not only in convenience but also in information management. There is. On the other hand,
In the EEPROM of the present invention, since addresses are successively allocated to the respective memory cells 11 in the memory cell block 12, when an arbitrary memory cell block 12 is stored and erased, it is possible to collectively read the physical address space. Are erased all at once, which is convenient and convenient for information management, and further suppresses the occurrence of errors, thereby contributing to improvement in reliability.

In the present embodiment, the case where the stored information is quaternary (two bits) has been described, but the present invention is not limited to this. For example, if the storage state is 3
In the case of bits (8 values), eight threshold voltages are stored in the storage states “000”, “001”, “010”, “01”.
1 "," 100 "," 101 "," 110 "," 11
1 ", and one of the eight storage states may be specified by a predetermined determination operation at the time of reading. Further, the storage information is not binary data, but may be 0, 1, or the like.
2, the storage state is “0”,
1 ”,“ 2 ”,“ 00 ”,“ 01 ”,“ 0 ”
2 "," 10 "," 11 "," 12 "," 20 "," 2
It is also possible to use 1 "and" 22 ". In such a case, the former will express the storage state as ternary, and the latter as ninth.

Further, the present invention is not limited to the EEPROM, but includes, for example, a memory capacitor for storing signal charges and an access transistor for selecting the memory capacitor. The present invention is also applicable to a multi-valued DRAM which is a volatile memory that sets a charge accumulation state by applying a predetermined reference voltage and stores storage information corresponding to the reference voltage. Further, this multi-level conversion is applicable not only to EEPROMs and DRAMs but also to various other semiconductor memories.

Further, the program code itself for operating various devices and the program code are supplied to a computer so as to realize the functions of the writing method and the reading method, and particularly the storage and erasing method described in the present embodiment. For example, the storage medium 31 storing such program code belongs to the category of the present invention.

The storage medium 31 reads out the program code stored in the storage / reproduction device 32 and operates the computer. As a storage medium for storing such a program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, magnetic tape, nonvolatile memory card, ROM, or the like can be used.

When the computer executes the supplied program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) or other operating system running on the computer. Such a program code is also included in the present invention when the functions of the above-described embodiments are realized in cooperation with application software or the like.

Further, after the supplied program code is stored in the memory provided in the function expansion board of the computer or the function expansion unit connected to the computer, the function expansion board or the function expansion unit is specified based on the instruction of the program code. The present invention also includes a system in which a CPU or the like provided in the system performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0061]

According to the present invention, a multi-valued semiconductor memory device is considered to be most promising for higher integration and higher capacity, that is, a technique for storing a plurality of data (bits) in one memory cell. In addition, even when the technique of partitioning a memory cell array into blocks is applied, it is possible to perform information management with high usability and high efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of an EEPROM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a state in a memory cell block which is a component of the EEPROM according to the embodiment of the present invention.

FIG. 3 is a schematic sectional view showing a main configuration of a memory cell of the EEPROM according to the embodiment of the present invention.

FIG. 4 is a circuit diagram showing a main configuration of a reading unit in a sub-decoder circuit which is a component of the EEPROM according to the embodiment of the present invention.

FIG. 5 is a characteristic diagram showing a distribution of threshold voltages in the EEPROM of the embodiment of the present invention.

FIG. 6 is a schematic diagram showing how to allocate addresses in the EEPROM according to the embodiment of the present invention.

FIG. 7 is a flowchart showing each step when reading quaternary storage information from the EEPROM according to the embodiment of the present invention.

FIG. 8 is a schematic diagram showing a physical address space of a memory cell array which is a component of the EEPROM according to the embodiment of the present invention.

FIG. 9 is a schematic diagram showing how to allocate addresses in a comparative example of the embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell array 2 decoder circuit 3 sub-decoder circuit 3 a reading means 4 sense amplifier 5 address buffer 6 I / O line 7 input / output circuit 11 memory cell 12 memory cell block 13 erasing transistor 14 redundant memory circuit 21, 22 sense amplifier 31 storage Medium 32 Storage / reproducing device 101 Silicon semiconductor substrate 102 Element formation region 103 Source 104 Drain 105 Tunnel oxide film 106 Floating gate 107 Dielectric film 108 Control gate Tr1 to Tr3 Reference transistor

Claims (17)

[Claims] A plurality of multi-valued memory cells capable of storing one of three or more possible states as predetermined information as storage information are arranged, and the predetermined memory cells are aggregated. A semiconductor memory device comprising a memory cell array divided into memory cell blocks and configured so that the storage information is erased independently for each of the memory cell blocks. 2. A first selection circuit for selecting a predetermined memory cell block, and a second selection for selecting a predetermined memory cell in the memory cell block selected by the first selection circuit. And a circuit that stores the multi-valued data constituting the storage information in the memory cell selected by the second selection circuit in correspondence with the address of the data. 2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is configured to continuously allocate each of said memory cells in a memory cell block. 3. The semiconductor memory device according to claim 2, wherein the addresses are allocated so as to be continuous for each of the memory cells. 4. An address corresponding to the storage capacity is allocated to each memory cell block, and the address is arbitrarily distributed to each data constituting the storage information stored in each memory cell of the memory cell block. 4. The semiconductor memory device according to claim 3, wherein said memory cells are allocated to each of said memory cells. 5. The memory cell includes a gate, a source, and a drain, and a dielectric film is interposed between the gate and a tunnel insulating film formed on a channel region between the source and the drain. A threshold voltage by applying a predetermined voltage to each of the gate, the source and the drain,
The device according to claim 1, wherein storage information corresponding to the threshold voltage is stored. 6. The semiconductor memory according to claim 5, wherein an erasing transistor connected to the source of each memory cell of the memory cell block is provided for each of the memory cell blocks. apparatus. 7. The memory cell, comprising: a memory capacitor for storing signal charges; and an access transistor for selecting the memory capacitor, and applying a predetermined reference voltage to the memory capacitor. 5. The semiconductor memory device according to claim 1, wherein a charge storage state is set thereby, and storage information corresponding to the reference voltage is stored. 6. 8. The semiconductor memory device according to claim 1, wherein said storage information is binary data. 9. A memory cell block in which a plurality of multivalued memory cells capable of storing storage information consisting of data of three or more predetermined values are arranged, and the predetermined memory cells are aggregated. A memory erasing method for a semiconductor memory device including a divided memory cell array, wherein at the time of erasing the storage information, a first step of selecting at least one of a plurality of memory cell blocks, And a second step of simultaneously erasing the storage information of each of the memory cells constituting the memory cell block selected in the first step. 10. The memory cell according to claim 1, wherein each of the data forming the multi-valued storage information is stored in the memory cell in correspondence with the address of the data, and each of the memory cells is arranged so that the address is continuous in the memory cell block. 10. The method according to claim 9, further comprising the step of: 11. The memory erasing method according to claim 10, wherein the addresses are allocated so as to be continuous for each of the memory cells. 12. An address corresponding to the storage capacity is allocated to each memory cell block, and the address is arbitrarily distributed to each data constituting the storage information stored in each memory cell of the memory cell block. 11. The method according to claim 10, wherein the memory cell is allocated to each of the memory cells. 13. The memory cell has a gate, a source, and a drain, and a dielectric film is interposed between the gate and a tunnel insulating film formed on a channel region between the source and the drain. A threshold voltage by applying a predetermined voltage to each of the gate, the source and the drain,
The method according to claim 9, wherein storage information corresponding to the threshold voltage is stored. 14. The memory cell, comprising: a memory capacitor for storing signal charges; and an access transistor for selecting the memory capacitor, and applying a predetermined reference voltage to the memory capacitor. 13. The method according to claim 9, wherein a charge accumulation state is set, and storage information corresponding to the reference voltage is stored. 15. The method according to claim 9, wherein said storage information is binary data. 16. A recording medium, wherein the first and second steps constituting the storage erasing method for a semiconductor memory device according to claim 9 are stored so as to be readable by a computer. 17. The semiconductor memory device according to claim 1, further comprising a redundant memory circuit having a plurality of memory cells for relieving defective memory cells of said memory cells.