JPH11316834A - IC circuit device of image forming apparatus and control method therefor - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] An IC circuit device of an image forming apparatus capable of performing an operation of an IC with a simple configuration to access an element having a restriction when power is supplied to the image forming apparatus, and a control thereof. Provide a way. A after power to the image forming apparatus, the reset IC204 is an operation start signal R1 after a predetermined time t1 has elapsed sends to the memory controller 202, memory controller 202 thereby to operate the hard counters, t ₁
From the hardware counter after the elapse of Δt from
To the CPU 201 to start the operation of the CPU 201. After receiving the operation start signal R2, the CPU 201
Since access to the DRAM 203 is started via the memory controller 203, after the DRAM 203 enters a standby state after a predetermined time has elapsed after power-on, the CP
The U201 itself can start the operation of the CPU 201 without having a timer and without performing special software management.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an IC circuit device for an image forming apparatus and a control method thereof.

[0002]

2. Description of the Related Art Conventionally, an image forming apparatus has an IC circuit system as shown in FIG. FIG. 1 is a schematic configuration diagram of a conventional IC circuit system. The IC circuit system shown in FIG. 1 includes a CPU 101, a memory controller 102, and a DRAM 103 connected in series.
01 is connected to the reset IC 104.

[0003] A CPU 101 manages the entire IC circuit system. The memory controller 102 has a memory array or the like, and the DRAM 103 is controlled by the memory controller 102 and is accessible from the CPU 101 via the memory controller 102. Reset IC
Reference numeral 104 denotes an operation start signal to the CPU 101 when the power supply to the image forming apparatus is turned on.

However, there is a limitation that the DRAM 103 cannot be accessed before a predetermined time elapses from when the power to the image forming apparatus is turned on and enters a standby state after the predetermined time elapses. The CPU 101 itself manages the elapsed time from when the power is turned on by using a timer or the like, and confirms that a predetermined time has elapsed before performing the operation.

[0005]

SUMMARY OF THE INVENTION However, CPU
DRAM 10 as described above as a work RAM 101
3, the CPU 101 accesses the DRAM 103 using a timer or the like for measuring the elapsed time from the power-on so that the CPU 101 itself checks that a predetermined time has elapsed since the power-on. Need and
When an inexpensive circuit IC system is to be constructed, there is a problem that it becomes a factor of cost increase, and management of software becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide an IC circuit device of an image forming apparatus capable of controlling operation start of an IC for accessing an element having a limited access time at the time of power-on to the image forming apparatus with a simple configuration. An object of the present invention is to provide a control method.

[0007]

According to another aspect of the present invention, there is provided an IC circuit device for an image forming apparatus, comprising: a first IC which starts operation in response to a first operation start signal; A second IC that accesses an element having a limitation on the accessible time when the power is turned on and starts the operation in response to a second operation start signal.
In the C circuit device, after the first IC is started to operate by the first operation signal and the initialization is completed, the second IC is operated.
And generating the second operation start signal.

According to a second aspect of the present invention, there is provided an image forming apparatus comprising:
It is characterized in that after the end of the initial setting, a predetermined time has elapsed.

According to a third aspect of the present invention, there is provided an IC circuit device for an image forming apparatus according to the first or second aspect, wherein the second IC is connected to the first IC during the accessible time. The method is characterized in that access to an element having a restriction is performed.

According to a fourth aspect of the present invention, there is provided an IC circuit device for an image forming apparatus according to any one of the first to third aspects.
In the C circuit device, the second IC is a CPU.

According to a fifth aspect of the present invention, there is provided an IC circuit device for an image forming apparatus according to any one of the first to fourth aspects.
In the C circuit device, the first IC is a memory controller.

According to a sixth aspect of the present invention, there is provided an image forming apparatus comprising:
In the C circuit device, the element having a limitation on the accessible time is a DRAM.

According to another aspect of the present invention, there is provided a method for controlling an IC circuit device of an image forming apparatus, comprising: a first IC which starts operation in response to a first operation start signal; And a second IC that starts operation by a second operation start signal while accessing an element having a limitation on the accessible time at the time when the first IC is connected to the first IC. , The first
After the operation is started, the second
Wherein the second operation start signal is generated for the IC.

According to an eighth aspect of the present invention, there is provided a method of controlling an IC circuit device of an image forming apparatus according to the seventh aspect of the present invention, wherein a predetermined time has elapsed after the completion of the initial setting. And

According to a ninth aspect of the present invention, there is provided a method of controlling an IC circuit device of an image forming apparatus according to the seventh or eighth aspect, wherein the second IC is connected via the first IC. And accessing an element having a limitation on the accessible time.

According to a tenth aspect of the present invention, there is provided a method of controlling an IC circuit device of an image forming apparatus according to any one of the seventh to ninth aspects, wherein the second IC is a CPU. There is a feature.

The method of controlling an IC circuit device of an image forming apparatus according to claim 11 is the method of controlling an IC circuit device of an image forming apparatus according to any one of claims 7 to 10, wherein
Is a memory controller.

According to a twelfth aspect of the present invention, there is provided a method of controlling an IC circuit device of an image forming apparatus according to any one of the seventh to eleventh aspects, wherein the accessible time is limited. The element is a DRAM.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a schematic configuration diagram of an IC circuit device according to an embodiment of the present invention.

The IC circuit device shown in FIG. 2 is configured for an image forming apparatus. 1 includes a CPU 201 (second IC), a memory controller 202 (first IC), and a DRAM 203 (accessible time) connected in series via bus lines 207 and 208 such as a data bus. The memory controller 202 is connected to a reset IC 204.

The CPU 201 manages the entire IC circuit device. The memory controller 202 has a memory array and the like, appropriately converts an access signal when the CPU 201 accesses the DRAM 203, and sends an operation start signal R2 to the CPU 201.

The DRAM 203 is a memory controller 20
2 and is accessible by the CPU 201 via the memory controller 202 as described above, and operates as a work RAM for the CPU 201 to operate. However, there is a limitation that the DRAM 203 cannot be accessed before a predetermined time elapses from when the power to the image forming apparatus is turned on, and enters a standby state after the predetermined time elapses. The memory controller 202 has an operation signal generation circuit shown in FIG.

The reset IC 204 sends an operation start signal R1 to the memory controller 202 after a predetermined time t1 described later has elapsed since the power of the image forming apparatus was turned on. In the operation start time R1, an accessible time to the memory controller 202 after the power of the image forming apparatus is turned on is set in advance.

The memory controller 202 has an operation signal generation circuit shown in FIG.

FIG. 3 is a circuit diagram of an operation signal generation circuit provided inside the memory controller 202.

The operation signal generation circuit shown in FIG. 3 includes a hard counter 301, a hard counter 302, and a hard compare circuit 303. The hardware counter 301 includes a system clock of the image forming apparatus, a reset IC 204
The operation start signal R1 transmitted from is input. The operation start signal R1 is also input to the hard counter 302 at the same time. The hard counter 301 counts the system clock after receiving the operation start signal R1 and outputs the counter value t to the hard compare circuit 303.

The count value t as the output of the hard counter 301 is input to one input of the hard compare circuit 302. A predetermined time Δt set in advance is input to the other input of the hard compare circuit 302. The hard compare circuit 302 compares the count value t with a predetermined time Δt, and outputs a predetermined time elapsed signal s indicating that t ≧ Δt to the hard counter 302.

An operation start signal R2 is further input to the hard counter 302, and the hard counter 302
The CPU 2 outputs the operation start signal R2 when the predetermined time elapse signal s is received while the operation start signal R1 is received.
01. In the operation start signal R2, an accessible time to the DRAM 203 after the operation of the memory controller 203 is started is set in advance.

The operation of the present embodiment will be described below with reference to FIG. FIG. 4 is a timing chart of the IC circuit device according to the embodiment of the present invention.

When the power of the image forming apparatus is turned on and a predetermined time t1 in FIG. 4 elapses, an operation start signal R1 is sent from the reset IC 204 to the memory controller 202, and the memory controller 202 is activated and the memory controller 202 is activated. Start operation. At this time, the operation start signal R2 for the CPU 201 is still in an inactive state, and the operation of the CPU 201 has not started.

When receiving the operation start signal R1, the memory controller 202 operates the internal hard counter 301. Next, the memory controller 202 causes the hard counter 304 to perform an access method to the DRAM 203 within the predetermined time Δt and perform an initial setting inside the memory controller 202, and further, after the predetermined time Δt elapses, activates the hard counter 304 to change the operation start signal R2 to the CP.
It is sent to U201 to start the operation of the CPU 201.
The CPU 201 that has received the operation start signal R2 starts accessing the DRAM 203 via the memory controller 203.

According to the present embodiment, after the power supply to the image forming apparatus is turned on, the reset IC 204 sends the operation start signal R1 to the memory controller 202 after a predetermined time t1 has elapsed, and the memory controller 202 sends the operation start signal R1. Upon receipt, the internal counter 301 is operated, and after the elapse of a predetermined time Δt, the hard counter 304 is operated, and an operation start signal R2 is sent to the CPU 201 so that the CPU 201
The operation of 201 is started. Since the CPU 201 that has received the operation start signal R2 starts accessing the DRAM 203 via the memory controller 202, the DRAM 203 having a time limit until the image forming apparatus can be accessed when the power is turned on after the predetermined time elapses After entering the standby state, the CPU 201 itself does not have a timer and does not perform any special software management.
201 can be started.

[0034]

As described above in detail, according to the IC circuit device of the image forming apparatus and the control method thereof according to the first and seventh aspects, the first IC starts operating in response to the first operation signal. Since the second operation start signal is generated for the second IC after the completion of the post-initialization, after the operation start signal R2 is received, the second IC is limited in the accessible time when the power is turned on. Access to the second IC, the second IC itself does not have a timer and does not perform any special software management after the element enters the standby state after the initialization and after the initialization. Can be started.

According to the IC circuit device of the image forming apparatus and the control method therefor, the first IC is provided.
Generates a second operation start signal to the second IC after a lapse of a predetermined time from the start of operation by the first operation signal. Therefore, after the element enters the standby state after the lapse of the predetermined time, the second operation starts. The second IC itself can be started to operate without having a timer and without performing special software management.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a conventional IC circuit system.

FIG. 2 is a schematic configuration diagram of an IC circuit device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of an operation signal generation circuit provided inside a memory controller 202;

FIG. 4 is a timing chart of the IC circuit device according to the embodiment of the present invention.

[Explanation of symbols]

 201 CPU 202 Memory controller 203 DRAM 204 Reset IC 207, 208 Data bus line R1, R2 Operation start signal

Claims (12)

[Claims] 1. An image forming apparatus comprising: a first IC which starts operation in response to a first operation start signal;
And a second IC that starts the access operation in response to the operation start signal.
An IC circuit device for an image forming apparatus, wherein the first IC generates the second operation start signal for the second IC after the operation is started by the first operation signal and after the initialization is completed. . 2. The image forming apparatus according to claim 1, wherein a time after the completion of the initialization is a predetermined time.
C circuit device. 3. The IC for an image forming apparatus according to claim 1, wherein the second IC accesses an element having a limit on the accessible time via the first IC. Circuit device. 4. The IC circuit device for an image forming apparatus according to claim 1, wherein said second IC is a CPU. 5. The IC circuit device for an image forming apparatus according to claim 1, wherein said first IC is a memory controller. 6. The IC circuit control device for an image forming apparatus according to claim 1, wherein the element having a limitation on the accessible time is a DRAM. 7. An image forming apparatus comprising: a first IC which starts operation in response to a first operation start signal;
And a second IC that starts the access operation in response to the operation start signal of the above, wherein the initial setting is completed after the operation of the first IC is started by the first operation signal. A method of controlling an IC circuit device of an image forming apparatus, wherein the second operation start signal is generated for the second IC later. 8. The image forming apparatus according to claim 7, wherein a predetermined time has elapsed after the completion of the initial setting.
Control method of C circuit device. 9. The IC according to claim 7, wherein the second IC accesses an element having a limit on the accessible time via the first IC. Circuit device control method. 10. The method of controlling an IC circuit device of an image forming apparatus according to claim 7, wherein said second IC is a CPU. 11. The method according to claim 7, wherein the first IC is a memory controller. 12. The device according to claim 7, wherein the element having a limitation on the accessible time is a DRAM.
2. The control method for an IC circuit control device of an image forming apparatus according to claim 1.