JPH11307816A - Package structure for chip semiconductor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a package structure in which no peeling nor disconnection occurs at the time of mounting the structure on a body and which does not cause a short circuit, has a superior light emitting ability, and can be manufactured with high productivity as a single package body. SOLUTION: The package 1 of a chip semiconductor 10 is formed by coating the exposed surface of the semiconductor chip 10 after electrodes 11 and 12 are respectively stuck to the P- and N-layer side end faces 10a and 10b of the chip 10. The package 1 is constituted in such a way that the package 1 has end faces 1a and 1b respectively faced to the P- and N-layer side end faces 10a and 10b of the semiconductor 10 and the electrodes 11 and 12 are formed by plating so that the electrodes 11 and 12 may be firmly stuck to the end faces 10a and 10b, and then, the external surfaces of the electrodes 11 and 12 are exposed on parts of the end faces 1a and 1b of the package 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type semiconductor package structure suitable for electrically connecting a chip type semiconductor such as a light emitting diode (hereinafter, referred to as an LED) to wiring on a circuit board. More particularly, the present invention relates to a surface mount type package structure of a chip type semiconductor suitable for mounting on a printed circuit board.

[0002]

2. Description of the Related Art Conventionally, an example of a package structure of a surface mount type relating to a chip type semiconductor is disclosed in, for example, JP-A-9-45.
No. 964 is disclosed. FIG. 18 is a perspective view showing the manufacturing method. As shown in FIG. 18 (a), for example, a paste-like conductive bonding material 113 is provided on one surface of one electrode plate 111 at a predetermined pitch. P
Are applied in the form of dots in a row and column by a printing means or the like, and each of the plurality of LED chips 114 has one pole,
For example, it is placed on each of the bonding materials 113 so as to be in contact with the N layer side. Also, one surface of the other electrode plate 112 is also applied vertically and horizontally at the same pitch p, and when the mounting of the LED chip 102 on the bonding material 113 of the one electrode plate 111 is completed, The other electrode plate 112 is the bonding material 1
13 with the other pole of the LED chip 102, for example, P
The LED chip 114 is placed so as to overlap on the layer side, whereby the LED chip 114 is sandwiched between the electrode plates 111 and 112.

[0003] While maintaining the above-mentioned state, it is passed through a heating furnace called a reflow furnace to melt the bonding material 113,
Bonded to each pole side of the LED chip 102, FIG.
As shown in (b), the electrode plates 111, 112 and L
The ED chip 102 is integrated.

Next, as shown in FIG. 18C, a transparent resin 115 such as an epoxy resin is injected between the electrode plate 111 and the electrode plate 112 and is cured. At this time, the L
All of the four exposed surfaces of the ED chip 114 are covered with the transparent resin 115. Subsequently, a predetermined pitch P, which is the interval between the LED chips 102, is cut by a thin diamond wheel cutter or the like so as to bisect the LED chip 102, thereby obtaining the LED chip package 110. FIG. 19 shows the package 110 mounted on the printed circuit board 12.
FIG. 3 is a cross-sectional view showing a state where the pad is attached to the printed circuit board 120. A pair of pads 121 are provided at predetermined intervals on the printed circuit board 120, and a bonding material 123 made of paste solder is applied. The package 117 is placed so that the electrode plates 111 and 112 are positioned, heated in a reflow furnace to melt the solder 123, and the pair of pads 121 and the electrode plates 111 and 112 are welded, respectively, to print the package 110. The surface mounting on the circuit board 120 is performed.

[0005]

According to such a package structure, a structure in which no gold wire is used is used, so that a space for arranging the wires can be omitted and the size of the package can be reduced. In addition, since a large number of individual products can be formed in the manufacturing process, the cost can be reduced as a whole manufacturing cost. However, such an improved package structure has the following disadvantages.

That is, as shown in FIG. 18B, the conductive bonding material 113 used when integrating the electrode plate 111, the electrode plate 112, and the LED chip 102 is as follows.
Conventionally, Ag paste or ACF (anisotropic conductive film), which can be cured at 200 ° C. or lower, is sometimes used because it is convenient in terms of handling. However, as shown in FIG. 19, in the case where the package 110 is heated to 220 to 240 ° C. in a reflow furnace or the like in order to melt the bonding material 123 made of the solder in the surface mounting on the printed circuit board 120. There are many. In such a case, Ag paste or ACF by heat of heating
The electrode plate 111 or the electrode plate 112 peels off from the LED chip 102 due to a decrease in the adhesive force of the bonding material 113 and a stress caused by a difference in linear expansion coefficient.
In many cases, the ED chip 102 cannot be turned on.

Also, in the bonding process already described with reference to FIGS. 18A and 18B, an Ag paste used as a bonding material 113 when bonding the electrode plate 111 and the electrode plate 112 to the LED chip 102 By protruding,
One electrode plate 111 and the other electrode plate are the LED chip 10
In many cases, the P layer and the N layer are short-circuited due to the protruding Ag paste in the vicinity of the area 2 or in the junction of the LED chip 102. Thus, the electrode plate 1 in the package 110 is formed.
Because of the short circuit between 11 and 112, the LED chip 114 in the package 110 cannot be turned on or has a defective lighting. In addition, even if the short circuit does not occur in the vicinity of the LED chip 114 due to the protrusion of the Ag paste or the like, the bonding material 113 adheres to or is close to part or most of the side surface of the LED chip 114. Not a few. In this case, when the package 110 is mounted on a printed board or the like and the LED chip 114 emits light, the emitted bonding material 113 blocks the light emission, and the light emission intensity of the package 117 decreases.

In order to improve such disadvantages, FIG.
As shown in (a) and (b), when the electrode plate 111 and the electrode plate 112 are joined to the LED chip 102, it is conventionally possible to use a high-temperature solder having a melting point of about 280 ° C. as the joining material 113. Has been done. According to this method,
Although the above-described problems such as disconnection can be solved, the cost of the high-temperature solder itself is high, and it is necessary to improve the electrodes of the semiconductor element such as the LED chip 102 for soldering, which further increases the cost. Furthermore, when joining a semiconductor element such as the LED chip 102 to the electrode plates 11 and 12, heat of about 280 ° C. is applied, so that the electrode plates 11 and 12 are warped, and the quality and reliability of the package 110 are reduced. Sometimes.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate and improve the above-mentioned disadvantages in the conventional chip type semiconductor package structure. The present invention solves this problem, and is compact, suitable for surface mounting, has no peeling or disconnection at the time of surface mounting, has excellent light emitting performance and reliability, does not increase cost, and has a high production yield. It is an object of the present invention to provide a high chip type semiconductor package structure and a method of manufacturing a package having such a structure with high productivity.

[0010]

As a first means for solving the above-mentioned problems, the present invention relates to a semiconductor chip,
In a chip type semiconductor package structure in which separate electrodes are respectively joined to both end surfaces on the layer side and the N layer side, and the exposed surface of the semiconductor chip is covered with a resin, the package is composed of the P layer of the semiconductor chip. The package has end faces opposed to both end faces on the N-side and the N-layer side, and the electrodes are fixed to the end faces of the semiconductor chip and formed by plating, and at least a part of the package end face has an outer surface of the electrode. It is characterized by being exposed.

According to a second aspect of the present invention, in order to solve the above problems, in the first aspect, the semiconductor chip is an LED chip, and the resin is a light-transmitting resin. .

As a third means for solving the above-mentioned problems, the present invention provides a heat-resistant sheet having an adhesive on one side at one end on a lower end surface of a frame member having a notch in at least a part thereof. Attaching a plurality of semiconductor chips in a matrix on the upper surface of the heat-resistant sheet with the adhesive, and arranging the plurality of semiconductor chips in a P-layer side or an N-layer side. Bonding a heat-resistant sheet with an adhesive on one side to the upper end surface of the bonded semiconductor chip and the upper end surface of the frame member with the surface with the adhesive facing down to form a filling space. Performing a step of injecting a resin into the filling space using the cutout portion of the frame member as an injection port and curing and sealing a side surface of the semiconductor chip, and after curing the injected resin, Paste A step of peeling the heat-resistant sheet, and after peeling the heat-resistant sheet, the upper surface and the lower surface of the integrated sealing assembly in which the semiconductor chip and the injection resin are exposed are made of a conductive material such as gold or copper. Fixing the electrode film by plating and conducting the semiconductor chip and the electrode film, after the plating, surrounds the semiconductor chips arranged in a matrix, and seals the sealing along a cut surface along the vertical and horizontal directions of the matrix. Cutting the assembly and forming individual chip-type semiconductor packages. A chip-type semiconductor package is manufactured by a manufacturing method.

As a fourth means for solving the above-mentioned problems, the present invention provides a heat-resistant sheet having an adhesive on one side, and a heat-resistant sheet having the above-mentioned adhesive facing up. A step of arranging a plurality of semiconductor chips in a matrix and joining one of the end faces on the P-layer side and the N-layer side, a heat-resistant sheet having an adhesive on one side on an upper end face of the joined semiconductor chips; A step of attaching the adhesive with the surface with the adhesive down, by attaching a heat-resistant tape to the outer surface portion of the heat-resistant sheet attached to the upper and lower sides,
A step of forming a filling space by partially filling and closing a resin injection port, a step of injecting a resin into the filling space from the resin injection port, and then curing and sealing the side surface of the semiconductor chip; and curing the resin. Thereafter, a step of peeling off the heat-resistant sheet and the heat-resistant tape, and after peeling off the heat-resistant sheet and the heat-resistant tape, the upper surface and the lower surface of the integrated sealing assembly in which the semiconductor chip and the injected resin are exposed. A step of fixing an electrode film made of a conductive material such as copper by plating, and conducting the semiconductor chip and the electrode film. After the plating, surrounding the semiconductor chips arranged in a matrix, cutting along the vertical and horizontal directions of the matrix. Forming a package of individual chip-type semiconductors by cutting the assembly of the sealings along a surface. Characterized in that it produced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIGS. 1A and 1B are views showing the structure of a chip-type semiconductor package 1 according to the present embodiment, wherein FIG. 1A is a perspective view and FIG. 1B is a sectional view. In FIG. 1, reference numeral 10 denotes a semiconductor chip formed by joining a P layer and an N layer, such as an LED chip. Reference numeral 15 denotes a resin for sealing the semiconductor chip 10, and is, for example, a translucent resin. Reference numerals 11 and 12 denote electrode films made of a metal film such as copper or gold, and each of the end surfaces 10a and 10b is one of the end surfaces on the P layer side and the N layer side of the semiconductor chip 10.
10b and the end surfaces of the sealing resin 15 on the same plane as these end surfaces are fixed by plating. Here, a single-layer or multi-layer plating is selected as the plating depending on the application or need. As a result, the semiconductor chip 10 has the electrode films 1 on the end faces 10a and 10b, respectively.
1 and 12, respectively. The outer surfaces of the electrode films 11 and 12 are connected to the end surfaces 10 a and 1
0b, the end surfaces 1a and 1b of the package 1 facing each other.
It has become.

FIGS. 2A and 2B are views showing the structure of a modification of the chip-type semiconductor package 1 shown in FIG. 1, wherein FIG. 2A is a perspective view and FIG. 2B is a sectional view. As shown in FIG. 2, in the package of the present embodiment, electrode films 11 and 12 made of a metal film such as copper or gold are fixed to a part of the end surfaces 10a and 10b of the semiconductor chip 10 by plating. The remaining exposed portions of the end surfaces 10a and 10b are
5. Here, a single-layer or multi-layer plating is selected as the plating depending on the application or need. In this example, the end faces 1a and 1b of the package 1 facing the end faces 10a and 10b of the semiconductor 10, respectively,
The end surface 1a is constituted by the outer surface of the electrode film 11 and the outer surface of the resin 15, and the end surface 1b is constituted by the outer surface of the electrode film 12 and the outer surface of the resin 15.

According to the structure of the chip type semiconductor package 1 shown in FIG. 1 or FIG.
Since the bonding between the semiconductor chips 1 and 12 and the semiconductor chip 10 is performed by plating without using a bonding material as described later in detail, the electrodes are bonded by using a high-temperature solder in the conventional example as shown in FIG. Warping by high-temperature heating does not occur as in the case. Further, an increase in cost due to the use of high-temperature solder can be avoided. Further, in the conventional example, as in the case where the electrodes are joined using an Ag paste, conductive joining materials made of the Ag paste protruding from the upper and lower end surfaces of the semiconductor chip are connected to each other or adhere to the junction. Does not cause a phenomenon of short-circuit.

Further, when an LED chip is used as each semiconductor chip 10, the conductive bonding material made of the Ag paste or ACF protruding from the upper and lower end surfaces as in the related art does not cause a short circuit even if the conductive material does not short-circuit. The phenomenon that the light emission from the side surface is blocked and the light emission intensity of the package 1 is reduced does not occur.

FIG. 3 is a sectional view showing a state in which the chip-type semiconductor package 1 shown in FIG. 1 is surface-mounted on a printed circuit board. Reference numeral 20 denotes a printed circuit board, which includes a circuit board 21 and a pair of pads 22 made of copper, gold, and the like provided on the circuit board 21 at predetermined intervals. A bonding material 23 made of paste-like solder is applied, and the package 1 is placed on the pad 22 so that the electrode films 11 and 12 are located. C to form a bonding material 23 made of the solder
And the pair of pads 22 and the electrode films 11 and 12 are welded to each other, and the printed circuit board 20 of the package 1 is melted.
Surface mounting is performed. At this time, the electrode films 11 and 12
Coefficient of thermal expansion (1.62 × 10 ⁻⁵ / when the electrode film is copper)
k) and the coefficient of thermal expansion of the sealing resin 15 (4 to 6 × 10 ⁻⁵ / ° C. in the case of a transparent epoxy resin), and the coefficient of thermal expansion between the electrode films 11 and 12 and the semiconductor chip 10. Due to the difference, the electrode films 11, 12 and the resin 15, the semiconductor chip 10
At the interface, shear thermal stress is generated to separate them from each other.

The electrode films 11 and 12 of this embodiment are firmly fixed to the semiconductor chip 10 and the like by plating without using a bonding material. Therefore, in the surface mounting as shown in FIG. 3, even if the above-mentioned heating for melting the solder 23 is performed, copper,
The surfaces of the electrode films 11 and 12 made of gold or the like are slightly melted and fixed with sufficient strength. Accordingly, the shear is considerably stronger than before. Further, this thermal stress is proportional to the thickness of the electrode films 11 and 12. The electrode terminals 11 and 12 of this example are metal films formed by plating, and the conventional package structure shown in FIGS. Can be formed to be much smaller in thickness than the electrode terminal cut out from the electrode substrate. Therefore,
The thermal stress of such shearing is considerably lower than before. By these effects, disconnection between the electrode terminal and the semiconductor chip due to peeling as in the related art is effectively prevented, and the chip-type semiconductor package 1 is prevented from being unable to light. Thus, a chip-type semiconductor package structure having high durability and high reliability in surface mounting can be realized.

Hereinafter, one method of manufacturing the chip-type semiconductor package 1 according to this embodiment shown in FIG. 1 will be described with reference to the drawings. As shown in FIG. 4, at least one surface is provided with an adhesive on at least one lower surface of a frame member 37 formed by molding resin, rubber, or the like, and having a cutout as the resin injection port 18. A heat-resistant sheet 26 made of a film and having heat resistance is attached with the pressure-sensitive adhesive face up.

Next, as shown in FIG. 5, one of the end faces of the P layer side and the N layer side of the semiconductor chip 10 is attached to the lower end face of the frame member 37 and on the adhesive face of the heat-resistant sheet 26. It is arranged and placed in a matrix in a downward direction, and is attached and fixed to the adhesive surface.

Next, as shown in FIG. 6, the heat-resistant sheet 26 similar to the above is attached to the upper surface of the arranged semiconductor chips 10 and the upper end surface of the frame member 37 with the adhesive surface thereof facing down. Thereby, the frame member 37 and the upper and lower heat-resistant sheets 2
A filling space surrounded by 6 is formed.

Next, as shown in FIG.
After the resin 15 is injected from the resin injection port 18 provided in the above and the filling space is filled, curing is performed. Here, as shown in FIG. 7 (b), the resin
In the case where it is provided at a location, the entire side of the frame member 37 may be the resin injection port 18 as shown in FIG. If necessary, the frame member 37 may be provided with a hole (not shown) for venting air at the time of filling.

Next, as shown in FIG. 8, the upper and lower heat-resistant sheets 26 are peeled off to expose the upper and lower end surfaces of the semiconductor chip 10 and the filled resin 15.

Next, as shown in FIG.
The electrode films 11 and 12 are fixed to the upper and lower end surfaces of the resin 15 (including the upper and lower end surfaces of the frame member 37) by plating with copper, gold, or the like.

Next, as shown in FIG. 10, using a diamond wheel, a multi-wire saw, or the like, a sealed assembly 30 in which the electrode films 11 and 12 are formed on the upper and lower end surfaces, respectively, is connected to each semiconductor chip. 10 are cut along predetermined dicing lines L at predetermined positions in the vertical and horizontal directions. Thereby, the package 1 shown in FIG. 1 is separated and cut out individually, and the structure of the chip-type semiconductor package 1 according to the present embodiment is completed.

Hereinafter, another manufacturing method of the chip-type semiconductor package 1 according to the present embodiment shown in FIG. 1 will be described with reference to the drawings. As shown in FIG. 11, a heat-resistant sheet 26 similar to that already shown and described in FIG. 4 is placed on the P layer side and the N layer of the semiconductor chip 10 on the adhesive surface with the adhesive surface with the adhesive agent facing upward. One of the sides is arranged, placed, attached, and fixed in a matrix with one end face down.

Next, as shown in FIG. 12, the heat-resistant sheet 26 similar to the above is attached to the upper surface of the arranged semiconductor chips 10 with the adhesive surface thereof facing down.

Next, as shown in FIG. 13, a heat-resistant tape 17 is adhered to the outer ends of the upper and lower heat-resistant sheets 26, and the space between the resin-sealed ports 18 is closed to form a filling space. At this time, the heat-resistant tape 17 can be adhered so as to leave a plurality of resin sealing ports 18 or, if necessary, although not shown, air vent holes for resin sealing.

Next, as shown in FIG. 14, the resin 15 is injected from the resin injection port 18 to fill the filling space and then cured.

Next, as shown in FIG. 15, after the filled resin 15 is cured, the upper and lower heat-resistant sheets 26 adhered to each other and the heat-resistant tape 1 adhered to their outer surfaces are adhered.
7 is peeled off. As a result, a sealed assembly 30 is obtained. Here, the resin 1 is placed on the upper and lower surfaces of the sealing assembly 30.
5 and the upper and lower end faces of the semiconductor chip 10 are exposed.

Next, as shown in FIG.
0 upper and lower surfaces (the side surfaces of the sealing assembly may be included)
The electrode films 11 and 12 are fixed by plating with copper, gold or the like, respectively.

Next, as shown in FIG. 17, a sealed assembly 30 in which the electrode films 11 and 12 are fixed on the upper and lower surfaces is formed in a predetermined vertical and horizontal direction by the same method as described with reference to FIG. Cut along the dicing line L at the position. Thereby, the package 1 shown in FIG. 1 is separated and cut out individually, and the structure of the chip-type semiconductor package 1 according to the present embodiment is completed.

As described above, according to the above-described manufacturing method, it is possible to manufacture the above-described excellent chip-type semiconductor package while improving the production efficiency by multi-cavity production.

[0035]

As described above, according to the present invention, it is small in size, suitable for surface mounting, has no peeling or disconnection during surface mounting, is excellent in light emitting performance and reliability, and has a high production yield. It is possible to provide a chip-type semiconductor package having a very high structure and a method of manufacturing a package having such a structure with high productivity.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams illustrating a structure of a chip-type semiconductor package according to an embodiment of the present invention, wherein FIG. 1A is a perspective view and FIG. 1B is a cross-sectional view.

FIG. 2 is a sectional view showing a modification of the structure of the chip-type semiconductor package shown in FIG. 1;

FIG. 3 is a cross-sectional view showing a method of surface mounting the chip-type semiconductor package shown in FIG.

FIG. 4 is a perspective view showing a step of assembling a molding jig member in the method of manufacturing the chip-type semiconductor package shown in FIG. 1;

FIG. 5 is a perspective view showing a process of arranging and fixing semiconductor chips to a molding jig member in the method of manufacturing a chip-type semiconductor package shown in FIG. 1;

FIG. 6 is a perspective view showing a step of forming a filling space from a semiconductor chip and a molding jig member in the method of manufacturing the chip-type semiconductor package shown in FIG.

FIG. 7 is a perspective view showing a step of filling a filling space with a resin in the method of manufacturing the chip-type semiconductor package shown in FIG. 1;

FIG. 8 is a perspective view showing a step of exposing a molding jig member to expose upper and lower surfaces of a filling resin or the like in the method of manufacturing the chip-type semiconductor package shown in FIG.

9 is a perspective view showing a step of fixing an electrode film to the exposed upper and lower surfaces of a filling resin or the like by plating in the method of manufacturing a chip-type semiconductor package shown in FIG. 1;

10 shows a method for manufacturing a chip-type semiconductor package shown in FIG. 1, in which the filling resin or the like having the electrode films fixed on the upper and lower surfaces is cut along predetermined vertical and horizontal dicing lines to cut out individual packages. It is a perspective view showing a process.

FIG. 11 is a perspective view showing a step of arranging and fixing semiconductor chips to a molding jig member in another method of manufacturing the chip-type semiconductor package shown in FIG. 1;

FIG. 12 is a perspective view showing a step of attaching a molding jig member to the arranged semiconductor chips in another method of manufacturing the chip-type semiconductor package shown in FIG.

13 is a perspective view showing a step of forming a filling space from a molding jig member including a semiconductor chip and a heat-resistant tape in another method of manufacturing the chip-type semiconductor package shown in FIG.

14 is a perspective view showing a step of filling a filling space with a resin in another method of manufacturing the chip-type semiconductor package shown in FIG. 1. FIG.

FIG. 15 is a perspective view showing a step of exfoliating a molding jig member and exposing upper and lower surfaces of a filling resin or the like in another method of manufacturing the chip-type semiconductor package shown in FIG.

FIG. 16 is a perspective view showing a step of fixing an electrode film to the exposed upper and lower surfaces of a filling resin or the like by plating in another method of manufacturing the chip-type semiconductor package shown in FIG. 1;

FIG. 17 is a cross-sectional view showing another method of manufacturing the chip-type semiconductor package shown in FIG. 1;
It is a perspective view which shows the process of cutting out the completed product of each package.

FIG. 18 is a perspective view showing a conventional method for manufacturing a chip-type semiconductor package.

19 is a cross-sectional view showing a method of surface mounting a conventional chip-type semiconductor package manufactured by the manufacturing method shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Package 1a, 1b, 10a, 10b End surface 10 Semiconductor chip 11, 12 Electrode film 15 Resin 17 Heat resistant tape 26 Heat resistant sheet 37 Frame member

Claims (4)

[Claims] 1. A chip type semiconductor package structure in which separate electrodes are respectively joined to both end surfaces on a P layer side and an N layer side of a semiconductor chip, and an exposed surface of the semiconductor chip is covered with a resin. The package has a package end face opposed to both end faces on the P layer side and the N layer side of the semiconductor chip, and the electrodes are fixed to the both end faces of the semiconductor chip and formed by plating, and at least the package end face is formed. A chip semiconductor package structure, wherein an outer surface of the electrode is partially exposed. 2. The package structure according to claim 1, wherein the semiconductor chip is an LED chip, and the resin is a translucent resin. 3. A step of attaching a heat-resistant sheet having an adhesive on one side to a lower end surface of a frame member having a cutout at least in a part thereof, with the surface having the adhesive facing up. A step of arranging a plurality of semiconductor chips in a matrix on the top surface with the adhesive and joining one of the end surfaces on the P layer side and the N layer side, the upper end surface of the joined semiconductor chip and Attaching a heat-resistant sheet with an adhesive on one side to the upper end surface of the frame member with the surface with the adhesive facing down to form a filling space, and filling the cutout portion of the frame member with the cutout portion as an inlet. A step of curing after injecting a resin into a space and sealing a side surface of the semiconductor chip, a step of peeling off the heat-resistant sheets attached to the upper and lower end faces after curing the injected resin, and a step of peeling the heat-resistant sheet Thereafter, an electrode film made of a conductive material such as gold or copper is fixed on the upper and lower surfaces of the integrated sealing assembly in which the semiconductor chip and the injected resin are exposed, by plating. Conducting a,
Enclosing the semiconductor chips arranged in a matrix after the plating, cutting the assembly of the encapsulation along cutting planes along the vertical and horizontal directions of the matrix, and forming individual chip-type semiconductor packages. A method for manufacturing a chip-type semiconductor package, comprising: 4. A heat-resistant sheet having an adhesive on one side, a plurality of semiconductor chips arranged in a matrix on the surface with the adhesive, with the surface with the adhesive facing upward, and a P layer side and an N-layer. Bonding one of the end faces on the layer side, affixing a heat-resistant sheet with an adhesive on one side to the upper end face of the bonded semiconductor chip with the surface with the adhesive facing down, A step of forming a filling space by pasting and closing a portion serving as a resin injection port by attaching a heat-resistant tape to an outer surface portion of the heat-resistant sheet stuck on the upper and lower sides, the filling space from the resin injection port. After injecting a resin, curing and sealing the side surface of the semiconductor chip, curing the resin, removing the heat-resistant sheet and heat-resistant tape, peeling off the heat-resistant sheet and heat-resistant tape, An electrode film made of a conductive material such as gold or copper is fixed on the upper and lower surfaces of the integrated sealing assembly in which the semiconductor chip and the injected resin are exposed by plating, and the semiconductor chip and the electrode film are conducted. Forming a package of individual chip-type semiconductors after surrounding the semiconductor chips arranged in a matrix after the plating, and cutting the assembly of the encapsulation along a cut surface along the vertical and horizontal directions of the matrix. And a method of manufacturing a chip-type semiconductor package.