JPH11297700A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To reliably prevent corrosion of a metal wiring or a metal plug formed by using a CMP method. SOLUTION: Above a p-type semiconductor region 4 constituting a terminating resistance element (R), a light shielding layer 20 made of, for example, a Cu film is provided.
Are formed. The light shielding layer 20 is made of a silicon oxide film 21
Is formed at the same time as the step of forming the second-layer wirings 17 to 19 by polishing the Cu film deposited on the upper portion by the CMP method, and has a wide area covering almost the entire area of the p-type semiconductor region 4. I have. By disposing the light-shielding layer 20 above the p-type semiconductor region 4, it is possible to prevent light from entering the p-type semiconductor region 4 in the step of forming the wirings 17 to 19 by polishing the Cu film by the CMP method. Pn
Corrosion of the wirings 17 to 19 due to photocurrent generated by light entering the junction is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly, to a semiconductor integrated circuit device having metal wiring formed by a chemical mechanical polishing (CMP) method. Effective technology.

[0002]

2. Description of the Related Art Conventionally, as a method of forming an LSI wiring, a high melting point metal film such as an aluminum (Al) alloy film or tungsten (W) is deposited on a silicon substrate (wafer) by using a sputtering method or the like, and then a photolithography is performed. A method of patterning the metal film by dry etching using a resist film as a mask is generally used.

However, due to the recent miniaturization of LSIs, the above-mentioned method has a remarkable increase in wiring resistance due to the miniaturization of wiring width, and particularly in high-performance logic LSIs,
It has become a major factor that hinders its performance. Therefore, recently, for example, "1993 VMIC (VLSI Multilevel
Interconnection Conference) Proceedings ", p15-p2
As described in 1, a groove is previously formed in an insulating film on a silicon substrate, and a Cu film having an electric resistance smaller than that of Al is deposited on the insulating film including the inside of the groove. Unnecessary Cu film on the outside is chemically and mechanically polished (Chemic
A so-called damascene process, in which a Cu wiring is formed inside a groove by polishing back by an al mechanical polishing (CMP) method, is being promoted.

In the above damascene process, if the width of the groove becomes narrower as the wiring width becomes finer, it becomes difficult to completely bury the Cu film inside the groove.
995 VMIC Proceedings ", pp. 308 to 314, a technique of reflowing a Cu film deposited by a sputtering method into a groove, and a technique disclosed in, for example, Press Journal Co., Ltd., November 20, 1997. As described in “Monthly Semiconductor World”, pp. 308 to 314, introduction of a technique of forming a Cu film by a CVD method or an electroplating method, which has better step coverage than the sputter-reflow method, is also in progress.

[0005]

In the conventional damascene process, the unnecessary Cu film remaining on the insulating film outside the groove is removed by CM even when the Cu film is formed by any of the above methods.
A step of polishing back by the P method is required. However, when the Cu film is polished by the CMP method, a part of Cu is eluted into the slurry, which may cause corrosion of the Cu wiring, resulting in an open defect or a short circuit. Such corrosion of the Cu wiring is caused by Cu connected to a pn junction (a source and a drain of a MOS transistor, a collector, a base, an emitter, and a diffusion resistance element of a bipolar transistor) formed on a silicon substrate.
It occurs characteristically in wiring. Although not as remarkable as the Cu film, another metal film (for example, a W film or an Al alloy film) is polished by a CMP method to form a wiring,
Corrosion may also occur when plugs are embedded in the connection holes.

FIG. 17A is a model diagram showing an electromotive force generation mechanism of a pn junction, FIG. 17B is a graph showing IV characteristics of the pn junction at the time of light irradiation and at the time of darkness, and FIG. FIG. 4 is a model diagram showing a corrosion generation mechanism of a Cu wiring.

As shown in FIG. 17A, when light is incident on the pn junction, an external voltage (up to 0.6 V) of + on the p-side and-on the n-side is generated due to the photovoltaic effect of silicon. As shown in (b), the IV characteristic of the pn junction shifts. Therefore, as shown in FIG. 18, when the Cu film is polished to form the Cu wiring, a short-circuit current flows between the two electrodes through the slurry diluting liquid attached to the wafer surface, and pn
C from the surface of the Cu wiring connected to the p-side (+ side) of the junction
The u + ions dissociate and cause wiring corrosion.

FIG. 19 is a graph showing the relationship between the slurry concentration (%) and the etching (elution) rate of Cu when a voltage is applied. As shown in the figure, when the slurry concentration is 100%, the elution rate of Cu is relatively small, but it can be seen that the elution rate rapidly increases when the slurry is diluted to some extent with water.

From the above, it can be said that when light is incident on the pn junction in a state where the slurry diluted with water is attached to the surface of the silicon wafer, the elution of Cu becomes remarkable, causing corrosion. Specifically, for example, when light is incident on the pn junction when slurry diluted with pure water is attached to the surface of the wafer, such as when the wafer is stored in a rinsing step after polishing or a post-cleaning step. Corrosion of the Cu wiring occurs.

The present inventor has investigated the conditions under which the corrosion of the Cu wiring is likely to occur, and as a result, the following has been found.
This will be described with reference to FIGS. 20 and 21. (1) Corrosion depends on the photocurrent value (Isc) but does not depend on the external voltage value (V) (where V> 0).

(2) The photocurrent value increases as the area of the pn junction increases, and particularly, the wiring and plug connected to the pn junction having a large area of about 100 μm 2 or more are likely to be corroded.

(3) The photocurrent value increases as the external resistance decreases. In other words, the resistance of the slurry diluent is usually much higher than the diffusion resistance of the pn junction, but when the distance between the electrodes is short and the liquid resistance is low, the photocurrent value increases and corrosion is accelerated.

Therefore, as a countermeasure for preventing corrosion of the Cu wiring, a CMP apparatus and a cleaning apparatus connected to the CMP apparatus must be installed in a dark room so that illumination light or the like does not hit the surface of the wafer. Can be considered. However, this countermeasure has a problem that the state of the wafer cannot be visually recognized during the operation, and is not a preferable countermeasure in view of a case where some trouble occurs in the apparatus during the operation.

An object of the present invention is to provide a technique capable of reliably preventing corrosion of a metal wiring or a metal plug formed by using a CMP method.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In the semiconductor integrated circuit device according to the present invention, a concave groove is formed in an insulating film on a main surface of a semiconductor substrate, and a film is formed inside the concave groove on the insulating film including the inside of the concave groove. A wiring or plug formed by polishing the formed metal film by a chemical mechanical polishing method is embedded, and an upper part of a pn junction formed on a main surface of the semiconductor substrate is
A light shielding layer made of the metal film is disposed so as to cover the pn junction.

A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) After forming an insulating film on the main surface of the semiconductor substrate, a first concave groove is formed in the insulating film in the wiring forming region or the connection hole forming region, and the first concave groove is formed on the main surface of the semiconductor substrate. Forming a second groove in the insulating film above the formed pn junction, and (b) forming a metal film on the insulating film including the inside of the first and second grooves. Forming a wiring or plug made of the metal film inside the first groove by polishing the metal film on the insulating film by a chemical mechanical polishing method; Forming a light-shielding layer made of the metal film therein.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.

FIG. 1 shows a CM according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a main part of a semiconductor substrate on which an OS-logic LSI is formed.

For example, an n-type well 2n and a p-type well 2p are formed on the main surface of a semiconductor substrate 1 made of p-type single crystal silicon.
Are formed. CMO is part of the p-type well 2p
An n-channel MISFET (Q
n) is formed, and a p-type semiconductor region 4 constituting the terminating resistance element (R) is formed in a part of the n-type well 2n. Although not shown, the field oxide film 3
Other regions of the n-type well 2n separated by
P-channel type MISF forming another part of MOS circuit
ET is formed.

The n-channel type MISFET (Qn) mainly includes a gate oxide film 5, a gate electrode 6, a source (n-type semiconductor region 7) and a drain (n-type semiconductor region 7). Each of the region 7) and the drain (n-type semiconductor region 7) has a first contact hole (connection hole) 9 formed in a silicon oxide film 8 covering the n-channel MISFET (Qn).
The wirings 11, 12, and 13 of the layer are electrically connected. Further, the p-type semiconductor region 4 forming the terminating resistance element (R) includes a source of the n-channel MISFET (Qn),
It has a larger area than the n-type semiconductor region 7 constituting the drain, and has a first end through a contact hole (connection hole) 10 formed in the silicon oxide film 8 covering the terminating resistance element (R) at both ends. The wirings 14 and 15 of the layer are electrically connected. The first-layer wirings 11 to 15 are made of, for example, a W film.

On the first wirings 11 to 15, a first interlayer insulating film 16 made of, for example, a silicon oxide film is formed.
Are formed, and the second-layer wirings 17 to 19 and the silicon oxide film 21 are formed thereon.
The second-layer wirings 17 to 19 are made of, for example, a Cu film,
It is electrically connected to the first-layer wirings 11 to 15 through through holes 22 to 25 formed in the interlayer insulating film 16. A plug 26 made of, for example, a W film is embedded in the through holes 22 to 25. The second-layer wirings 17 to 19 are formed by polishing a Cu film deposited on the silicon oxide film 21 by a CMP method. The plug 26 is formed by polishing a W film deposited on the interlayer insulating film 16 by a CMP method.

Above the p-type semiconductor region 4 constituting the terminating resistance element (R), a light shielding layer 20 made of, for example, a Cu film is formed. The light-shielding layer 20 is formed at the same time as the step of polishing the Cu film deposited on the silicon oxide film 21 by the CMP method to form the second-layer wirings 17 to 19. It has a large area that covers almost the entire area. By disposing the light-shielding layer 20 above the p-type semiconductor region 4, it is possible to prevent light from entering the p-type semiconductor region 4 in the step of forming the wirings 17 to 19 by polishing the Cu film by the CMP method. Therefore, it is possible to prevent the wirings 17 to 19 from being corroded due to a photocurrent generated when light enters the pn junction.

The region where the light-shielding layer 20 is disposed is not limited to the region above the p-type semiconductor region 4 constituting the terminating resistance element (R). That is, an n-channel MISFET
Source and drain (n-type semiconductor region 7) and p (not shown)
By arranging above the pn junction of various semiconductor elements such as the source and drain of a channel type MISFET or the emitter, base and collector of a bipolar transistor, it is possible to prevent corrosion of wiring connected to these pn junctions. .

In the case of a highly integrated LSI, the MIS
Since the area of the pn junction such as the source and drain of the FET and the emitter, base and collector of the bipolar transistor is extremely small, arranging the light-shielding layer 20 on the pn junction not only involves difficulty in wiring design but also In addition, the wiring capacity increases, which hinders high-speed operation. In addition, since the photovoltaic (photocurrent) value increases in proportion to the area of the pn junction, the generation of photovoltaic (photocurrent) is extremely small even when light enters the pn junction having such a small area. ,
There is little risk of wiring corrosion. Therefore, like the p-type semiconductor region 4 constituting the above-described terminating resistance element (R), the light shielding layer 2 is selectively formed only above the pn junction having a relatively large area.
Only 0 may be arranged.

The wiring corrosion is caused by the p-side of the pn junction (+
This occurs in the wiring connected to the side), and the smaller the wiring, the more severe the corrosion. That is, in the case of a wiring having a large area, even if the surface is eluted, the influence is small. Therefore, the pn junction p
When a fine pattern wiring is connected to the side (+ side), the light shielding layer 20 is selectively provided only above the pn junction.
May be simply arranged. The fine pattern means that the design rule of the wiring width is 0.3 μm, 0.5 μm, 1.0 μm, for example.
m, 0.3 μm × 0.3 to 0.6 μm = 0.09
0.18 μm ² , 0.5 μm × 0.5 to 1.0 μm = 0.25 to
0.50 μm ² , 1.0 μm × 1.0 to 2.0 μm = 1.0 to 2.0
This is a pattern of about μm ² .

Second layer wirings 17 to 19 and light shielding layer 2
A second interlayer insulating film 27 made of, for example, a silicon oxide film is formed on the upper part of the wiring layer 0, and a third layer wirings 28 to 30 and a silicon oxide film 31 are further formed on the second interlayer insulating film 27. ing. A passivation film 36 made of, for example, a stacked film of a silicon oxide film and silicon nitride is formed on the third layer wirings 28 to 30.

The wirings 28 to 30 of the third layer are made of, for example, Cu
It is made of a film and is connected to the second-layer wirings 17 to 19 through through holes 32 to 34 formed in the interlayer insulating film 27. A plug 26 made of, for example, a W film is embedded in the through holes 32 to 34. The third-layer wirings 28 to 30 are formed by polishing a Cu film deposited on the silicon oxide film 31 by CMP, and the plug 35 is formed by polishing a W film deposited on the interlayer insulating film 27 by CMP. It is formed by polishing with a method.

Next, an example of a method of manufacturing the CMOS-logic LSI will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 2, an n-type well 2n, a p-type well 2p and a field oxide film 3 are formed on the main surface of a semiconductor substrate 1 by well-known ion implantation and selective oxidation (LOCOS). , N-type well 2n and p-type well 2p are thermally oxidized to form gate oxide film 5.

Next, as shown in FIG. 3, the p-type well 2p
After the gate electrode 6 is formed on the gate oxide film 5, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type well 2 p on both sides of the gate electrode 6 to form a source and a drain (n).
By forming the type semiconductor region 7), an n-channel MISFET (Qn) is formed. A gate electrode 6 is formed on the gate oxide film 5 of the n-type well 2n in a region (not shown).
Is formed, the n-type wells 2 on both sides of the gate electrode 6 are formed.
By implanting a p-type impurity (for example, boron) into n to form a source and a drain (p-type semiconductor region), a p-channel MISFET is formed. Further, a low-concentration p-type impurity (for example, boron) is ion-implanted into the illustrated n-type well 2n to form the p-type semiconductor region 4, thereby forming the terminating resistance element (R). The gate electrode 6 is formed, for example, by depositing a polycrystalline silicon film and a W silicide film on the semiconductor substrate 1 by a CVD method, and then patterning these films by dry etching using a photoresist film as a mask.

Next, as shown in FIG. 4, after depositing a silicon oxide film 8 on the semiconductor substrate 1 by the CVD method, the silicon oxide film 8 is dry-etched using the photoresist film as a mask, so that the source, A contact hole 9 is formed above the drain (n-type semiconductor region 7), and a contact hole 10 is formed above both ends of the p-type semiconductor region 4.

Next, as shown in FIG. 5, after forming first-layer wirings 11 to 15 on the silicon oxide film 8, a silicon oxide film is formed on these wirings 11 to 15 by the CVD method. The first interlayer insulating film 16 is deposited to form through holes 22 to 25 in the interlayer insulating film 16 by dry etching using a photoresist film as a mask.
The first-layer wirings 11 to 15 are formed, for example, on the silicon oxide film 8 including the insides of the contact holes 9 and 10 by CVD.
After a W film is deposited by a method (or a sputtering method), the W film is formed by patterning the W film by dry etching using a photoresist film as a mask.

Next, as shown in FIG.
After a W film 40 is deposited on the upper part of the interlayer insulating film 16 including the insides 2 to 25 by the CVD method, and the W film 40 is polished by the CMP method, as shown in FIG. The plug 26 is formed inside.

Next, as shown in FIG.
After depositing a silicon oxide film 21 on top of the substrate by a CVD method,
The silicon oxide film 21 is dry-etched using the photoresist film as a mask, thereby forming the second-layer wiring 17.
The grooves 41 to 44 are formed in the region where the light shielding layer 20 is formed and the region where the light shielding layer 20 is formed.

Next, as shown in FIG.
A Cu film 45 is deposited on the silicon oxide film 21 including the inside by sputtering. When the concave grooves 41 to 44 have a large aspect ratio and it is difficult to sufficiently bury the Cu film 45 therein, after depositing the Cu film 45, the semiconductor substrate 1 is heat-treated to reflow the Cu film 45. Then, it may be poured into the concave grooves 41 to 44. Alternatively, the Cu film 45 may be formed by a CVD method or an electroplating method having better step coverage than the sputtering-reflow method.

Next, as shown in FIG. 10, the concave grooves 41 to 4 are formed by polishing the Cu film 45 by the CMP method.
4, the second-layer wirings 17 to 19 and the light-shielding layer 20 are formed.

FIG. 11 shows the plug 26 and the wiring 17 described above.
19 is a schematic view of a CMP apparatus used for forming the light shielding layer 20. As shown in the figure, the CMP apparatus has a housing 101 having an open top, and the upper end of a rotating shaft 102 rotatably attached to the housing 101 is rotationally driven by a motor 103. Polishing machine (platen)
104 is attached. A polishing pad 105 formed by uniformly attaching a synthetic resin having a large number of pores is attached to the surface of the polishing board 104.

The CMP apparatus has a wafer carrier 106 for holding the semiconductor substrate (wafer) 1. Drive shaft 10 with wafer carrier 106 attached
Numeral 7 is rotated integrally with a wafer carrier 106 by a motor (not shown), and is moved up and down above the polishing plate 104.

The semiconductor substrate (wafer) 1 is held by the wafer carrier 106 with its main surface, that is, the surface to be polished facing downward, by a vacuum suction mechanism (not shown) provided on the wafer carrier 106. At the lower end of the wafer carrier 106, a concave portion 1 for accommodating the semiconductor substrate (wafer) 1 is provided.
When the semiconductor substrate (wafer) 1 is accommodated in the concave portion 106a, the surface to be polished is substantially the same as or slightly protrudes from the lower end surface of the wafer carrier 106.

Above the polishing plate 104, a polishing pad 10
A slurry supply pipe 108 for supplying a slurry (S) is provided between the surface of the semiconductor substrate (wafer) 1 and the surface to be polished of the semiconductor substrate (wafer) 1. The surface to be polished of (wafer) 1 is chemically polished.

The CMP apparatus is provided with a polishing pad 10
5 is provided with a dresser 109 which is a tool for shaping (dressing) the surface. This dresser 109
It is attached to the lower end of a drive shaft 110 that moves up and down above the polishing plate 104 and is driven to rotate by a motor (not shown).

The dressing is performed after the polishing of some semiconductor substrates (wafers) 1 is completed or every time the polishing of one semiconductor substrate (wafer) 1 is completed.
Alternatively, dressing may be performed simultaneously with polishing. For example, when the semiconductor substrate (wafer) 1 is pressed against the polishing pad 105 by the wafer carrier 106 and is polished for a predetermined time, the wafer carrier 106 is retracted upward. Next, the dresser 109 moves downward and is pressed against the polishing pad 105, and after its surface is dressed for a predetermined time, the dresser 109 is retracted upward. Followed by another semiconductor substrate (wafer)
1 is attached to the wafer carrier 106, and the above-mentioned polishing step is repeated. After a predetermined number of semiconductor substrates (wafers) 1 have been polished in this manner, the polishing operation is terminated by stopping the rotation of the polishing plate 104.

Next, as shown in FIG. 12, a silicon oxide film is deposited on the second-layer wirings 17 to 19 and the light-shielding layer 20 by a CVD method to form a second-layer interlayer insulating film 27. Then, through holes 32 to 34 are formed in the interlayer insulating film 27 by dry etching using a photoresist film as a mask, and then plugs 35 made of a W film are embedded in the through holes 32 to 34. Subsequently, after depositing a silicon oxide film 31 on the interlayer insulating film 27 by the CVD method,
Third-layer wirings 28 to 30 made of a film are formed. The plug 35 and the third-layer wirings 28 to 30 are formed in the same manner as the plug 26 and the second-layer wirings 17 to 19, respectively.

It should be noted that among the wirings 28 to 30 of the third layer,
If there is a wiring connected to the p-side (+ side) of the pn junction, when forming the wirings 28 to 30, a light-shielding layer may be formed simultaneously on the pn junction. However, this is not necessary when the upper layer of the pn junction is already covered by the first or second layer wiring or another light shielding layer.

Thereafter, a silicon oxide film and silicon nitride are deposited on the third wirings 28 to 30 by the CVD method to form a passivation film 36, whereby the CMOS logic LSI shown in FIG. Complete.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

In the above embodiment, the case where the upper wiring and the lower wiring are connected via the plug embedded in the through hole has been described. However, in the present invention, the wiring is embedded in the concave groove and the through hole at the same time. The present invention can be applied to a case where a Cu wiring is formed by a so-called dual damascene process.

For example, when the second-layer wirings 17 to 19 are formed by a dual damascene process, first, as shown in FIG. 13, through-holes are formed in the interlayer insulating film 16 by dry etching using two photomasks. Hall 22 ~
25 and concave grooves 41 to 44 are sequentially formed. Next, FIG.
As shown in FIG.
After depositing a Cu film 45 on the upper portion of the silicon oxide film 21 including the insides of the layers 44 to 44 by using a sputtering method or the like, the Cu film 45 is polished by using the CMP apparatus, as shown in FIG. 17 to 19 and the light shielding layer 20 are simultaneously formed.

In the above embodiment, the pn junction (p
The light-shielding layer 20 is disposed above the mold semiconductor region 4), for example, as shown in FIG. 16A (plan view) and FIG.
As shown in (a) a cross-sectional view along the line BB, p
The light-shielding layer 51 may be arranged above the mold semiconductor region (pn junction) 50, and a metal plug 54 may be buried in a connection hole 53 formed in the insulating film 52 around the light-shielding layer 51 and used as a light-shielding layer. In such a case, the light incident on the p-type semiconductor region 50 not only from directly above but also obliquely from above is simultaneously shielded, so that corrosion of the wiring connected to the p-type semiconductor region 50 is more reliably prevented. can do. The connection holes 53 are formed simultaneously, for example, in a step of forming a connection hole connecting the semiconductor element and the wiring, and the metal plugs 54 are formed simultaneously in a step of embedding the metal plug in the connection hole connecting the semiconductor element and the wiring. I just need.

In the above embodiment, the case where the present invention is applied to a CMOS-logic LSI having three-layer wiring has been described. However, the present invention is not limited to this. INDUSTRIAL APPLICABILITY The present invention can be widely applied to various LSIs in which a metal wiring or a metal plug is formed by using a CMP method.

[0054]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, corrosion of metal wirings and metal plugs formed by using the CMP method can be reliably prevented, so that the reliability and manufacturing yield of a high-speed LSI using Cu wiring are particularly improved. Can be done.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate showing a CMOS-logic LSI according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a CMOS-logic LSI according to an embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS-logic LSI according to the embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS-logic LSI according to the embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS-logic LSI according to the embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS-logic LSI according to the embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS-logic LSI according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS-logic LSI according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS-logic LSI according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS-logic LSI according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS-logic LSI according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS-logic LSI according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a CMOS-logic LSI according to another embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a CMOS-logic LSI according to another embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a CMOS-logic LSI according to another embodiment of the present invention;

16A is a plan view of a principal part of a semiconductor substrate showing another embodiment of the present invention, and FIG. 16B is a cross-sectional view taken along line BB of FIG.

FIG. 17A is a model diagram showing a mechanism of generating an electromotive force of a pn junction, and FIG.
5 is a graph showing V characteristics.

FIG. 18 is a model diagram showing a corrosion generation mechanism of a Cu wiring.

FIG. 19 shows slurry concentration (%) and Cu
4 is a graph showing a relationship between the etching (elution) rate and the etching speed.

FIG. 20 is a graph showing the correlation between pn junction area and open circuit voltage and corrosion.

FIG. 21 is a graph showing a correlation between a pn junction area, a short-circuit current, and corrosion.

[Description of Symbols] 1 semiconductor substrate (wafer) 2n n-type well 2pn-type well 3 field oxide film 4 p-type semiconductor region 5 gate oxide film 6 gate electrode 7 n-type semiconductor region (source, drain) 8 silicon oxide film 9 Reference Signs List 10 contact hole (connection hole) 11-15 first-layer wiring 16 first-layer interlayer insulating film 17-19 second-layer wiring 20 light-shielding layer 21 silicon oxide film 22-25 through hole 26 plug 27 Second layer interlayer insulating film 28-30 Third layer wiring 31 Silicon oxide film 32-34 Through hole 35 Plug 36 Passivation film 40 W film 41-44 Groove 45 Cu film 50 p-type semiconductor region 51 light shielding layer 52 Insulating film 53 Connection hole 54 Metal plug 101 Housing 102 Rotating shaft 103 Motor 104 Polishing machine (platen) 1 5 the polishing pad 106 the wafer carrier 106a recess 107 drive shaft 108 slurry supply pipe 109 dresser 110 drive shaft S slurry Qn n-channel type MISFET R terminator resistor

Claims (8)

[Claims] A concave groove is formed in an insulating film on a main surface of a semiconductor substrate, and a metal film formed on the insulating film including the inside of the concave groove is formed inside the concave groove by a chemical mechanical method. A semiconductor integrated circuit device in which wirings or plugs formed by polishing by a polishing method are embedded, wherein a light-shielding layer made of the metal film is provided above a pn junction formed on a main surface of the semiconductor substrate. A semiconductor integrated circuit device arranged to cover the pn junction. 2. The semiconductor integrated circuit device according to claim 1, wherein a light shielding layer formed of a metal plug embedded in a connection hole formed in an insulating film surrounds the pn junction around the pn junction. A semiconductor integrated circuit device which is arranged to surround. 3. The semiconductor integrated circuit device according to claim 1, wherein said metal film contains at least copper. 4. The semiconductor integrated circuit device according to claim 1, wherein the light-shielding layer is provided only above a pn junction having a relatively large area among pn junctions formed on a main surface of the semiconductor substrate. A semiconductor integrated circuit device which is selectively disposed. 5. The semiconductor integrated circuit device according to claim 4, wherein said pn junction includes at least a pn junction forming a terminating resistance element. 6. The semiconductor integrated circuit device according to claim 1, wherein said wiring or plug is electrically connected to a p-type semiconductor region forming a part of said pn junction. Semiconductor integrated circuit device. 7. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming an insulating film on a main surface of a semiconductor substrate on which a pn junction is formed, and then forming a wiring forming region or Forming a first groove in the insulating film in the connection hole formation region, and forming a second groove in the insulating film above the pn junction; (b) the first and second grooves After forming a metal film on the insulating film including the inside of the first film, the metal film on the insulating film is polished by a chemical mechanical polishing method, whereby the first film is formed.
Forming a wiring or a plug made of the metal film inside the concave groove, and forming a light shielding layer made of the metal film inside the second concave groove. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein said metal film contains at least copper.