JPH11284179A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor device which does not cause depletion of a gate electrode and does not impair the characteristics of a gate insulating film, and a method for manufacturing the same. SOLUTION: A thin polycrystalline silicon film 22 is formed on the entire surface of a gate insulating film 17 by a CVD method. After forming a protective film on the polycrystalline silicon film 22 by a CVD method,
The protective film and the polycrystalline silicon film 22 are each processed into an electrode pattern shape. Thereafter, the gate side wall (side wall) 1 is formed on the side surface of the polycrystalline silicon film 22 and the protective film.
The n ⁺ -type source region 14 and the n ⁺ -type drain region 15 are formed in a self-aligned manner by ion implantation of an n-type impurity, for example, arsenic, using the gate sidewall 18, the protective film and the element isolation film 13 as a mask. Form. After removing the protective film, a cobalt film 26 is formed on the entire surface of the silicon substrate 11 by, for example, a sputtering method, and heat treatment (RTA) is performed. Thereby, the entire polycrystalline silicon film 22 is silicided, and this becomes a gate electrode. At the same time, a silicide layer is formed on the n ⁺ type source region 14 and the n ⁺ type drain region 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS (Metal Ox
The present invention relates to a semiconductor device having a transistor of the (ide Semiconductor) type and a method of manufacturing the same.
-Aligned Siliside) and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, LSIs (Large Scale Integrated
In the field of semiconductor manufacturing such as circuits, miniaturization of elements is progressing according to the scaling law, and higher integration and higher performance (higher speed and lower power consumption) are performed. However, with the miniaturization of this element, a MOS field effect transistor (FET) has been developed.
(Hereinafter referred to as MOSFET), various new problems have become apparent. One of the problems is MOSFE
Depletion of the T gate.

As a gate electrode of a MOSFET, a Si gate made of conductive polycrystalline silicon is used instead of a conventional Al gate made of aluminum (Al). In the MOSFET using this Si gate, C
After forming a Si gate electrode by VD (Chemical Vapor Deposition), the source / drain regions can be formed in a self-aligned manner by ion implantation using the Si gate electrode directly as a mask. Thereby, in the Si gate MOSFET, the Al gate MOSFE
Since the gate electrode and a part of the source / drain region do not overlap with each other as in T, the parasitic capacitance is reduced, and the speed can be made higher than that of the Al gate MOSFET.

In this Si gate MOSFET, the resistance of the Si gate is reduced by adding an impurity into the polycrystalline silicon film by a method such as ion implantation. Here, if the ion implantation amount of the impurity is too large, there is a possibility that the impurity ions may penetrate toward the substrate side, so that the implantation amount has to be limited. However, if the implantation amount is small, the added impurity is not sufficiently diffused to the vicinity of the gate insulating film of the polycrystalline silicon film, and the impurity concentration distribution becomes non-uniform. That is, the vicinity of the gate insulating film remains in a semiconductor state. In this state, when a predetermined voltage is applied to the gate electrode during operation of the Si gate MOSFET, the Si
The gate is depleted to generate capacitance (depletion layer capacitance). The ratio of the depletion layer capacitance occupied by the gate depletion increases relatively as the miniaturization progresses and the thickness of the gate insulating film decreases. As a result, the current driving capability of the MOSFET is reduced, and this is a major problem today.

Therefore, as one of the countermeasures, an MO having a metal gate structure having a gate electrode made of a high melting point metal has been proposed.
SFETs have been proposed. In this metal gate, since the entire gate electrode is made of metal, the problem of gate depletion does not occur as in the case of the Si gate.
There is an advantage that the resistance can be reduced as compared with the gate. As a method of manufacturing a MOSFET having a metal gate structure, a titanium nitride (TiN) film and a tungsten (W) film are stacked in this order on a gate oxide film, and then patterned into an electrode shape. A method of performing ion implantation of impurities into a substrate and further forming a source region and a drain region by, for example, RTA (Rapid Thermal Annealing) at 1000 ° C. (IE
DM97, p. 825-828) and after forming the source and drain regions in the silicon substrate and forming the polycrystalline silicon film in the gate electrode portion, the polycrystalline silicon film is processed into an electrode shape, and the polycrystalline silicon film is formed on the polycrystalline silicon film. A method of forming a metal film made of titanium nitride and tungsten by a CVD method has been reported (IEDM97, pp. 821 to 824).
).

[0006]

However, any of the above-mentioned MOSFETs having the metal gate structure has a problem that the characteristics of the gate insulating film are deteriorated when the gate is formed. That is, in the method of forming a source electrode and a drain region by ion implantation and RTA after forming a gate electrode made of a metal (titanium nitride and tungsten), interdiffusion between the gate electrode and the gate insulating film during RTA is performed. Occurs, so that the characteristics of the gate insulating film deteriorate.

On the other hand, in the method of forming a source region and a drain region, etching a polycrystalline silicon film, and further forming a gate electrode of a metal film on the polycrystalline silicon film, a method of forming a gate electrode Since the heat treatment is performed at a relatively low temperature of 450 ° C., there is no possibility that interdiffusion occurs between the gate electrode and the gate insulating film. However, this method has a problem in that the gate insulating film is exposed when the polycrystalline silicon film is etched and damages the gate insulating film, so that the characteristics of the gate insulating film deteriorate. Furthermore,
This method has a problem in that the process is longer than in the above-described method.

[0008] As another problem associated with miniaturization,
As the impurity regions of the source and the drain become shallower and their sheet resistance becomes higher, there is a problem that the contact resistance between the aluminum wiring and the impurity region increases.
In order to suppress such an increase in contact resistance, a MOSFET having a salicide structure has been put to practical use. This salicide structure is formed by forming a metal such as a compound of titanium (Ti) and silicon (Si) (silicide) on an impurity region, and can be formed in a self-aligned manner without using a mask process. It can be formed in a narrow area, and is a technique suitable for miniaturization. Therefore, even when the above-described gate electrode is formed, not only is it possible to suppress gate depletion, but also a method that can be adapted to such a process of forming silicide in a source region and a drain region is desired.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device which does not cause depletion of a gate electrode and does not impair the characteristics of a gate insulating film, and a method of manufacturing the same. To provide.

The present invention not only suppresses gate depletion but also adapts to a salicide technique for forming a source region and a drain region, thereby realizing low resistance of the source region and the drain region, and further, the gate electrode. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same.

[0011]

A semiconductor device according to the present invention comprises: a substrate formed of a silicon material and having a pair of impurity regions serving as a source and a drain formed thereon;
The semiconductor device includes a gate insulating film formed in a region between the impurity regions on the substrate, and a gate electrode formed entirely on the gate insulating film and made of metal silicide.

A method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a gate insulating film on a substrate made of a silicon material; forming a silicon film on the gate insulating film;
Depositing a refractory metal on the silicon film and performing a heat treatment to silicide the entire silicon film to form a gate electrode.

Another method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate insulating film on a substrate made of a silicon material, a step of stacking a silicon film and a protective film on the gate insulating film in this order, Processing the protective film and the silicon film into a gate electrode pattern shape; forming a gate sidewall made of an insulating material so as to cover the processed silicon film and the side surface of the protective film; and selectively removing the protective film Then, after exposing the surface of the silicon film, a step of depositing a high melting point metal on the silicon film and performing a heat treatment to silicide the entire silicon film to form a gate electrode.

Still another method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate insulating film on a substrate made of a silicon material, and a step of laminating a silicon film and a protective film on the gate insulating film in this order. Processing the protection film and the silicon film into a gate electrode pattern shape, forming a gate sidewall made of an insulating material so as to cover the processed silicon film and the protection film wall surface, and forming the gate sidewall and the protection film. A step of forming a pair of impurity regions serving as a source and a drain by injecting impurities into the substrate as a mask, and selectively removing the protective film to expose the surface of the silicon film, and then covering the entire surface of the substrate. A high melting point metal is deposited, and then the entire silicon film is silicided by heat treatment to form a gate electrode, and selectively on each impurity region. It is intended to include a step of forming a Risaido layer.

In the semiconductor device according to the present invention, since the entire gate electrode is formed of metal silicide, a voltage can be applied to the gate electrode without causing gate depletion.

In the method for manufacturing a semiconductor device according to the present invention,
After the refractory metal is deposited on the silicon film on the gate insulating film, heat treatment is performed to silicide the entire silicon film.

In another method of manufacturing a semiconductor device according to the present invention, after a gate sidewall is formed so as to cover the side surfaces of a stacked silicon film and a protective film, the silicon film is selectively removed by removing the protective film. Is exposed. Subsequently, the gate electrode is formed by silicidation of the entire silicon film by the heat treatment, and a gate sidewall higher than the gate electrode is formed.

In still another method of manufacturing a semiconductor device according to the present invention, after forming an impurity region serving as a source and a drain, a high melting point metal is deposited over the entire surface of the substrate and heat treatment is performed. As a result, a silicide layer is formed on the impurity region, and at the same time, a gate electrode entirely silicided is formed.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the configuration of an n-channel MOSFET 10 according to one embodiment of the present invention. This MOSFET 10 has a p-type MOSFET on the surface of an n-type silicon substrate 11.
It is formed in the mold well region 12 and is insulated from adjacent elements by a thick element isolation film 13 made of a silicon oxide film (SiO ₂ ).

The MOSFET 10 has a p-type well region 12
Region between the n ⁺ -type source region 14, n ⁺ -type drain region 15 and the p-type n ⁺ -type source region 14 in the well region 12 and the n ⁺ -type drain region 15, which is formed on the surface of the (channel region) Gate electrode 16 provided opposite to
It consists of.

The gate electrode 16 is formed on a gate insulating film 17 formed of, for example, a silicon oxide film having a thickness of 3.5 nm. In the present embodiment, the gate electrode 16 is entirely formed of a high melting point metal silicide, and has a thickness of 10 to 150 nm, preferably 15 to 1 nm.
The value is in the range of 00 nm. The gate electrode 16 made of the refractory metal silicide is formed, for example, by CVD (Chemical Vapor Deposition) as described later.
) Method, a high-melting-point metal is deposited on this silicon film, and then heat-treated. As refractory metal silicide,
Cobalt silicide (CoSi ₂ ) using cobalt (Co) as the high melting point metal is preferable, but titanium (Ti), nickel (Ni), tungsten (W), platinum (Pt), molybdenum (Mo) is also used as the high melting point metal. ) May be used.

On both side surfaces of the gate electrode 16 on the gate insulating film 17, gate side walls (sidewall films) 18 made of, for example, silicon dioxide (SiO ₂ ) are formed.
The n ⁺ -type source region 14 and the n ⁺ -type drain region 15 are formed in a self-aligned manner using the gate side walls 18. The height of the gate side wall 18 is, for example, 3
It is 50 nm. That is, the gate side wall 18 has a so-called offset structure in which the upper end is at a position higher than the upper end of the gate electrode 16. This is because, when the gate electrode 16 becomes thinner, when the gate side wall 18 is formed in accordance with the height of the gate electrode 16, misalignment may occur when a contact portion for the source and drain regions is formed in a subsequent process. This is to prevent this and to provide a process margin.

[0024] On the surface of the p-type well region 12, impurity concentration than the n ⁺ -type source region 14 and n ⁺ -type drain region 15 low concentration between the n ⁺ -type source region 14 and n ⁺ -type drain region 15 And shallow n ^- type LDD (Lightly Doped
Drain) regions 19 and 20 are formed adjacent to the n ⁺ -type source region 14 and the n ⁺ -type drain region 15, respectively. The impurity concentration of n ⁻ -type LDD regions 19 and 20 is n
^{The +} type source region 14 and the n ⁺ type drain region 15 are, for example, about 1 × 10 ¹⁵ atoms / cm ³ , respectively, whereas they are about 1 × 10 ¹⁴ atoms / cm ³ . The electric field is reduced to suppress the hot carrier effect.

On the n ⁺ type source region 14 and the n ⁺ type drain region 15, low resistance silicide layers 21a and 21b made of the same high melting point metal silicide (cobalt silicide in this case) as the gate electrode 16 are formed. ing.

In this MOSFET 10, the gate electrode 1
Since the entire 6 is formed of a metal (refractory metal silicide), without the gate depletion occurs as the gate electrode including polycrystalline silicon, yet also the n ⁺ -type source region in the gate electrode 16 The resistance can be reduced as in the case of the n ⁺ -type drain region 14 and the n ⁺ -type drain region 15. In this MOSFET 10, the gate side wall 18
Is higher than the upper end surface of the gate electrode 16, and the width at the lower end of the gate side wall 18 is relatively large accordingly, and the contact portions to the n ⁺ -type source region 14 and the n ⁺ -type drain region 15 are formed. No misalignment occurs during the formation of.

Next, a method of manufacturing the MOSFET 10 will be described with reference to FIGS. 2 to 5 and FIG.

First, as shown in FIG. 2A, for example, a LOCOS (Local Oxidatio) is formed on an n-type silicon substrate 11.
A thick device isolation film 13 made of a silicon oxide film is selectively formed by an n of Silicon method. Next, p is applied to a region of the silicon substrate 11 surrounded by the element isolation film 13.
A p-type well region 12 is formed by selectively ion-implanting a type impurity such as boron (B).
Oxidation is performed on the surface of the gate insulating film 17 by, for example, a 3.5-nm-thick silicon oxide film.
To form

Subsequently, CVD (Chemical V) using monosilane gas (SiH ₄ ) is applied to the entire surface of the gate insulating film 17.
A polycrystalline silicon film 22 having a thickness of, for example, 30 nm is formed by an apor deposition method. At this time, the flow rate of SiH ₄ is, eg, 400 sccm, and the ambient conditions are a temperature, eg, 625 ° C., and a pressure, eg, 20 Pa. The thickness of the polycrystalline silicon film 22 is 30 nm as an example here, but may be in the range of 10 nm to 100 nm. This polycrystalline silicon film 22 is silicided as described later to become a gate electrode. Polycrystalline silicon film 2
The silicidation of 2 can be performed as follows if there is no time and temperature limitation.
Although it can be made thicker than 00 nm, the upper limit is preferably set to 100 nm in consideration of the temperature limitation generally applied to the MOSFET. On the other hand, when silicidation is performed in a later step, the lower limit of the polycrystalline silicon film 22 is desirably 10 nm in order to obtain a stable and low-resistance film.

Next, as shown in FIG. 2B, a protective film 23 made of, for example, silicon nitride (SiN) having a thickness of 200 nm is formed on the polycrystalline silicon film 22 by, for example, a CVD method at a temperature of 400 ° C. I do. This protective film 23 prevents impurity ions from penetrating to the silicon substrate 11 side when ions are implanted into the polycrystalline silicon film 22 in a step described later, and also forms the gate side wall 18 in a gate electrode forming step. It is used for forming a height higher than 16.

Subsequently, as shown in FIG. 2C, a photoresist film 24 having an electrode pattern is selectively formed on the protective film 23.
Is applied and formed.

Next, as shown in FIG. 3A, RIE (Reactive) is performed using the photoresist film 24 as a mask.
Anisotropic etching by Ion Etching is performed, and the protective film 23 and the polycrystalline silicon film 22 are each processed into an electrode pattern shape.

Next, as shown in FIG. 3B, using the element isolation film 13 and the protective film 23 as a mask, for example, under the conditions of an energy of 10 keV and an injection amount of 8 × 10 ¹⁴ ions / cm ^2, an n-type impurity is formed. For example, arsenic (As) is ion-implanted (LDD-implanted) to form n ⁻ -type LDD regions 19 and 20. Subsequently, for example, 76
After depositing 150 nm of silicon dioxide (not shown) by a plasma CVD method at a temperature of 0 ° C., the titanium nitride film is subjected to anisotropic etching (etch back), and the side surfaces of the polycrystalline silicon film 22 and the protective film 23 are formed. A wide gate side wall (side wall) 18 is formed at the portion. In this embodiment, silicon nitride is exemplified as a material forming the protection film 23 and silicon dioxide is illustrated as a material forming the gate side wall 18. In addition, PSG (Phospho-Silicate Glass) is used as the protection film 23. An insulating material such as a silicon nitride film can be appropriately used for the gate side wall 18 such as a film, a silicon dioxide film or an organic film. However, in this combination, in order to form the gate side wall 18 having a desired shape, the gate side wall 18 needs to be formed of a material having a higher etching rate than the material forming the protective film 23.

After the formation of the gate side wall 18, FIG.
As shown in (c), ion implantation of an n-type impurity, for example, arsenic is performed using the gate side wall 18, the protective film 23 and the element isolation film 13 as a mask, and the n ⁻ -type LDD regions 19 and 2 are formed.
A high-concentration n ⁺ -type source region 14 and an n ⁺ -type drain region 15 having a junction depth deeper than 0 are formed in a self-aligned manner. In the ion implantation, for example, the energy is 50 keV,
The ion implantation is performed at a dose of 3 × 10 ¹⁵ ions / cm ² . Subsequently, a heat treatment (RTA) at 1000 ° C. for 10 seconds, for example, is performed to activate the impurities implanted into the n ⁺ type source region 14 and the n ⁺ type drain region 15. At this time, since the polycrystalline silicon film 22 is covered with the protective film 23, the impurity ions do not penetrate to the silicon substrate 11 side.

Subsequently, as shown in FIG. 4A, after a photoresist film 25 is formed on the entire surface of the silicon substrate 11, this photoresist film 25 is etched so that only the surface of the protective film 23 is exposed. (Etch back). Next, wet etching using, for example, a hydrofluoric acid-based etchant is performed using the photoresist film 25 as a mask. As a result, as shown in FIG. 4B, the protective film 23 is selectively removed from above the polycrystalline silicon film 22.

Next, as shown in FIG. 5, portions of the gate insulating film 17 above the n ⁺ -type source region 14 and the n ⁺ -type drain region 15 are wet-etched using a hydrofluoric acid-based etchant. To remove selectively.
Next, a cobalt film 26 having a thickness of 20 nm is formed on the entire surface of the silicon substrate 11 by, for example, a sputtering method.
Here, as described above, titanium other than cobalt,
A refractory metal film such as nickel may be formed. After forming the cobalt film 26, for example,
A heat treatment (RTA) for 0 seconds is performed, and the polycrystalline silicon film 2 is formed.
2, n ⁺ type source region 14 and n ⁺ type drain region 1
The silicon in 5 is reacted with cobalt. As a result, as shown in FIG. 1, the polycrystalline silicon film 22 is entirely silicided, and the gate electrode 16 made of cobalt silicide having low resistance and no thin wire effect is formed. At the same time, silicide layers 21a and 21b are formed on n ⁺ -type source region 14 and n ⁺ -type drain region 15. After silicidation, unreacted cobalt on the upper surfaces of the element isolation film 13, the gate sidewalls 18 and the like is selectively removed by immersion in an etchant such as sulfuric acid-hydrogen peroxide.

Thereafter, although not shown, an interlayer insulating film made of a silicon oxide film is formed by, for example, a CVD method, and subsequently, the dry film is opposed to the n ⁺ -type source region 14 and the n ⁺ -type drain region 15 of the interlayer insulating film. In the regions, contact holes (contact holes) reaching the silicide layers 21a and 21b are formed. A selectively thin titanium nitride film and titanium (Ti) are selectively formed on the inner wall and the bottom of the connection hole (that is, the surfaces of the silicide layers 21a and 21b).
A laminated film (TiN / Ti) made of a film is formed, and then the connection holes are filled with a tungsten layer. Subsequently, a titanium film is formed on the silicon substrate 11 including the connection holes, and an aluminum-based alloy such as aluminum (Al) containing silicon is formed on the titanium film and patterned to be electrically connected to the tungsten layer. Is formed.

As described above, the MOSFE according to the present embodiment
In the method of manufacturing T10, cobalt (high melting point metal) is deposited on a thin polycrystalline silicon film 22 having a thickness of about 30 nm, and silicon reacts with cobalt to form the gate electrode 16.
Is formed, a metal gate entirely made of a low-resistance high-melting-point metal silicide can be obtained in a self-aligned manner. Therefore, the problem of depletion unlike the conventional polycrystalline silicon gate does not occur.

In this embodiment, since the silicidation of the gate electrode 16 can be performed simultaneously with the silicidation of the n ⁺ -type source region 14 and the n ⁺ -type drain region 15, the manufacturing process of the MOSFET is simplified. Be transformed into

Further, in this embodiment, the heat treatment (RT
Since the silicidation is performed after the n ⁺ -type source region 14 and the n ⁺ -type drain region 15 are formed by A), the silicide does not diffuse into the gate insulating film 17 by RTA. Therefore, the gate electrode 1
The stability of the interface characteristics between the gate insulating film 6 and the gate insulating film 17 can be improved, and the characteristics of the gate insulating film 17 do not deteriorate.

In this embodiment, ion implantation for forming n ⁺ -type source region 14 and n ⁺ -type drain region 15 is performed with protective film 23 provided on polycrystalline silicon film 22. Therefore, during silicon implantation, impurities pass through the polycrystalline silicon film 22 and pass through the silicon substrate 11.
Can be prevented.

In addition, in the present embodiment, the gate sidewall 18 is formed so as to cover the side surface of the laminated film of the polycrystalline silicon film 22 and the protective film 23, and then the protective film 23 is removed. The upper end of the side wall 18 has a structure located at a position higher than the upper surface of the polycrystalline silicon film 22 (that is, the gate electrode 16). Therefore, the n ⁺ type source region 1
It is possible to increase the process margin when forming the contact portion for the 4 and n ⁺ type drain regions 15 in a self-aligned manner.

In short, in the present embodiment, the gate electrode 16 having low resistance and not being depleted can be formed in a self-aligned manner, and at the same time, the n ⁺ -type source region 14 and the n ⁺ -type drain can be formed. The salicide structure of the region 15 can be realized, and further, the contact portions to the n ⁺ -type source region 14 and the n ⁺ -type drain region 15 can be formed in a self-aligned manner.

As described above, the present invention has been described with reference to the embodiments. However, the present invention is not limited to these embodiments, and can be variously modified. For example, in the above embodiments, the silicon film for forming the gate electrode is described as a polycrystalline silicon film. However, the gate electrode may be formed by silicidizing an amorphous silicon film.

In the above embodiment, an n-channel MOSFET has been described as an example of a semiconductor device.
Needless to say, the present invention can be applied to an FET having a complementary metal oxide semiconductor (structure) structure.

[0046]

As described above, according to the semiconductor device of any one of the first to sixth aspects, the gate electrode is entirely made of metal silicide, so that gate depletion is prevented. In addition, the resistance can be reduced, and the current driving capability is significantly improved.

According to the method of manufacturing a semiconductor device according to any one of claims 7 to 13, a refractory metal is deposited on a thin silicon film, and the entire silicon film is silicided by heat treatment to form a gate. Since the electrodes are formed, it is possible to manufacture a gate electrode which is completely metallized and does not become depleted without attacking the gate insulating film underlying the gate electrode.

In particular, according to the method of manufacturing a semiconductor device according to any one of claims 8 to 10, after forming the gate side wall so as to cover the side surface of the laminated structure of the silicon film and the protection film, the protection film is formed. Is removed to expose the silicon film, so that the gate side wall is formed higher than the gate electrode. Therefore, the process margin when forming the contact portion for the source and drain impurity regions is expanded.

Further, according to the method of manufacturing a semiconductor device according to the twelfth aspect or the thirteenth aspect, a high-melting-point metal is deposited on the entire surface of the substrate and then subjected to a heat treatment, so that the gate electrode and the soft Since a silicide layer on a pair of impurity regions serving as a source and a drain is formed, a gate electrode entirely made of metal silicide and a source region and a drain region having a salicide structure are simultaneously formed. Is simplified. Further, since the gate electrode made of the refractory metal silicide is formed after forming the impurity regions to be the source and the drain, no heat treatment is required after the formation of the gate electrode. Therefore,
This has the effect that deterioration of the insulating film characteristics can be prevented.

[Brief description of the drawings]

FIG. 1 shows an n-channel MOS according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a configuration of an FET.

FIG. 2 is a cross-sectional view illustrating each manufacturing process of the MOSFET illustrated in FIG.

FIG. 3 is a sectional view illustrating each manufacturing step following FIG. 2;

FIG. 4 is a sectional view illustrating each manufacturing step following FIG. 3;

FIG. 5 is a sectional view illustrating each manufacturing step following FIG. 4;

[Explanation of symbols]

11 ... silicon substrate, 12 ... p-type well region, 13 ... isolation layer, 14 ... n ⁺ -type source region, 15 ... n ⁺ -type drain region, 16 ... gate electrode, 17 ... gate insulating film, 1
8 ... gate side wall, 19, 20 ... n ^- type LDD region, 21
a, 21b: silicide layer, 22: polycrystalline silicon film,
23 ... Protective film, 24, 25 ... Photoresist film, 26 ...
Cobalt film

Claims (13)

[Claims] A substrate formed of a silicon material and having a pair of impurity regions serving as a source and a drain formed thereon; a gate insulating film formed in a region on the substrate corresponding to the region between the impurity regions; A gate electrode formed entirely on the gate insulating film and made of metal silicide. 2. The gate electrode is formed by forming a silicon film on the gate insulating film, forming a refractory metal film on the silicon film, and then silicidizing the entire silicon film by heat treatment. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 3. The semiconductor device according to claim 1, wherein a gate side wall made of an insulating material is provided on a side surface of said gate electrode. 4. The semiconductor device according to claim 3, wherein said gate side wall has an upper end located at a position higher than a surface of said gate electrode. 5. The gate electrode has a thickness of 10 to 150 n.
2. The semiconductor device according to claim 1, wherein the range is m. 6. The semiconductor device according to claim 1, wherein a metal silicide layer is formed on each of the pair of impurity regions.
13. The semiconductor device according to claim 1. 7. A step of forming a gate insulating film on a substrate made of a silicon material, and after forming a silicon film on the gate insulating film, depositing a refractory metal on the silicon film and performing a heat treatment. And forming a gate electrode by silicidizing the entire silicon film. 8. A step of forming a gate insulating film on a substrate made of a silicon material, a step of stacking a silicon film and a protective film on the gate insulating film in this order, and forming the protective film and the silicon film on a gate electrode. A step of forming a gate sidewall made of an insulating material so as to cover side surfaces of the processed silicon film and the protective film; and selectively removing the protective film to form a silicon film. Forming a gate electrode by exposing the surface, depositing a refractory metal on the silicon film and performing heat treatment to silicide the entire silicon film to form a gate electrode. 9. The method according to claim 8, wherein the gate side wall is formed of a material having a higher etching rate than a material forming the protective film. 10. The method of manufacturing a semiconductor device according to claim 9, wherein said protection film is formed of silicon nitride, and said gate side wall is formed of silicon dioxide. 11. The silicon film has a thickness of 10 to 100.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the value is within a range of nm. 12. A step of forming a gate insulating film on a substrate made of a silicon material, and after laminating a silicon film and a protective film on the gate insulating film in this order, forming the protective film and the silicon film on a gate electrode. Forming a gate sidewall made of an insulating material so as to cover a wall surface of the processed silicon film and the protective film; and forming an impurity on a substrate using the gate sidewall and the protective film as a mask. Forming a pair of impurity regions serving as a source and a drain by injecting a metal. After selectively removing the protective film to expose the surface of the silicon film, depositing a refractory metal over the entire surface of the substrate Then, the entire silicon film is silicided by heat treatment to form a gate electrode, and a silicide layer is selectively formed on each impurity region. The method of manufacturing a semiconductor device which comprises the step of forming. 13. The method of manufacturing a semiconductor device according to claim 12, wherein cobalt is used as the high melting point metal, and the silicide layer on the gate electrode and each impurity region is made of cobalt silicide.