JPH11275066A - Signal transmission system - Google Patents

Abstract

(57) [Summary] [Problem] To transmit a large amount of data, it is necessary to use a plurality of signal lines, but in this case, a difference (skew) in a delay amount of each signal line becomes a problem. However, the distance and transmission speed at which signals can be transmitted correctly are limited. A signal transmission system for transmitting and receiving a signal using a plurality of signal lines, wherein a signal delay generated in a process of transmitting and receiving the signal is adjusted according to a skew of each of the signal lines. It is configured to include a timing adjusting unit that adjusts a timing of receiving a signal in the receiving circuit for each signal line to an optimum timing for each signal line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a signal transmission system, and more particularly to an LSI (Large Scale Integration Circuit).
The present invention relates to a signal transmission system for transmitting and receiving a signal at high speed during t) or between devices. In recent years, with the high-speed operation of LSIs, there has been a demand for providing a signal transmission system capable of transmitting large-capacity signals at high speed as signal transmission between LSIs or between devices constituted by a plurality of LSIs.

[0002]

2. Description of the Related Art In recent years, the performance of components constituting a computer or other information processing equipment has been greatly improved, and accordingly, between LSIs (LSI chips) or between a plurality of LSIs.
It has become necessary to transmit and receive signals at high speed between the devices configured as described above.

FIG. 1 is a block circuit diagram schematically showing an example of a conventional signal transmission system. In FIG. 1, reference numeral 401 denotes a transmission side driving circuit (buffer) for clock clk, 411 to 41n denote transmission side driving circuits for data DD1 to DDn, 402 denotes a wiring for clock (clock signal line), and 421 to 42n. Is a data wiring (data signal line), 403 is a clock receiving-side drive circuit, 431 to
43n is a receiving-side drive circuit for data, and 441 to 441
44n indicates a data fetch circuit (input latch).

[0004] As shown in FIG. 1, a conventional signal transmission system for a large data amount includes a plurality of signal lines 402,
Signals were sent using 421 to 42n. That is, for example, the clock clk is transmitted to the buffer 40 on the transmission side.
1 and a buffer (clock buffer) 403 on the receiving side via the clock signal line 402 and supplied to the clock terminals (capture timing control terminals) of the input latches 441 to 44n.

The data (signals) DD1 to DDn are:
Buffers 431 on the receiving side via buffers 411-41n on the transmitting side and data signal lines 421-42n, respectively.
43n, and the clock buffer 40
3 are supplied to input latches 441 to 44n whose capture timing is controlled by a clock (strobe signal) from the input latch 441.

[0006]

In the conventional signal transmission system shown in FIG. 1, a plurality of signal lines 40 are provided.
2, 421 to 42n and buffers 401, 411 to 4
1n; 403, 431 to 43n are used, so that the amount of delay differs in the signal transmitted through each signal line. That is, each signal line (data signal lines 421 to 42)
For each n), the optimum fetch timing of the signal (data) transmitted via the signal line is different.
The difference (skew) of the delay amount for each signal line is
For example, as the frequency of the clock clk becomes higher, high-speed operation (high-speed transmission) becomes a serious problem as it proceeds.

Therefore, as in the conventional signal transmission system shown in FIG. 1, a common strobe signal (clock clk) is supplied to input latches 441 to 44n provided on each of the signal lines 421 to 42n to generate a signal (clock clk). ), It is impossible to cope with the skew of each signal line. That is, the input latches 441 to 4 of each signal line
4n, when the difference between the timings of capturing the optimal signals becomes extremely large, the common timing (clock cl)
In k), it becomes impossible to correctly capture (receive) all signals, and as a result, the distance and transmission speed at which signals can be transmitted accurately are limited. Alternatively, in order to increase the transmission distance of a signal or to increase the transmission speed (increase the bit rate), an expensive cable with a specially adjusted skew must be used, but this is only costly. However, the improvement of the transmission distance and the transmission speed cannot be expected to be large, and it cannot be said that this is a fundamental solution.

The present invention has been made in view of the above-mentioned problems of the conventional signal transmission system, and has as its object to provide a signal transmission system capable of performing high-speed and error-free signal transmission without being affected by skew of each signal line. I do.

[0009]

According to the present invention, there is provided a signal transmission system for transmitting and receiving a signal using a plurality of signal lines, wherein a signal delay generated in a process of transmitting and receiving the signal is reduced. According to the skew of each signal line,
There is provided a signal transmission system comprising timing adjustment means for adjusting the timing of receiving a signal in each signal line in a receiving circuit to an optimum timing for each signal line.

[0010] According to the signal transmission system of the present invention, the timing adjustment means adjusts the amount of signal delay generated in the process of signal transmission and reception in accordance with the skew of each signal line.
The timing of receiving a signal in the receiving circuit for each signal line is adjusted to an optimum timing for each signal line. As described above, according to the signal transmission system of the present invention, high-speed, error-free signal transmission can be performed without being affected by skew.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing in detail an embodiment of a signal transmission system according to the present invention, FIG.
This will be described with reference to FIGS. FIG. 2 is a block circuit diagram schematically showing the principle configuration of the signal transmission system according to the present invention, and FIGS. 3 and 4 are timing charts for explaining an example of the operation in the signal transmission system of FIG.

In FIG. 2, reference numerals 511 to 51n denote transmitting side drive circuits (drivers) for data DD1 to DDn, 521 to 52n denote data wirings (data signal lines), and 531 to 53n denote timing adjustment circuits (optimum circuits). (Timing defining means) and 541 to 54n indicate data fetch circuits (input latches). As shown in FIG. 2, the signal transmission system of the present invention transmits signals using a plurality of signal lines (data signal lines) 521 to 52n, and outputs data (signals) DD1 to DDn.
Are supplied to timing adjustment circuits (timing adjustment means) 531 to 53n on the reception side via drivers 511 to 51n on the transmission side and data signal lines 521 to 52n, respectively.

Each of the timing adjustment circuits 531 to 53
n is also supplied with a clock clk, and each signal line 5
In accordance with the skew of each of 21 to 52n, the timing of fetching a signal in each of the input latches (receiving circuits) 541 to 54n is adjusted to an optimum timing. Here, the timing adjustment circuits 531 to 53n include the data DD1 to DD
Strobe signals (clocks) clk1 to clkn are output near the center of the period (data window) in which n is determined.

That is, as shown in FIG. 3, PT5 of the signal lines 521 to 52n of the signal transmission system shown in FIG.
At the positions shown in FIG.
Has a skew due to each signal line or the like. Therefore, for example, in the case of the clock clk (the strobe signal at a timing substantially at the center of the period during which the data DD1 is determined) optimum for taking in the data DD1 transmitted via the signal line 521, the transmission via the signal line 52n is performed. The data DDn cannot be fetched because of the timing of the transition area of the data DDn.

Therefore, as shown in FIG. 4, in the signal transmission system of the present invention, each timing adjustment circuit 5
Each of the input latches 541 to 54n adjusts the timing of fetching a signal in each of the input latches 541 to 54n to an optimum timing in accordance with the skew of each of the signal lines 521 to 52n. That is, the strobe signal (clock) clk1 whose timing has been adjusted by the timing adjustment circuit 531 in consideration of the skew of the signal line 521 and the like is supplied to the input latch 541 for capturing the data DD1, and the data DD2 is captured. For the input latch 542, the timing adjustment circuit 532 controls the signal line 52.
The strobe signal clk2 whose timing has been adjusted in consideration of the skew due to 2 or the like is supplied.
For the input latch 54n that captures Dn, the strobe signal cl whose timing is adjusted by the timing adjustment circuit 53n in consideration of the skew due to the signal line 52n and the like
kn is supplied. Here, the rising timing of the strobe signal clk1 is based on the data DD1.
Is substantially at the center of the period in which the data DD2 is determined, and the rising timing of the strobe signal clk2 is substantially at the center of the period in which the data DD2 is determined, and the rising timing of the strobe signal clkn is the data DDn. Is almost in the middle of the period in which is determined.

As a result, high-speed and error-free signal transmission can be performed without being affected by the skew of each signal line. Note that, in the signal transmission system of the present invention, the timing adjustment circuits 531 to 53n are not limited to those that adjust the timing of the strobe signals clk1 to clkn supplied to the respective timing adjustment circuits 531 to 53n on the reception side. For example, data D
The timing of D1 to DDn may be adjusted on the transmission side.

Hereinafter, embodiments of the signal transmission system according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 5 is a block circuit diagram schematically showing a first embodiment of the signal transmission system of the present invention, and FIG. 6 is a timing chart for explaining an example of the operation in the signal transmission system of FIG.

In FIG. 5, reference numeral 530 is a timing adjustment circuit (optimal timing defining means), 5301 is a phase comparison circuit, 5302 and 5303 are variable delay circuits, 54
0 is a data capture circuit (input latch), and 52
0 indicates a signal line (data signal line). Here, the variable delay circuits 5302 and 5303 have the same configuration, and the same delay amount is given by the output of the phase comparison circuit 5301. The data DD, the signal line 520, the timing adjustment circuit 530, and the input latch 540 in the first embodiment correspond to, for example, the data DD1, the signal line 521, the timing adjustment circuit 531 and the input latch 541 in FIG. These configurations are provided for each data (DD1 to DDn).

The signal transmission system according to the first embodiment transmits a received signal (data) DD and a clock clk to a receiving side.
A timing adjustment circuit 530 for adjusting the relative timing relationship with (clk ′) is provided, and the input latch 540 takes in the data DD at the optimal timing (the timing substantially at the center of the period during which the data DD is determined) (latch). )
It is supposed to do. That is, as shown in FIG. 5, the timing adjustment circuit 530 outputs the first clock c
a first variable delay circuit 5302 for delaying lk,
Variable delay circuit 5303 that delays the clock clk ′ of data DD, data DD and second variable delay circuit 5
A phase comparison circuit 5301 is provided for performing a phase comparison with the second clock clk ′ supplied via the switch 303. Here, the second clock clk ′ is the first clock clk ′.
The signals are 180 degrees out of phase with respect to k. In the second embodiment, two-phase clocks clk and clk 'whose phases are different by 180 degrees are used.

Here, as shown in FIG. 6, the phase comparison circuit 5301 uses the data DD and the second clock clk '.
Are compared with each other to control the delay amount of the second variable delay circuit 5303, whereby the transition timing of the data DD and the rising timing of the second clock clk 'are made to coincide. Further, the phase comparison circuit 5301 also controls the delay of the first variable delay circuit 5302 in the same manner as the second variable delay circuit 5303, and performs the first clock (strobe signal) clk on the first clock. 2 variable delay circuits 5
The same delay amount as 303 is given. As a result, the rising timing of the first clock clk having a phase difference of 180 degrees with respect to the second clock clk 'is substantially the center of the period (data window) during which the data DD is determined, and the error rate is increased. Small data reception becomes possible.

The timing adjustment circuit 530 is provided for each of the signal lines (521 to 52n). As a result, it is possible to perform accurate data reception for all data lines. Note that the variable delay circuits 5302, 53
As 03, various configurations can be applied in addition to a configuration in which a multi-stage inverter as shown in FIG. 5 is used and the number of stages of the inverter is changed to vary the delay amount.

FIG. 7 is a block circuit diagram schematically showing a modification of the signal transmission system shown in FIG. 5, and FIG. 8 is a timing chart for explaining an example of the operation in the signal transmission system of FIG. Comparison of FIGS. 5 and 7, and
As is clear from FIG. 8, the modified example (timing adjustment circuit 530 ′) of the first embodiment is a case where the duty ratio of the clock (clk0) is about 50%, that is, the high-level period of the clock clk0 This is applicable when the low-level periods have almost the same ratio, and the second period in FIG.
Using the clock clk0 as the clock clk 'of
The first clock clk and the first variable delay circuit 5302 in FIG. 5 can be eliminated.

As shown in FIG. 7 and FIG.
In the modification of the embodiment, the delay amount of the variable delay circuit 5303 is controlled by the variable delay circuit 5303 so that the timing of the data DD and the clock clk0 match, and a signal (/ cl) obtained by inverting the clock clk0 by the inverter 5304 is used.
k0) controls the data fetch timing of the input latch 540.

That is, the rising timing of the clock clk0 is matched with the transition timing of the data DD by the phase comparison circuit 5301 and the variable delay circuit 5303. At this time, the rising timing of the strobe signal (clock) / clk0 obtained by inverting the clock clk0 is almost at the center of the period in which the data DD is determined, so that the data by the input latch 540 using this signal / clk0 is used. Import Thus, according to the present modification, the duty ratio is approximately 50%, ie, 1%.
Only by using the phase clock, it is possible to perform high-speed and error-free signal transmission without being affected by skew.

FIG. 9 is a block circuit diagram schematically showing a second embodiment of the signal transmission system of the present invention. In FIG. 9, reference numeral 550 denotes a timing adjustment circuit, 5501 denotes a tapped delay circuit, and 5502 denotes a termination resistor. As shown in FIG. 9, the signal transmission system of the second embodiment uses the clock clk as it is as the strobe signal of the input latch 540, and inserts a tapped delay circuit 5501 for the data DD, and Adjustments are made. Here, the tapped delay circuit 5501 is, for example, a tapped transmission line formed by a thin film circuit or a wiring on a printed board, and a plurality of sets of a capacitor CC, a switch SW, and a resistor RR are provided for the transmission line. By turning on an arbitrary switch SW, the delay amount of the data DD is variably controlled. The delay circuit 55 with tap
01 is, for example, 1 ns at a transmission distance of about 5 cm.
c. The one with the maximum delay of the order is applicable. Needless to say, a variable delay circuit that can delay an analog signal (data DD) can be used as the delay circuit 5501 with taps, as long as it is a variable delay circuit.

Although the signal transmission system of the second embodiment requires an external delay line (delay circuit 5501 with taps), it has high stability against temperature and the like and delay control with excellent frequency characteristics. Because it is possible, it is possible to realize higher-speed signal transmission. FIG. 10 is a block circuit diagram schematically showing a third embodiment of the signal transmission system of the present invention. 10, reference numerals 561 to 56
n is a timing adjustment circuit (optimal timing defining means),
601 is a data capture circuit (output latch), and
Reference numeral 5602 denotes a variable delay circuit.

As shown in FIG. 10, the signal transmission system according to the third embodiment adjusts the timing by making the transmission timing variable on the signal transmission side. ) An output latch 5601 is provided at a stage preceding to 511 to 51n.
A signal obtained by delaying the clock clk by the variable delay circuit 5602 is used as the strobe signal. That is, the timing of the drivers 511 to 51n is adjusted by the output of the variable delay circuit 5602 that variably controls the delay amount.

That is, for example, the timing adjustment circuit 5
61 controls the driver 511 to transmit the data DD1 at a timing at which the clock on the receiving side becomes the optimum point of the data DD1 (at a timing substantially at the center of the period during which the data DD is determined). It is supposed to. In the signal transmission system according to the third embodiment, the transmission timing of the data (DD1 to DDn) is adjusted by the timing adjustment circuits (561 to 56n) on the transmission side. This adjustment is performed, for example, when the power is turned on. , Using a communication protocol. That is, for example, when the power is turned on, a predetermined signal (data) is applied to each of the signal lines 521 to 52n by each of the timing adjustment circuits 561 to 56n.
The transmission can be configured such that the timing is sequentially changed according to n and the timing at which the reception of data is optimal on the receiving side is determined by feedback to each of the timing adjustment circuits 561 to 56n.

The signal transmission system of the third embodiment can simplify the circuit configuration on the receiving side, and is preferable, for example, when it is strongly desired to reduce the cost of the device on the receiving side. is there. FIG. 11 is a block circuit diagram schematically showing a fourth embodiment of the signal transmission system of the present invention. In FIG. 11, reference numeral 5310 denotes a timing adjustment circuit, and 5311 denotes a phase interpolator.

As shown in FIG. 11, in the signal transmission system of the fourth embodiment, the timing adjustment circuit 530
Is a phase interpolator 5311 for generating a new clock having an intermediate phase from a plurality of clocks having different phases.
It is provided with. That is, four-phase clocks φ0 to φ3 are supplied to the phase interpolator 5311, an intermediate phase is generated based on these four-phase clocks, and a strobe signal (clk00) is supplied to the input buffer 540. Has become. The phase interpolator 5311 is connected to each signal line 520 (521 to 52n).
It is needless to say that it is provided for each of the input latches 540 (541 to 54n) that take in the data DD (DD1 to DDn) transmitted via the.

FIG. 12 is a circuit diagram showing an example of the phase interpolator in the signal transmission system of FIG. As shown in FIG. 12, the phase interpolator 5311
Is input by changing the bias current (Tail Current) of the two differential amplifier stages 5312 and 5313.
By adding weights to the phase clocks φ0 to φ3 and further passing the signals S1 and S2 from the two differential amplifier stages 5312 and 5313 to the comparator 5314,
An intermediate phase output (strobe signal clk00) between the phases of these two signals S1 and S2 is obtained. Here, the weighting of the input clocks φ0 to φ3 in each of the differential amplifier stages 5312 and 5313 is performed by, for example, a plurality of sets of control transistors including two nMOS transistors connected in series, and one of the transistors (5315). Control codes (C01, C0)
, C0n; C11, C12,..., C1n), and the gates of the other transistors (5316) are commonly connected so that a control voltage (Vcn) is applied. The advantage of using such a phase interpolator 5311 is that the timing of the output signal (strobe signal clk00) can be digitally adjusted with a resolution finer than that of the delay unit for one stage, so that highly accurate timing adjustment is possible. Become.

FIG. 13 shows a fifth embodiment of the signal transmission system according to the present invention.
FIG. 3 is a block circuit diagram schematically showing an embodiment. In FIG. 13, reference numeral 570 denotes a retiming circuit,
573 is a latch circuit, 574 is a selector, 575 is a shift register, 576 is a variable delay circuit, and 577 is a delay control circuit. Here, the fifth embodiment is
This is applied when a variable delay circuit 576 is inserted in a clock (strobe signal) for driving the input latch 540 on the receiving side. Note that the variable delay circuit 576
The delay control circuit 577 corresponds to, for example, the variable delay circuit 5302 and the phase comparison circuit 5301 in the first embodiment shown in FIG.

For example, in the signal transmission system of the first embodiment described above, the data DD is latched at the optimal timing by inserting the variable delay circuit 576 (5302) into the clock of the input latch 540. Although the signal obtained after passing through the input latch 540 has a digitized level, the timing of the data change is different for each signal line (data line) 520 reflecting the skew of the cable. .

Therefore, in the signal transmission system of the fifth embodiment, a retiming circuit 570 is provided after the input latch 540, and the data is latched again so that all data changes at the same timing. The shift register 575 adjusts a delay of one bit or more between data. As shown in FIG. 13, the retiming circuit 570 includes latch circuits 571 to 573 and a selector 574, and two-stage latch circuits 571 and 572 connected in series by the selector 574.
And the output of the latch circuit 573 are selected. Here, strobe signal RTB is supplied to latch circuit 571, and latch circuits 572 and 5
73 is supplied with a strobe signal RTA. Note that the strobe signal RTA is a signal having a phase difference of 180 degrees with respect to the strobe signal RTB.

FIGS. 14 and 15 are timing charts for explaining an example of the operation in the signal transmission system of FIG. As shown in FIG. 14, the PT51 of FIG.
At the output positions of the input latches 540 (541 to 54n) shown in FIG. 7, each data (signal) DD1 to DDn is fetched at the optimal timing, but each data DD
The timings at which 1 to DDn change vary depending on the skew caused by signal lines and the like.

However, no matter what position each data changes, at least the timing (rising timing) of one of two signals (strobe signal) RTA and RTB having a phase difference of 180 degrees. Data can be captured for one of the signals. That is, for example, one strobe signal RT
The rising timing of A is the data DD2 and DDn
, The rising timing of the other strobe signal RTB having a phase difference of 180 degrees from this signal RTA always exists in a period in which the data DD2 and DDn are determined, and the data is taken in. Can be.

In the retiming circuit 570 of the fifth embodiment, the output of the input latch 540 is captured by the latch circuit 571 supplied with the strobe signal RTB and the latch circuit 573 supplied with the strobe signal RTA. At least one of them can take in correct data. Further, by providing a latch circuit 572 at a stage subsequent to the latch circuit 571, the strobe signal RT
The outputs of the latch circuits 571 (572) and 573 can be supplied to the selector 574 at the timing according to A. Here, the selector 574 includes a delay control circuit 577.
Of the latch circuit 572 and the output of the latch circuit 573 are determined.

As a result, as shown in FIG.
At the output position of the selector 574 indicated by No. 3 PT52, the data DD1 to DDn change (retimed) at the same timing. However, there is a possibility that a delay of one bit or more exists between these data DD1 to DDn. That is, as shown in FIG. 15, for example, data DD1 is data DD2
, And the data DDn may be delayed by 2 bits from the data DD2. Therefore, in the signal transmission system of the fifth embodiment,
A shift register 575 is provided after the selector 574,
Data with the latest timing (for example, data DDn)
The output timing of all data is adjusted (skew is performed).

FIG. 16 shows a sixth embodiment of the signal transmission system of the present invention.
FIG. 17 is a block circuit diagram schematically showing an embodiment, and is a timing chart for explaining an example of the operation in the signal transmission system of FIGS. 17 and 18; FIG. In FIG. 16, reference numeral 580 denotes a retiming circuit, and 581 to 58
4 is a latch circuit, 585 and 586 are variable delay circuits,
540a and 540b indicate input latches. As shown in FIG. 16, the signal transmission system according to the sixth embodiment includes two input latches 54 that interleave the input latch 540 in the fifth embodiment.
0a and 540b. That is, as shown in FIG. 17, two clocks (strobe signals) aa and bb having phases different by 180 degrees are supplied to input latches 540a and 540b via variable delay circuits 585 and 586, respectively, and two input latches are provided. Data is alternately taken in at 540a and 540b. Here, the frequency of the strobe signals aa and bb is, for example, twice the frequency of the signals RTA and RTB in the fifth embodiment described above, and
, DD (m
-2), DD (m-1), DD (m), DD (m + 1), DD (m + 2),...) Are alternately fetched by the input latches 540a and 540b. Therefore, input latches 540a and 54
0b means that it is only necessary to operate at half the actual data rate (the rate of the transmitted signal). In addition,
The above-described interleave operation is not limited to double,
Weight or more.

The retiming circuit 580 includes two serially connected latch circuits 581 and 582 for receiving the output of one input latch 540a, and the other input latch 540.
b, and two-stage latch circuits 583 and 584 connected in series for receiving the output of
1, 582, and 584, and a strobe signal RC to the latch circuit 583.
TD is supplied.

As shown in FIG. 18, strobe signals RTC and RTD are signals whose phases are different from each other by 180 degrees. These signals are used as strobe signals and output from latch circuits 581, 582, and 584 as signal lines. 52
Data DD (..., DD (m−2), DD (m
-1), DD (m), DD (m + 1), DD (m + 2),...).

As described above, in the signal transmission system of the sixth embodiment, the input latch (540
Since the circuit operation after a and 540b) can be operated at half the transmission rate of the signal line, it is suitable for high-speed signal transmission. Also, the retiming circuit 580
In this case, there is also an advantage that circuit design can be facilitated because a sufficient time can be provided for the latch operation.

FIG. 19 shows the seventh embodiment of the signal transmission system of the present invention.
FIG. 2 is a block diagram schematically showing an embodiment, wherein a so-called PRD (Partial Resp.
onseDetection) type latch (differential PRD receiver)
Is used. In FIG. 19, reference numeral 52
0a and 520b are complementary signals (data) DD, /
Signal lines 590a and 590b for transmitting DD indicate PRD amplifiers that perform an interleaving operation. In the seventh embodiment, two signal lines 520a and 520b are provided for one data DD, and are transmitted as complementary data DD and / DD. Also, in each of the other embodiments, it goes without saying that signal transmission may be applied in either single or differential (complementary).

As shown in FIG. 19, the receiver circuit (input latch) according to the seventh embodiment uses complementary data D
D, / DD are supplied, and controlled by control signals φ10 and φ20 to perform a first interleaving operation.
It comprises amplifiers 590a and 590b. Here, the first and second PRD amplifiers 590a, 590
The output signal b is processed through, for example, a serial-parallel conversion circuit or the like in order to lower the operating frequency of the subsequent stage.

FIG. 20 is a circuit diagram showing an example of a PRD amplifier in the signal transmission system of FIG. 20, reference numeral 591 denotes a PRD function part, 592 denotes a differential amplifying part having a precharge function, and 593 and 594 denote a waveform shaping differential amplifier and an inverter. As shown in FIG. 20, the PRD function part 591 includes four capacitors C10a, C10b, C10
20a, C20b and four transfer gates (switch means) 5911, 5912, 5913, 5914
The connection of each capacitor is controlled by control signals φ10 (/ φ10) and φ20 (/ φ20), and the intersymbol interference component estimation operation and signal determination operation shown in FIGS. 22 and 23 are alternately performed. It has become.

Here, when the circuit shown in FIG. 20 is used as a differential PRD receiver, C20 = 1 / 3.multidot.C20 between the capacitance C10 of the capacitors C10a and C10b and the capacitance C20 of the capacitors C20a and C20b. C
It is necessary to make ten relationships hold. Or,
When used as an auto-zero receiver without being used as a PRD receiver, C10 = C20 may be set.

The differential amplification section 592 performs differential amplification of an input signal to determine data. The differential amplification section 592 further includes transfer gates 5921 and 5922, and estimates an intersymbol interference component. A precharge operation is also performed during the operation period. Differential amplifier 5
93 and an inverter 594 are for amplifying the output level of the differential amplifying part 592 and outputting a signal whose waveform is shaped. Here, in the circuit of FIG. 20, a complementary transfer gate is used as a switch element, but any other element having a switch function may be used. For example, only an NMOS transistor or a PM transistor may be used.
Only the OS transfer gate may be used. Further, the differential amplification portion 592 is configured as an NMOS gate receiver, but whether to use an NMOS receiver or a PMOS receiver depends on technology or the like, and an optimum one can be selected. .

FIG. 21 is a diagram for explaining timing signals (control signals φ10, φ20) used in the signal transmission system of FIG. 19, and FIGS. 22 and 23 show an example of the operation in the signal transmission system of FIG. It is a figure for explaining. As shown in FIGS. 22 and 23, the receiver circuit of the seventh embodiment shown in FIG. 19 has one PRD amplifier (the first PRD amplifier 59) at a certain timing.
0a), the intersymbol interference component is estimated, and the other P
Data determination is performed by the RD amplifier (second PRD amplifier 590b), and at the next timing, data determination is performed by one PRD amplifier (first PRD amplifier 590a) and the other PRD amplifier (second PRD amplifier 590a). PR of 2
An interleave operation such as estimation of an intersymbol interference component is performed by the D amplifier 590b).

Here, in the PRD amplifier performing the operation of estimating the intersymbol interference component, the PRD amplifier is also precharged at the same time, and the transfer gate 59 is used.
21 and 5922 set the input level to a predetermined potential (precharge potential Vpr). Note that this precharge time is performed behind the interleave data reading, and does not affect the data transfer cycle.

According to the signal transmission system of the seventh embodiment, the component of the intersymbol interference included in the input signal (data DD, / DD) caused by the primary response of the signal transmission system is removed. , And stable reception not affected by the DC drift is possible. Also, as described above, for example,
Even in an auto-zero receiver in which the relationship between the capacitance C10 of the capacitors C10a and C10b and the capacitance C20 of the capacitors C20a and C20b is C10 = C20, common-mode noise and the like can be removed, and large common-mode noise resistance can be obtained. .

FIG. 24 shows an eighth embodiment of the signal transmission system of the present invention.
FIG. 3 is a block circuit diagram schematically showing an embodiment. In FIG. 24, reference numeral 501 denotes a transmitting side driving circuit (clock driver) for the clock clk, 502 denotes a clock wiring, 503 denotes a clock receiver, and 611 to 61.
n indicates a variable delay circuit (clock timing adjustment circuit).

As shown in FIG. 24, in the signal transmission system according to the eighth embodiment, on the receiving side, the transmitted clock clk is timed by variable delay circuits 611-61n provided in the input latches 541-54n. Adjustment is made so that the data fetch timing of each of the input latches 541 to 54n is optimized. Here, the clock clk is transmitted by the transmitting side together with the data DD1 to DDn (always transmitted as special data that continuously changes to “0, 1, 0, 1,...”). In the case of clk, even if there is a jitter in the clock generation circuit on the transmission side, only a common jitter is generated. Therefore, in the signal transmission system according to the eighth embodiment, the jitter has no adverse effect on the data latched using the clock clk.

FIG. 25 shows a ninth embodiment of the signal transmission system of the present invention.
FIG. 3 is a block circuit diagram schematically showing an embodiment. In FIG. 25, reference numerals 602 and 621 denote latch circuits and 603.
Denotes a charge pump circuit, 604, 641, and 651 denote variable delay circuits, and 661 denotes a delay amount storage circuit. Here, the output of the latch circuit 602 is supplied to the charge pump circuit 603 via a two-stage inverter.

As shown in FIG. 25, in the signal transmission system of the ninth embodiment, similarly to the eighth embodiment, the clock clk is supplied to the data DD1 (DD1 to DD1).
The transmission is performed from the transmission side in the same manner as in n). This clock clk is latched by an input latch (latch) 602 similar to other data reception latches. In this latch 602, a strobe signal for taking in the clock clk is an internal strobe signal via a variable delay circuit 604. The clock clki is used. That is, what operates the latch 602 is a clock obtained by passing the receiving-side reference clock (internal clock clki) through the variable delay stage (variable delay circuit 604).

In the above, if the output of the input latch 602 is "0", the delay is increased (down: DN) and "1"
Then, if a signal of delay decrease (up: UP) is issued to give a delay to the internal clock clki, the clock clk
Can be locked to the rising edge of the internal clock clki. The delay is controlled by the charge pump circuit 6 using the UP / DN signal.
03 is operated, and the delay control signal DCS from the charge pump circuit 603 is supplied to the variable delay circuit 604. Also,
The delay control signal DCS is supplied to the variable delay circuit 641 and the clock timing of the input latch 621 for the other data line is similarly variably controlled, whereby the jitter component simultaneously added to the clock clk and the data DD1 can be reduced. It can be removed in the same way as in the example, without affecting the output. The signal transmission system according to the ninth embodiment includes a clock c in addition to the advantages of the eighth embodiment.
Since it is possible to remove noise on lk and receive the clock clk and the data DD1 (DD1 to DDn) using exactly the same latches 602 and 621,
There is an advantage that it is not necessary to devise a method of matching the phase shift in the clock receiving system with the phase in the data receiving system.

FIG. 26 is a block circuit diagram schematically showing a modification of the signal transmission system of FIG. FIG. 25 and FIG.
As is clear from the comparison with No. 6, in this modified example,
The variable delay circuit (641) for delaying the internal clock clki provided for each data DD1 (DD1 to DDn) is removed, and the output of the variable delay circuit 604 supplied as a strobe signal of the clock latch 602 is output to each data D1.
D1 is supplied to the variable delay circuit 651.

FIG. 27 shows a first example of the signal transmission system of the present invention.
FIG. 9 is a block circuit diagram schematically showing a zeroth embodiment, which is applicable to coding in which a clock component is guaranteed to be present in a data sequence, for example, 8B / 10B. Here, in FIG. 27, reference numerals 671 to 673 indicate latch circuits. As shown in FIG. 27, the signal transmission system of the tenth embodiment
For example, a signal in which data and a clock are coded by 8B / 10B or the like is supplied to three latches 671, 67.
2,673. That is, the strobe signal (internal clock) φ02 is supplied to the latches 671 and 672, and the strobe signal (internal clock) φ01 is supplied to the latch 673. Here, strobe signals φ01 and φ02 are
The signal is 180 degrees out of phase.

FIG. 28 is a timing chart for explaining an example of the operation in the signal transmission system of FIG. 27. FIG. 29 is a diagram showing the relationship between the output of each latch circuit and the state of the internal clock in the signal transmission system of FIG. It is. FIG.
As shown in FIG. 8, the strobe signal φ01 and the strobe signal 02 are 180 degrees out of phase with each other. For example, the rising timing of the strobe signal φ01 is a transition region (for example, a signal coded by 8B / 10B) of data. In the transient region (DT), the rising timing of the strobe signal φ02 is at the center of the period in which data is determined. Here, the latch 671
And 672 are supplied with the strobe signal φ02. For example, the currently received data DB becomes the output of the latch 671, and the data DA immediately before the data DB becomes the output of the latch 672. That is,
Latch 6 captured by strobe signal φ01
73 is a data transient area (data window boundary) DT, this strobe signal φ0
The strobe signal φ which is 180 degrees out of phase with respect to 1.
02, the data can be correctly output by the latch 671 that has been fetched.

FIG. 29 shows the output of latch 671 (current data DB) and the output of latch 672 (data D immediately before).
A), the output of the latch 673 (data DT in the transient area) and the internal clock (strobe signal φ).
01, φ02). That is, D
A, DT, DB are "0, 0, 1" or "1, 1, 0"
In the case (1), the internal clocks (φ01, φ02) are advanced (fast), and for example, the internal clocks (φ01, φ02) are delayed by the signal DN. DA,
When DT and DB are “0, 1, 1” or “1, 0, 0”, the internal clock (φ01, φ02) is delayed (slow). For example, the internal clock (φ01, φ02) is generated by the signal UP. (φ01, φ02). Here, the signal U
The adjustment of the internal clock by P and DN can be performed using, for example, a charge pump circuit and a variable delay circuit, or other known circuits.

In the signal transmission system of the tenth embodiment, a special period (calibration mode) is provided to adjust the latch timing of normal data. For example, 8B / 10B or the like is provided. During data reception (data transmission mode) if it is guaranteed that there is a clock component in the data sequence by performing coding
It is also possible to always perform adjustment work.

FIG. 30 shows a first example of the signal transmission system of the present invention.
FIG. 4 is a timing chart for explaining one embodiment. Book first
For example, the signal transmission system according to the first embodiment has a structure similar to that of the eighth embodiment shown in FIG.
(A sequence of 0, 1, 0, 1,...), And the receiving side synchronizes the clock clk with the phase adjustment data DDP.
For example, the delay amount of the variable delay circuit is controlled so that the rising and falling timings of the clock clk coincide with the boundaries of the data window. FIG. 30 shows DDR
(Double Data Rate), that is, an example in which data is taken in at both rising and falling timings of the clock clk. In each embodiment of the signal transmission system according to the present invention, D
It goes without saying that data can be captured at both the rising and falling timings of the clock by applying DR.

After synchronizing the clock clk with the phase adjustment data DDP, the actual data DD (DD1 to DD1)
DDn), the actual data DD is 180 degrees out of phase with respect to the phase adjustment data DDP. Therefore, the rising and falling timings of the clock clk synchronized with the phase adjustment data DDP are set at the center of the data window (data Is determined at the center of the period in which is determined).

As described above, the signal transmission system according to the eleventh embodiment does not need to provide a circuit for shifting the phase of the clock by 180 degrees on the receiving side, and can simplify the receiving circuit. Power consumption can be reduced. FIGS. 31 and 32 are block circuit diagrams showing a twelfth embodiment of the signal transmission system of the present invention. FIG.
32 and FIG. 32, reference numeral 680 is a DLL (Delay
Locked Loop) circuit, 681 is a latch section for clock clk, 682 is a control signal generation circuit, 683 is an up / down counter (UDC), 684 is a phase interpolator (PIP), and 685 is a clock generation circuit (CL).
KGE). Reference numerals 6811 to 68
1n is a latch section for data DD1 to DDn,
684n is a phase interpolator (PIP), 6861
To 686n are addition circuits, 6871 to 687n are initial value setting circuits for the respective data lines (521 to 52n),
688n is a retiming circuit;
9n indicates a deskew and serial-parallel conversion circuit (DSKW & SPC).

As shown in FIGS. 31 and 32, in the signal transmission system of the twelfth embodiment, the clock clk transmitted via the clock signal line 502 is captured by the clock latch unit 681. The clock latch unit 681 is supplied with the clock clk, and performs two interleaved latch circuits 681a and 681.
1b, and each of the latch circuits 681a and 6
Reference numeral 81b captures the clock clk at a predetermined timing by a signal (strobe signal) from the phase interpolator 684.

The control signal generation circuit 682 includes a latch circuit 6
Up signal UP according to the outputs of 81a and 681b
And a down signal DN to an up / down counter 683. The up / down counter 683 counts the up signal UP and the down signal DN and feedback controls the phase interpolator 684 to output the strobe signal of the latch circuits 681a and 681b. The timing is controlled. The output of the up / down counter 683 is also supplied to the phase interpolators 6841 to 684n for the respective data DD1 to DDn, and the latch circuits 681 of the latch units 6811 to 681n, respectively.
The fetch timing of 1a, 6811b to 681na, 681nb is controlled.

Here, for each of the data lines 521 to 52n, for example, a phase adjustment test is performed as a calibration mode when the power is turned on, and an initial value setting circuit 6871 to store the delay amount for each signal line. 687n are provided,
This initial value and the output of the up / down counter 683 are added by the adder circuits 6861 to 686n and supplied to the phase interpolators 6841 to 684n to absorb variations in the phase between the signal lines in the initial state. In the data transmission mode, data is taken in correctly. Further, each phase interpolator 684, 6841-
For the 684n, a four-phase clock in which the master clock (clock on the receiving side) clkm is processed by the DLL circuit 680 to reduce the frequency f of the clock clkm to 1/8 (divided by 8) is supplied. ing. Note that the phase interpolator 68 is output from the up / down counter 683.
The signals supplied to 4,6841 to 684n and the initial values stored in the initial value setting circuits 6871 to 687n are, for example, 6-bit signals. The up / down counter 683 corresponds to, for example, the charge pump 603 in the ninth embodiment shown in FIG. However, the charge pump 603 in the ninth embodiment processes the clock phase information in an analog manner, whereas the up / down counter 683 in the twelfth embodiment processes the clock phase information as a digital value. Different.

The output of the phase interpolator 684 is supplied to a clock generation circuit 685 and to each of the retiming circuits 6881 to 688n, and the clock generation circuit 685 generates a clock clkc for logic. Also, the retiming circuit 6881 (6881-68)
8n) includes three latch circuits 6881a, 6881b, and 6881c.
a is a latch circuit 681a of the clock latch unit 681.
And the same strobe signal is supplied to the latch circuit 6.
881b and 6881c have a clock latch 68
The same strobe signal as the one latch circuit 681b is supplied.

The retiming circuits 6881 to 688n
Thus, for example, each data DD1 to DD1 shown in FIG.
A signal whose DDn changes at the same timing is obtained. However, as described with reference to FIG. 15, a delay of one bit or more may exist between these data DD1 to DDn. Therefore, the outputs of the retiming circuits 6881 to 688n are supplied to the deskew and serial-parallel conversion circuit (DSKW & SPC) 6
891 to 689n and processed so that the output timing of all data coincides with the data with the latest timing. Further, the deskew and serial-parallel conversion circuits 6891 to 689n perform serial-parallel conversion of data, thereby lowering the operating frequency in the logic circuit (reception-side circuit).

As described above, according to the signal transmission system of the twelfth embodiment, since the distribution of the clock phase information is performed by the digital signal, there is no fear that jitter occurs in the transmission process, and the multi-bit signal is transmitted. Transmission and reception can be performed stably. As described above, according to each embodiment of the present invention, for example, a signal can be correctly received even when there is a skew many times as long as the data period, and the timing of capturing the signal is optimized for each data line. High-speed, error-free signal transmission becomes possible.

[0070]

As described above, according to the signal transmission system of the present invention, high-speed, error-free, large-capacity signal transmission can be performed without being affected by skew.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram schematically illustrating an example of a conventional signal transmission system.

FIG. 2 is a block circuit diagram schematically showing a principle configuration of a signal transmission system according to the present invention.

FIG. 3 is a timing chart (part 1) for explaining an example of an operation in the signal transmission system of FIG. 2;

FIG. 4 is a timing chart (part 2) for explaining an example of an operation in the signal transmission system of FIG. 2;

FIG. 5 is a block circuit diagram schematically showing a first embodiment of the signal transmission system of the present invention.

FIG. 6 is a timing chart for explaining an example of an operation in the signal transmission system of FIG. 5;

FIG. 7 is a block circuit diagram schematically showing a modified example of the signal transmission system shown in FIG. 5;

FIG. 8 is a timing chart for explaining an example of an operation in a modified example of the signal transmission system of FIG. 7;

FIG. 9 is a block circuit diagram schematically showing a second embodiment of the signal transmission system of the present invention.

FIG. 10 is a block circuit diagram schematically showing a third embodiment of the signal transmission system of the present invention.

FIG. 11 is a block circuit diagram schematically showing a fourth embodiment of the signal transmission system of the present invention.

FIG. 12 is a circuit diagram illustrating an example of a phase interpolator in the signal transmission system of FIG.

FIG. 13 is a block circuit diagram schematically showing a fifth embodiment of the signal transmission system of the present invention.

FIG. 14 is a timing chart (part 1) for explaining an example of the operation in the signal transmission system of FIG. 13;

FIG. 15 is a timing chart (part 2) for explaining an example of the operation in the signal transmission system of FIG. 13;

FIG. 16 is a block circuit diagram schematically showing a sixth embodiment of the signal transmission system of the present invention.

17 is a timing chart (part 1) for describing an example of an operation in the signal transmission system of FIG.

18 is a timing chart (part 2) for describing an example of an operation in the signal transmission system of FIG.

FIG. 19 is a block diagram schematically showing a seventh embodiment of the signal transmission system of the present invention.

20 is a circuit diagram illustrating an example of a PRD amplifier in the signal transmission system of FIG.

FIG. 21 is a diagram for explaining a timing signal used in the signal transmission system of FIG. 19;

FIG. 22 is a diagram (part 1) for describing an example of an operation in the signal transmission system of FIG. 19;

FIG. 23 is a diagram (part 2) for describing an example of an operation in the signal transmission system of FIG. 19;

FIG. 24 is a block circuit diagram schematically showing an eighth embodiment of the signal transmission system of the present invention.

FIG. 25 is a block circuit diagram schematically showing a ninth embodiment of the signal transmission system of the present invention.

26 is a block circuit diagram schematically showing a modification of the signal transmission system of FIG. 25.

FIG. 27 is a block circuit diagram schematically showing a tenth embodiment of the signal transmission system of the present invention.

FIG. 28 is a timing chart illustrating an example of an operation in the signal transmission system of FIG. 27.

29 is a diagram showing the relationship between the output of each latch circuit and the state of the internal clock in the signal transmission system of FIG. 27.

FIG. 30 is a timing chart for explaining an eleventh embodiment of the signal transmission system of the present invention.

FIG. 31 is a block circuit diagram (part 1) illustrating a twelfth embodiment of the signal transmission system of the present invention.

FIG. 32 is a block circuit diagram (part 2) showing a twelfth embodiment of the signal transmission system of the present invention.

[Explanation of symbols]

511-51n transmission-side drive circuits (drivers) 520, 521-52n signal lines (data signal lines) 530, 531-53n timing adjustment circuits (optimal timing defining means) 540, 541-54n data capture circuits (inputs) Latch) 5301 ... Phase comparison circuit 5302, 5303 ... Variable delay circuit 5311 ... Phase interpolator clk, clk1 to clkn ... Clock DD, DD1 to DDn ... Data (signal)

Claims (21)

[Claims] 1. A signal transmission system for transmitting and receiving a signal using a plurality of signal lines, wherein a signal delay generated in a process of transmitting and receiving the signal is set according to a skew of each of the signal lines. A signal transmission system comprising timing adjustment means for adjusting the timing at which a signal is received by the receiving circuit for each of the signal lines to an optimum timing for each of the signal lines. 2. The signal transmission system according to claim 1, wherein the timing adjustment unit effectively gives a variable delay to a clock for driving each of the receiving circuits for taking in each of the signals. A signal transmission system characterized by the following. 3. The signal transmission system according to claim 2, wherein said timing adjusting means includes a phase interpolator for generating a new clock having an intermediate phase from a plurality of clocks having different phases. Signal transmission system. 4. The signal transmission system according to claim 2, wherein said timing adjusting means includes a phase interpolator for generating a new clock having an intermediate delay from a plurality of clocks having different delays. A signal transmission system characterized by: 5. The signal transmission system according to claim 1, wherein said timing adjusting means effectively gives a variable delay to each of said signals on a transmission side. Signal transmission system. 6. The signal transmission system according to claim 1, wherein the signal transmission system further includes, for a plurality of signals fetched at optimal timings by the plurality of signal lines, all of the plurality of signals. A retiming circuit for re-timing the timing so that it changes in synchronization with a common clock, and a deskew circuit for inserting a delay of an integral multiple of the data period as necessary when there is a skew longer than the data period. A signal transmission system characterized by: 7. The signal transmission system according to claim 1, wherein the timing adjustment unit includes a plurality of latch circuits for capturing the signal, and performs a double or more interleaving operation by the plurality of latch circuits. A signal transmission system, characterized in that: 8. The signal transmission system according to claim 7, wherein the plurality of latch circuits performing the interleaving operation are each configured as a circuit to which a PRD method is applied. 9. The signal transmission system according to claim 1, wherein a clock for driving each of the receiving circuits for taking in each of the signals is obtained from a signal on a dedicated clock line. Signal transmission system. 10. The signal transmission system according to claim 1, wherein a clock for driving each of the receiving circuits for taking in each of the signals includes a signal on a data line or a dedicated clock line and the receiving circuit. A signal transmission system which performs a phase comparison with an internal reference clock and generates the signal internally based on a result of the phase comparison. 11. The signal transmission system according to claim 1, wherein the timing adjustment unit includes an optimal timing defining unit that defines an optimal point of the signal fetch timing on a receiving side, and the optimal timing defining unit includes: A signal transmission system wherein a first clock and a second clock having a predetermined phase difference from the first clock are used to define an optimum point of the signal fetch timing. 12. The signal transmission system according to claim 11, wherein the second clock has a phase difference of approximately 180 degrees with respect to the first clock. . 13. The signal transmission system according to claim 11, wherein said optimum timing defining means detects a transition region of data by said first clock and optimizes a timing of fetching said signal by said second clock. A signal transmission system wherein a signal is fetched by the receiving circuit at an optimum timing by defining a point. 14. The signal transmission system according to claim 1, wherein the timing adjusting means includes an optimum timing defining means for defining an optimum point of the signal fetch timing on a receiving side; Duty ratio is almost 50
A signal transmission system characterized in that an optimum point of the signal fetch timing is defined by using a percentage clock. 15. The signal transmission system according to claim 14, wherein said optimum timing defining means detects a transition region of data by said clock, and uses an inverted clock obtained by inverting said clock to obtain an optimum point of said signal fetch timing. The signal transmission system is characterized in that the signal is taken in the receiving circuit at an optimum timing by defining the following. 16. The signal transmission system according to claim 1, wherein the timing adjustment unit includes an optimal timing defining unit that defines an optimal point of the signal fetch timing on a transmitting side; A signal transmission system characterized in that data is transmitted at a timing such that a clock on a receiving side becomes an optimum point of data. 17. The signal transmission system according to claim 16, wherein said optimum timing defining means is a calibration mode for transmitting data at a first timing, and a timing shifted from said first timing by a predetermined phase difference. The calibration mode detects a transition region in the data at the first timing by the clock on the receiving side, and the data transmission mode includes a clock on the receiving side. Wherein the receiving circuit takes in data at a timing shifted from the first timing by a predetermined phase difference at an optimum point. 18. The signal transmission system according to claim 17, wherein the timing shifted from the first timing by a predetermined phase difference is a timing shifted from the first timing by a phase difference of substantially 180 degrees. A signal transmission system, comprising: 19. The signal transmission system according to claim 1, wherein the signal transmission system includes: a phase information extracting unit that extracts phase information of a clock on a clock line or a data line; And a storage unit for storing a relative phase value, which is a difference between a phase of an optimum reception timing obtained by each of the receiving circuits and a phase of a clock actually used, for each of the receiving circuits, When the signal is captured, the sum of the phase information of the clock and the stored relative phase value is formed for each of the receiving circuits to define the optimal receiving timing in each of the receiving circuits. A signal transmission system, characterized in that: 20. The signal transmission system according to claim 1, wherein said timing adjustment means includes a delay circuit for delaying data on a receiving side. 21. The signal transmission system according to claim 20, wherein said delay circuit is configured as a variable delay circuit capable of delaying an analog signal.