JPH11274477A - Insulated gate semiconductor device - Google Patents

Abstract

(57) [Summary] To provide an insulated gate semiconductor device capable of realizing Active Clamp and performing stable and high-speed operation. SOLUTION: All internal gate electrodes 71 are commonly connected to a gate terminal, and a floating gate electrode 72 is connected to a gate electrode of an NMOS transistor M1. An external emitter electrode 91 is provided on the first main surface of the P-type base diffusion region 21, and the N-type emitter diffusion region 31 and the P-type base diffusion region 21 are short-circuited. The source and the emitter terminal of the NMOS transistor M1 are also connected to the external emitter electrode 91. The drain of the NMOS transistor M1 is connected to an external terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for improving an overvoltage protection function in an insulated gate power device represented by an IGBT.

[0002]

2. Description of the Related Art A power device, for example, a power transistor represented by an insulated gate bipolar transistor (hereinafter referred to as "IGBT"), preferably has an increased withstand voltage and current carrying capability so that it can be used at a high voltage and a high current. . In particular, the element must be designed with a sufficient margin for the withstand voltage. When a power device is actually used in a circuit, an overvoltage may be applied due to induced electromotive force (spike voltage) generated in wiring inductance due to fluctuations in power supply voltage, regeneration of load power, high-speed current change during switching, and the like. It is. When a breakdown current flows at the P-type base junction of the IGBT cell (in the case of an N-channel IGBT), a thyristor parasitic on the IGBT is latched up, and the IGBT is destroyed. .

However, providing a sufficient margin for the breakdown voltage causes a problem that the manufacturing cost is increased and the power loss is increased. Therefore, investigations for an appropriate level are continuing.

As one solution to such a problem,
When a high voltage close to the breakdown voltage is applied between the main electrodes (between the collector and the emitter) of the power transistor, the voltage applied to the control electrode (gate) of the power transistor is controlled to temporarily operate the power transistor. Driving to ON state (hereinafter referred to as “ON driving”) (Ac
tive Clamp) is being considered. According to this method, since the impedance between the main electrodes decreases, the rise in the voltage applied thereto is suppressed, and the breakdown current can be prevented from flowing through the P-type base junction.

In the case of using the active clamp, a means for detecting that the voltage between the main electrodes is close to the breakdown voltage,
Means for turning on the power transistor with the control electrode is required. Conventionally, the detection of the voltage between the main electrodes is performed by connecting a high-voltage avalanche diode provided separately (so-called externally) to the power transistor between the collector and the gate of the power transistor. . The breakdown voltage of this avalanche diode is set to be slightly lower than the breakdown voltage of the power transistor to be protected. Therefore, when the avalanche diode breaks down, the gate of the power transistor can be charged with the charge that bears the breakdown current, and the gate voltage can be increased. Thus, the power transistor can be turned on immediately before the power transistor itself breaks down. At the time of normal ON driving, a diode is connected in series with the avalanche diode in the opposite direction so that a forward current does not flow through the avalanche diode.

The method of providing the avalanche diode separately from the power transistor in this manner is not suitable for mass production because it is necessary to make the breakdown voltage of the avalanche diode and the breakdown voltage of the power transistor in a proper relationship in separate manufacturing steps. . Further, there is a problem that the number of parts and the cost increase.

Therefore, a configuration in which an avalanche diode is built in a power transistor has been devised. Since they share some diffusion and lithography steps, they are also suitable for mass production. FIG. 8 shows a planar gate type N-channel IGBT 200 having an avalanche diode.
FIG. 2 is a cross-sectional view schematically showing the configuration of FIG. On the first main surface (the upper main surface in FIG. 8) of the N-type base region 1 having a low impurity concentration, P-type base diffusion regions 2 are selectively formed at predetermined intervals. Inside the P-type base diffusion region 2, an N-type emitter diffusion region 3 having a high impurity concentration and selectively formed on the first main surface is provided. A portion of the P-type base diffusion region 2 which is interposed between the N-type base region 1 and the N-type emitter diffusion region 3 and is the first region.
(Hereinafter referred to as “channel region”) is covered with a gate oxide film 6 formed of, for example, a silicon oxide film. For example, an internal gate electrode 7 made of polysilicon having a high impurity density is provided facing the channel region with a gate oxide film 6 interposed therebetween. Each of the internal gate electrodes 7 is commonly connected to a gate terminal.

P type base diffusion region 2 other than channel region
The N-type emitter diffusion region 3 and the N-type emitter diffusion region 3 both have an emitter terminal (Emit
ter).

The second main surface (the lower main surface in FIG. 8) of N-type base region 1 has N
Buffer region 4, P-type region 5 having an even higher impurity concentration than N-type buffer region 4, and external collector electrode 10.
Are stacked in this order. A collector terminal (Collector) is connected to the external collector electrode 10.

At least one P-type avalanche diode diffusion region 8 is formed separately from the P-type base diffusion region 2. These are all connected via an electrode 93 to the anode of an external diode D0. Diode D
The cathode of 0 is connected to the gate terminal. That is, the diode D0 is connected in series and in the opposite direction to the avalanche diode Da formed by the N-type base region 1 and the avalanche diode diffusion region 8 so that a forward current does not flow as described above.

Here, the avalanche diode diffusion region 8
By making it shallower than, for example, the P-type base diffusion region 2, the curvature of the shape can be made larger than that of the P-type base diffusion region 2. Accordingly, the reverse bias electric field in the avalanche diode Da can be made larger than the reverse bias electric field at the boundary between the N-type base region 1 and the P-type base diffusion region 2.

In the N-channel IGBT 200, a case is considered in which a gate drive power supply (not shown) and a suitable current limiting resistor (not shown) are used to bias the gate terminal so that the potential at the gate terminal becomes lower than the potential at the emitter terminal. in this case,
The potential of the channel region is lower than the potential of the P-type base diffusion region 2 other than the channel region, and the channel region is not depleted. Therefore, even if the potential of the collector terminal is higher than the potential of the emitter terminal, almost no current flows between them, and the transistor is turned off. When the voltage at the collector terminal is increased in this state, the depletion layer spreads in the N-type base region 1 and the electric field at the boundary between the N-type base region 1 and the P-type base diffusion region 2 becomes stronger.

This electric field is a critical electric field of silicon (about 2 × 1).
0 ⁵ V / cm) becomes higher when the IGBT impact ionization of carriers become rapidly intensely than shows the breakdown characteristics. However, in the N-channel IGBT 200, the avalanche diode Da is provided, and the N-channel IGBT 200 is provided.
The avalanche diode Da receives a critical electric field and breaks down with a potential difference lower than 200 breaks down. Then, due to the breakdown of the avalanche diode Da, a current flows into the gate drive power supply via the diode D0 and the current limiting resistor. As a result, the voltage generated at the current limiting resistor raises the potential of the gate terminal, and the potential of the channel region rises, where an inversion layer (channel) is generated.
Since a current flows between the emitter terminal and the collector terminal via the channel, the impedance between these main electrodes is reduced, and the overvoltage applied between the main electrodes is alleviated. The electric field at the boundary with the mold base diffusion region 2 is also alleviated, and breakdown here is avoided.

This operation is basically the same even when the N-channel IGBT 200 is in a transient operation state, and it is considered that the spike voltage in the turn-off operation can be suppressed. The configuration of the N-channel IGBT 200 is introduced in, for example, “Avalanche-guaranteed IGBT” (Tomoyuki Yamazaki et al., Proceedings of the National Convention of the Institute of Electrical Engineers of 1992).

[0015]

However, the above technique still has the following problems. First, the avalanche diode Da cannot be formed in the P-type base diffusion region 2 where the channel region is formed. For this reason, an avalanche diode Da is formed separately from the arrangement of the P-type base diffusion regions 2 which are repeatedly formed at a predetermined pitch. Accordingly, the electric field distribution is different between the vicinity of the avalanche diode Da and the vicinity of the arrangement of the P-type base diffusion regions 2, and particularly the N-type base region 1.
The yield that occurs when carriers are present at a high density is
The avalanche diode Da cannot be detected (that is,
The avalanche diode D before the breakdown between the N-type base region 1 and the P-type base diffusion region 2 under such a state.
a does not yield).

Secondly, there is an outflow of excess carriers accumulated in the N-type base region 1. At the time of turn-off, such excess carriers flow out not only through the P-type base diffusion region 2 but also through the avalanche diode Da. This raises the potential of the gate terminal, and the turn-off operation may be delayed.

Further, as a third problem, when an off state is obtained in a state where the potential of the gate terminal is lower than the potential of the emitter terminal, the diode D0 conducts and a reverse bias is applied to the avalanche diode Da, and the avalanche diode is applied. The breakdown voltage of the diode Da may substantially decrease.

The present invention avoids the above-mentioned problems while providing Acti
An object of the present invention is to provide a semiconductor device capable of performing stable and high-speed operation with the object of realizing ve clamp.

[0019]

Means for Solving the Problems Claim 1 of the present invention
Are insulated from the semiconductor substrate, first and second current electrodes sandwiching the semiconductor substrate, and the first and second current electrodes depending on the applied electric charge. And a potential detection gate in a floating state, wherein the potential detection gate depends on a potential difference between the first and second current electrodes. An insulated gate semiconductor device wherein a monitor potential is detected, and when the monitor potential exceeds a predetermined level, the drive gate conducts between the first and second current electrodes.

According to a second aspect of the present invention,
2. The insulated gate semiconductor device according to claim 1, wherein the driving gate and the detection gate are both provided in grooves formed in a thickness direction of the semiconductor substrate.

According to a third aspect of the present invention,
2. The insulated gate semiconductor device according to claim 1, wherein each of the driving gate and the detection gate has an insulating film with respect to a main surface of the semiconductor substrate on which the first current electrode is provided. 3. They are provided to face each other.

According to a fourth aspect of the present invention,
The insulated gate semiconductor device according to claim 1, wherein the insulated gate transistor includes a control electrode to which the potential detection gate is connected, and first and second current electrodes insulated from the control electrode. A driving circuit that charges and discharges the driving gate electrode of the insulated gate semiconductor device based on a current flowing through the second current electrode of the insulated gate transistor. The first current electrode of the insulated gate transistor is connected to the first current electrode of the insulated gate semiconductor device, and the insulated gate transistor is configured such that when the monitor potential exceeds the predetermined level, Conduct.

According to a fifth aspect of the present invention,
5. The insulated gate semiconductor device according to claim 4, wherein the drive circuit amplifies and outputs a current flowing through the second current electrode of the insulated gate transistor, thereby driving the insulated gate semiconductor device. Charge the gate.

According to a sixth aspect of the present invention,
5. The insulated gate semiconductor device according to claim 4, wherein the bipolar transistor has an emitter, a collector connected to the driving gate, and a base connected to the second current electrode of the insulated gate transistor. A first resistor connected between the emitter and the base of the bipolar transistor; and a second resistor connected between the collector and the base of the bipolar transistor.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a sectional view schematically showing a configuration of a semiconductor device 101 having a built-in overvoltage protection function according to the present invention and a connection between the semiconductor device 101 and an NMOS transistor M1. N-type base region 1 with low impurity concentration
A P-type base diffusion region 21 is formed on a first main surface (a main surface located upward in FIG. 1). An N-type emitter diffusion region 31 having a high impurity concentration is formed at a predetermined pitch on a first main surface of the P-type base diffusion region 21 (a main surface of the N-type base region 11 remote from the first main surface). It is provided selectively.

A groove is dug through the N-type emitter diffusion region 31 and the P-type base diffusion region 21 from the first main surface of the P-type base diffusion region 21 to the middle of the N-type base region 11. An internal gate electrode 71 formed of, for example, polysilicon having a high impurity concentration is buried in the trench by being wrapped in the gate insulating film 61. Further, the P-type base diffusion region 2 is located close to the groove in which the gate electrode 71 is formed.
1 from the first main surface to the middle of the N-type base region 11,
A groove is dug through the mold base diffusion region 21. A floating gate electrode 72 formed of, for example, polysilicon having a high impurity concentration is buried in the trench by being wrapped in the gate insulating film 62.

All the internal gate electrodes 71 are commonly connected to a gate terminal (Gate), and the floating gate electrode 72 is connected to the gate electrode of the NMOS transistor M1. An external emitter electrode 91 is provided on the first main surface of the P-type base diffusion region 21, and the N-type emitter diffusion region 31 and the P-type base diffusion region 21 are short-circuited. The external emitter electrode 91 has an NMOS transistor M
One source and emitter terminal (Emitter) is also connected. The drain of the NMOS transistor M1 is connected to an external terminal (Out).

The second main surface (the lower main surface in FIG. 1) of the N-type base region 11 has an N-type with a high impurity concentration (for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ ). A buffer region 4, a P-type region 5 having an impurity concentration higher than that of the N-type buffer region 4 (for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ ), and an external collector electrode 10 are stacked in this order. The external collector electrode 10 has a collector terminal (Collecto
r) is connected.

In such a configuration, the internal gate electrode 71 and the floating gate electrode 72 can be formed in the same step. The difference is that the N-type emitter diffusion region 31 is located above the groove in which these are housed.
Are provided, and two types of grooves can be easily realized by thinning out one N-type emitter diffusion region 31 formed at a predetermined pitch.

As is apparent from the above configuration, the semiconductor device 101 has a structure in which a part of the internal gate electrode 71 of the trench gate type IGBT is
In the groove surrounding the floating gate electrode 72, the formation of the N-type emitter diffusion region 31 is omitted.

In the semiconductor device 101, a case is considered in which a gate drive power supply (not shown) and an appropriate current limiting resistor (not shown) are used to bias the gate terminal so that the potential at the gate terminal becomes lower than the potential at the emitter terminal. In this case, the potential of the channel region of the P-type base diffusion region 21 which is in contact with the groove surrounding the internal gate electrode 71 is lower than the potential of the P-type base diffusion region 21 other than the channel region, and the channel region is depleted. Does not change. Therefore, even if the potential of the collector terminal is higher than the potential of the emitter terminal, almost no current flows between them, and the transistor is turned off.

When the voltage of the collector terminal is increased in this state, the depletion layer spreads in the N-type base region 11 and
The electric field at the boundary between the base region 11 and the P-type base diffusion region 2 (hereinafter referred to as “junction boundary”) becomes stronger. As the potential of the collector increases, the depletion layer extends longer,
The electric field at the junction boundary (hereinafter referred to as the “junction boundary electric field”) increases due to the effective charges therein. When the junction boundary electric field reaches the critical electric field of silicon, collisional ionization of carriers occurs violently, and the trench IGBT portion provided in the semiconductor device 101 breaks down.

At this time, the potential of the floating gate electrode 72 increases in proportion to the junction boundary electric field. This will be described below with reference to FIGS. The floating gate electrode 72 is close to the internal gate electrode 71 and can be formed in substantially the same shape. The change is small in a plane perpendicular to the direction. Therefore, a one-dimensional distribution of electric field and potential in the thickness direction of the element will be examined.

FIG. 2 is a schematic diagram considering only the thickness direction at the position where the floating gate electrode 72 exists.
Gate insulating film 62 surrounding floating gate electrode 72
Here appear as a gate insulating film 621 existing on the external emitter electrode 91 side of the floating gate electrode 72 and a gate insulating film 622 existing on the external collector electrode 10 side of the floating gate electrode 72. The thickness of the gate insulating film 621 and 622 and T _ox1, T _ox2 respectively, also the thickness of the floating gate electrode 72 and GD. On the external collector electrode 10 side of the gate insulating film 622, an N-type base region 11 exists with a thickness T _Si .

FIG. 3 is a graph showing the electric field strength in the structure shown in FIG. The horizontal axis represents the distance from the first main surface of the N-type base region 1. Since the floating gate electrode 72 can be treated as a conductor, the electric field strength is zero. It can be approximated that the effective charge density of the N-type base region 11 is substantially constant and the electric field intensity decreases linearly. Since the gate insulating films 621 and 622 are insulators, the electric field intensity takes a constant value _Eox . Assuming that the dielectric constant of silicon and the dielectric constant of the silicon oxide film are ε _Si and ε _ox , respectively, the electric field strength of the N-type base region 11 at a position in contact with the gate insulating film 622, that is, the strength of the junction boundary electric field is E _sm ＝ ε _ox・ E _ox / ε
Required as _Si .

FIG. 4 is a graph showing voltage in the structure shown in FIG. The horizontal axis represents the distance from the first main surface of the N-type base region 1 as in FIG. Voltage of the floating gate electrode 72 with respect to the potential (i.e., the potential of the external emitter electrode 91) in the first major surface of the N-type base region 1 is determined by Vfg = E _ox · T _ox1. N
Since the voltage applied to the type buffer region 4 and the P-type region 5 is small and is ignored, the voltage applied between the emitter terminal and the collector terminal is as follows: Vd = E _sm · T _Si / 2 + E _ox · (T _ox1 + T _ox2 ) = Vfg ｛(1/2) · (ε _ox / ε _Si ) · (T _Si / T
_ox1 ) + (1 + α)｝ (where α = T _ox2 / T _ox1 ).
As described above, with the potential of the floating gate electrode 72, the strength of the junction boundary electric field directly related to the breakdown condition,
The voltage applied between the emitter terminal and the collector terminal can be monitored.

As described above, the floating gate electrode 72
That the electric potential of is proportional to the junction boundary electric field is also confirmed by device simulation. Also, it can be confirmed by device simulation that the breakdown voltage of the IGBT portion hardly differs depending on the presence or absence of the floating gate electrode 72.

Since the potential of the floating gate electrode 72 is determined depending on the capacitance, a terminal through which a steady current does not flow, such as the gate electrode of an insulated gate element, is used to detect this. Here, the NMOS transistor M
One gate is connected to the floating gate electrode 72. Then, in order to protect the IGBT section from an overvoltage, the NMOS transistor M1 has a lower voltage than the IGBT section breaks down (that is, the junction boundary electric field becomes a critical electric field).
Is adjusted so that its gate conducts.

An NMO is provided between the external terminal and the gate terminal.
By connecting a driver circuit that supplies electric charge to the gate terminal based on the current flowing to the drain of the S transistor, the voltage of the gate terminal can be increased and the semiconductor device 101 can be temporarily turned on. However, it is desirable that the input capacitance of the insulated gate element (here, the NMOS transistor M1) having a gate to be connected to the floating gate electrode 72 is small. Since this input capacitance is connected as a load of the floating gate electrode 72,
This is because it is necessary to reduce the influence on the capacitance. In this case, it is necessary to reduce the size of the insulated gate element, and the current flowing between the transistor insulated gate element and the external emitter electrode 91 decreases. For example, the drive circuit may amplify this current. A specific configuration will be described in Embodiments 2 and 4 described later.

As described above, according to the present embodiment, the state immediately before the breakdown of the power transistor can be detected only by the capacitive coupling of the floating gate electrode 72 provided in the cell in which the IGBT section is formed. . That is, since the electric field of the cell is directly monitored, it is possible to protect against breakdown that occurs when carriers are present in the N-type base region 11 at a high density. Moreover, since the avalanche diode is not built-in, there is no increase in the gate voltage due to the outflow of excess carriers, and thus there is no influence on the turn-off operation. ) Does not cause a problem of a decrease in breakdown voltage. Therefore, breakdown and destruction of the power transistor can be avoided while solving all of the conventional first to third problems.

Moreover, since the internal gate electrode 71 and the floating gate electrode 72 can be obtained with a similar structure,
Only minor changes are required to the process of manufacturing a conventional IGBT. Since the floating gate electrode 72 can be formed in the conventional cell, the potential detected by the floating gate electrode 72 well reflects the electric field and voltage between the main electrodes, and accurately detects when an overvoltage state is applied. Can be done.

The internal gate electrode 71 can be used as the floating gate electrode 72. That is, only the internal gate electrode 71 functioning as the floating gate electrode 72 is connected to the gate of the NMOS transistor M1, and the other internal gate electrodes 71 are connected to the normal IG.
What is necessary is just to connect to a gate terminal similarly to BT. In this case, the N-type emitter diffusion region 31 exists near the upper portion of the internal gate electrode 71 functioning as the floating gate electrode 72, but the external emitter electrode 91 is not connected to the N-type emitter diffusion region 31. Or if an insulator is interposed between the N-type emitter diffusion region 31 and the external emitter electrode 91, the effects of the present invention will not be impaired in view of the explanation of FIGS. . In addition, the N-type emitter diffusion region 31 is formed at a predetermined interval, and it is not necessary to thin out the N-type emitter diffusion region 31. Therefore, the conventional manufacturing process can be utilized more advantageously.

Embodiment 2 FIG. 5 is a circuit diagram showing the present embodiment. In the present embodiment, a technique for driving power transistor 100 is described. As the power transistor 100, the semiconductor device 10 described in the first embodiment is used.
1 can be used. However, the symbol of the power transistor 100 in FIG.
In addition to the GBT symbol, a V-shaped figure is drawn to indicate the floating gate FG. The floating gate FG is electrically connected to the floating gate electrode 72 of the semiconductor device 101.

The floating gate FG is connected to the gate of the NMOS transistor M1, and the emitter terminal of the power transistor 100 is connected to the source thereof. The drain is connected to a potential point Vcc (hereinafter, the potential point and the potential to be given are used with the same sign) Vcc, which applies the potential Vcc, through a series connection of the resistors R1 and R2. The emitter of the PNP transistor Q1 is connected to a resistor R2.
Is connected to the potential point Vcc, the collector is connected to the gate terminal of the power transistor 100, and the base is connected to the drain of the NMOS transistor M1 via the resistor R1.

The gate driver 20 has a gate drive resistor Rg.
And an output terminal connected to the gate terminal of the power transistor 100 via the power transistor 100. The two potential points Vcc and Vee are connected and driven. Here, the potential Vee is lower than the potential Vcc. The gate driver 20 includes, for example, a complementary output stage, and allows a current to flow through its output terminal based on a signal applied to an input terminal In of the gate driver 20.

The circuit shown in FIG. 5 operates as follows. When the power transistor 100 is not in an overvoltage state, since the potential of the floating gate FG is low, N
The MOS transistor M1 is off, the drain current does not flow, and the PNP transistor Q1 is off. Therefore, the power transistor 100 is controlled to be turned on and off by the output of the gate driver 20 given to its gate terminal via the gate drive resistor Rg.

When the voltage applied between the collector terminal and the emitter terminal of the power transistor 100 increases,
The potential of the floating gate FG rises. Then, as described in the first embodiment, the NMOS transistor M
By properly setting the gate threshold value of 1, the NMOS transistor M1 turns on before the breakdown voltage is reached. Then, the PNP transistor Q is connected via the resistor R1.
1, a base current flows, and the PNP transistor Q1 turns on. A state in which the power transistor 100 is off,
Alternatively, during the turn-off operation, the output of the gate driver 20 is set to be equal to or lower than the potential of the emitter terminal of the power transistor 100.
Since a current flows into the gate driver 20 via the P transistor Q1 and the gate drive resistor Rg, a voltage is generated in the gate drive resistor Rg, and the power transistor 100
Of the gate terminal increases. As a result, the power transistor 100 is turned on, and an operation for preventing a rise in the potential of the collector terminal is performed. That is, the constant voltage clamping operation by analog feedback is performed. Therefore, the power transistor 1 due to the application of overvoltage
00 can be prevented beforehand.

The configuration of the gate driver 20 does not need to include a complementary output stage as long as it can sink the current supplied from the PNP transistor Q1 via the gate drive resistor Rg.

Embodiment 3 FIG. 6 is a sectional view schematically showing the configuration of the semiconductor device 102 having a built-in overvoltage protection function according to the present invention and the connection between the semiconductor device 102 and the NMOS transistor M1. P-type base diffusion regions 2 are selectively formed at a predetermined pitch on a first main surface (a main surface located upward in FIG. 6) of N-type base region 1 having a low impurity concentration. Inside the P-type base diffusion region 2, an N-type emitter diffusion region 3 having a high impurity concentration and selectively formed on the first main surface is provided. P-type base diffusion region 2
Of these, the channel region exposed between the N-type base region 1 and the N-type emitter diffusion region 3 and exposed on the first main surface is, for example, a gate oxide film 6 formed of a silicon oxide film. Covered by For example, an internal gate electrode 7 made of polysilicon having a high impurity density is provided facing the channel region with a gate oxide film 6 interposed therebetween. All the internal gate electrodes 7 have a common gate terminal (Ga
te). The P-type base diffusion region 2 and the N-type emitter diffusion region 3 other than the channel region are both connected to the emitter terminal (Emitter) via the external emitter electrode 92 on the first main surface. As in the first embodiment, N-type buffer regions 4 and P are provided on the second main surface of N-type base region 1 (the main surface located below in FIG. 6).
The mold region 5 and the external collector electrode 10 are laminated in this order,
Collector terminal (Collector) for external collector electrode 10
Is connected.

The configuration described above is a so-called planar type I
The semiconductor device 102 is additionally provided with a floating gate electrode 73 as a characteristic configuration, which is a GBT and is also provided in the conventional N-channel IGBT 200. The floating gate electrode 73 faces the first main surface of the N-type base region 1 where the P-type base diffusion region 2 is not formed via the gate oxide film 63. The floating gate electrode 73 is connected to the gate electrode of the NMOS transistor M1.

The source and emitter terminals of the NMOS transistor M1 are also connected to the emitter electrode 92. N
The drain of the MOS transistor M1 is an external terminal (Out)
It is connected to the.

As shown in FIG. 6, the internal gate electrode 7
Although the floating gate electrode 73 has a portion facing the first main surface where the P-type base diffusion region 2 is not formed, the floating gate electrode 73 has an N-type emitter diffusion region on the first main surface like the internal gate electrode 7. It does not have a region facing the P-type base diffusion region 2 sandwiched between the region 3 and the N-type base region 1. On the other hand, as shown in FIG. 6, a gate oxide film 6 is formed on the P-type base diffusion region 2 sandwiched between the N-type emitter diffusion region 3 and the N-type base region 1 on the first main surface.
An internal gate electrode 74 facing through the gate 3 can be provided and connected to the internal gate electrode 7.

Since the floating gate electrode 73 and the internal gate electrodes 7 and 74 have the above-described configuration, they can be easily formed in the same process. Therefore, similarly to the first embodiment, only a slight change is required for the process of manufacturing the conventional IGBT. Since the floating gate electrode 73 can be formed in the conventional cell, the potential detected by the floating gate electrode 73 reflects the electric field and voltage between the main electrodes well, and can accurately detect when an overvoltage state is applied. Can be done.

The internal gate electrode 7 can be used as the floating gate electrode 73. That is, only the internal gate electrode 7 functioning as the floating gate electrode 73 is connected to the gate of the NMOS transistor M1, and the other internal gate electrodes 7 are connected to a normal IGBT.
May be connected to the gate terminal in the same manner as described above. In this case, the N-type emitter diffusion region 3 exists below the internal gate electrode 7 functioning as the floating gate electrode 73, but the external emitter electrode 92 is connected so as not to be connected to the N-type emitter diffusion region 3. Or shaping this N
If an insulator is interposed between the typed emitter diffusion region 3 and the external emitter electrode 92, the effects of the present invention are not impaired in view of the description of FIGS. In addition, there is no need to divide the internal gate electrode 74 and the floating gate electrode 73 as shown in FIG. 6, so that more conventional manufacturing steps can be used, which is advantageous.

Further, in this embodiment, as compared with the embodiment shown in the first embodiment, the cost can be suppressed because there is no process for forming a groove, which is complicated in etching and film formation steps. However, since the technique described in the first embodiment is of the trench gate type, the trade-off performance between the ON state (or saturation) voltage and the switching loss is excellent.

Naturally, the semiconductor device 102 of the present embodiment can be employed as the power transistor 100 in the second embodiment. In that case, the floating gate FG is electrically connected to the floating gate electrode 73.

Embodiment 4 FIG. FIG. 7 is a circuit diagram showing the present embodiment. In this embodiment, the power transistor 1
00 shows a technique for driving the power transistor 100
The semiconductor device 10 described in the first and third embodiments
1,102 can be used. The floating transistor FG is connected to the gate of the NMOS transistor M1, and the emitter terminal of the power transistor 100 is connected to the source thereof. The drain is NP via the resistor R1
It is connected to the base of N transistor Q2. The output terminal of the gate driver 20 is connected to the anode of the diode D1, and the cathode of the diode D1 is connected to the gate terminal of the power transistor 100 via the gate drive resistor Rg. The emitter of the NPN transistor Q2 is connected to the anode of the diode D2,
Is connected to the anode of the diode D1. Further, a resistor R3 is connected between the emitter and the base of the NPN transistor Q2. The base and collector of the NPN transistor Q2 are resistors R2 and R4, respectively.
Is connected to the gate terminal of the power transistor 100 via

The circuit shown in FIG. 7 avoids overvoltage breakdown caused by spike voltage caused by parasitic inductance of wiring when turn-off operation occurs, rather than overvoltage protection due to power supply voltage fluctuation. Can do things.

When the power transistor 100 is driven to be turned on, the potential at the output terminal of the gate driver 20 is set to be about 15 V higher than the potential at the emitter terminal of the power transistor 100, and the diode D1 receives a forward bias and conducts. At this time, since the diode D2 receives a reverse bias and does not conduct, the transistor Q2 does not participate in the operation of the power transistor 100. Also, since the potential of the floating gate FG does not increase, the NMOS transistor M1 does not participate in the operation of the power transistor 100.
Therefore, a current is supplied to the gate terminal of the power transistor 100 via the gate drive resistor Rg (that is, the input capacitance of the power transistor 100 is charged), the potential of the gate terminal increases, and the power transistor 100 is turned on.

When driving the power transistor 100 to the off state, the potential of the output terminal of the gate driver 20 is set to be lower than the potential of the emitter terminal of the power transistor 100. Therefore, the diode D1 receives a reverse bias, and the gate drive resistor Rg does not participate in the operation of the power transistor 100. On the other hand, the diode D2 receives a forward bias, and part of the charge charged in the gate terminal of the power transistor 100 flows into the base of the NPN transistor Q2 via the resistor R2. Since this is amplified by the NPN transistor Q2, the power transistor 10
The charge flows from the gate terminal 0 to the output end of the gate driver 20 via the resistor R4, the collector and the emitter of the NPN transistor Q2, and the diode D2. As a result, the potential of the gate terminal of the power transistor 100 decreases, and the power transistor 100 is turned off.

In the turn-off operation, the potential at the collector terminal of the power transistor 100 rises, and the current flowing through the collector terminal decreases. However, an induced voltage is generated in the parasitic inductance of the wiring, and a high voltage higher than the power supply voltage is applied to the power transistor. 100 may be applied. In such a case, if an overvoltage state does not occur, the NMOS transistor M1 is in the off state because the potential of the floating gate FG is low, and no drain current flows. Therefore, the electric charge stored in the gate terminal of the power transistor 100 is discharged via the NPN transistor Q2 and the resistor R4, and the transition to the off state ends. In this case, NP
The current obtained from the gate terminal of the power transistor 100 is amplified by the resistor R4
Can be set to a large value, so that the state can be quickly shifted to the off state.

However, when an overvoltage occurs during the turn-off operation, the potential of the floating gate FG of the power transistor 100 increases, and the NMOS transistor M1 turns on. Therefore, the base current of the NPN transistor Q2 is bypassed via the resistor R1, and N
The PN transistor Q2 turns off. Therefore, the current from the gate terminal of power transistor 100 is equal to resistance R
1, R2. Normally, the resistors R1 and R2 that determine the operating bias point of the NPN transistor Q2 are set to be large, so that the current flowing therethrough is suppressed.

By the above phenomenon, the speed at which the potential of the gate terminal of the power transistor 100 decreases becomes slow, and the reduction rate of the current flowing through the collector terminal of the power transistor 100 decreases.
Even if the parasitic inductance exists, the induced voltage becomes small. Therefore, the potential of the collector terminal of the power transistor 100 decreases, and the overvoltage state does not further progress.
That is, also in this case, the constant voltage clamp is performed by the analog feedback.

In this embodiment, the power transistor 1
The power transistor 100 is driven without the potential of the gate terminal 00 being lower than the potential of the emitter terminal.
Compared to the technique shown in the second embodiment, the power supply for turning on (potential point Vcc connected to the emitter of PNP transistor Q1) can be protected from overvoltage without need, so that NPN transistor Q2, Diode D
1, D2, resistors R1 to R4, NMOS transistor M1
Can be integrated with the power transistor 100, and a semiconductor element can be apparently obtained as one IGBT 300.

Other Modifications In the embodiment described above, an N-channel IGBT has been introduced. However, the present invention can be applied to a P-channel IGBT.
Like ET, EST (Emitter Switched Thyristor)
The present invention can be similarly applied to a semiconductor element which can cut off a current flowing through the semiconductor element under the control of its own insulating gate. Further, the elements shown in the second and fourth embodiments, that is, the insulated gate element for detecting overvoltage, the transistor, the diode, and the resistor which constitute the feedback circuit are mounted on a substrate different from the power transistor chip and connected to the wiring. They can be combined. Of course, it is also possible to integrate the power transistor on the same chip by using a junction separation or a dielectric separation method.

[0066]

According to the present invention, according to the insulated gate semiconductor device of the first aspect, the potential is monitored at the so-called insulated gate, and the state is established when the first and second current electrodes are non-conductive. When an excessive voltage is applied, it is temporarily turned on. Therefore, it is possible to protect the semiconductor layer existing between the first and second current electrodes from excessive voltage even against breakdown that occurs when carriers are present unevenly. In addition, since the avalanche diode is not built in, even if excess carriers flow out, the voltage of the driving gate does not increase and the turn-off operation is not affected. Further, even when the operation is performed in a state where a reverse bias is applied between the driving gate and the first current electrode, a problem of a decrease in breakdown voltage does not occur.

According to the insulated gate semiconductor device of the second or third aspect of the present invention, the drive gate and the detection gate can be obtained with configurations similar to each other. Only minor changes are required to the manufacturing process. The detection gate can also be formed in the region where the driving gate provided in the conventional insulated gate type semiconductor device is formed, so that the monitor potential is the electric field and voltage between the first and second current electrodes. Reflect well. Therefore, it is possible to accurately detect an excessive voltage applied when the first and second current electrodes are non-conductive.

According to the insulated gate semiconductor device of the fourth aspect of the present invention, when the monitor potential exceeds a predetermined level while the potential detection gate is kept in a floating state, the second of the insulated gate transistor is turned off. A current flows through the current electrode, and the driving circuit can temporarily turn on the insulated gate semiconductor device.

According to the insulated gate type semiconductor device of the present invention, the current flowing through the current electrode of the insulated gate type transistor is amplified to charge the driving gate, so that the size of the insulated gate type transistor is reduced. The effect of claim 4 can be obtained even if it is reduced. Therefore, the input capacitance of the insulated gate transistor is reduced, the influence on the capacitance of the detection gate is reduced, and in a state where the first and second current electrodes of the insulated gate semiconductor device are non-conductive, It is possible to accurately detect when an excessive voltage is applied.

According to the insulated gate type semiconductor device of the present invention, if an overvoltage state does not occur in the turn-off operation, the insulated gate type semiconductor device is in a non-conductive state, and is greatly increased by the amplifying action of the bipolar transistor. The driving gate of the insulated gate transistor is discharged by the current. Therefore, the insulated gate semiconductor device turns off at high speed. On the other hand, when an overvoltage state occurs during the turn-off operation, the insulated gate transistor conducts, so that the current flowing through the base of the bipolar transistor is bypassed, and the bipolar transistor is turned off. Therefore, the driving gate of the insulated gate semiconductor device is discharged via the first and second resistors, and the turn-off becomes slow. For this reason, even if the parasitic inductance exists, the induced voltage does not increase, and the overvoltage state does not further progress.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically illustrating a configuration of a first embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating Embodiment 1 of the present invention.

FIG. 3 is a graph illustrating the first embodiment of the present invention.

FIG. 4 is a graph illustrating the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

FIG. 6 is a cross-sectional view schematically illustrating a configuration of a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 8 is a cross-sectional view schematically showing a conventional technique.

[Explanation of symbols]

1,11 N type base region, 7, 71, 74 internal gate electrode, 72, 73 floating gate electrode, R2,
R3 resistor, Q2 NPN transistor, M1 NMO
S transistor, 9,91,92 External emitter electrode,
10 External collector electrode.

Claims (6)

[Claims] 1. A semiconductor substrate, first and second current electrodes sandwiching the semiconductor substrate, and insulated from the first and second current electrodes, the first and second current electrodes depending on applied charges. And a potential detection gate in a floating state, wherein the potential detection gate depends on a potential difference between the first and second current electrodes. An insulated gate semiconductor device, wherein a monitor potential is detected, and when the monitor potential exceeds a predetermined level, conduction is provided between the first and second current electrodes by the driving gate. 2. The insulated gate semiconductor device according to claim 1, wherein both the driving gate and the detection gate are provided in a groove formed in a thickness direction of the semiconductor substrate. 3. The drive gate and the detection gate are both provided via an insulating film with respect to a main surface of the semiconductor substrate on a side where the first current electrode is provided. Item 2. An insulated gate semiconductor device according to item 1. 4. An insulated gate transistor having a control electrode to which the potential detection gate is connected, first and second current electrodes insulated from the control electrode, and an insulated gate transistor of the insulated gate transistor. A driving circuit that charges and discharges the driving gate electrode of the insulated gate semiconductor device based on a current flowing through the second current electrode, wherein the first current electrode of the insulated gate transistor includes: The insulated gate semiconductor device according to claim 1, wherein the insulated gate transistor is connected to the first current electrode of the insulated gate semiconductor device, and the insulated gate transistor conducts when the monitor potential exceeds the predetermined level. 5. The drive circuit according to claim 4, wherein the drive circuit amplifies and outputs a current flowing through the second current electrode of the insulated gate transistor, thereby charging the drive gate of the insulated gate semiconductor device. An insulated gate semiconductor device as described in the above. 6. A bipolar transistor having an emitter, a collector connected to the driving gate, and a base connected to the second current electrode of the insulated gate transistor, and the emitter of the bipolar transistor. The insulated gate semiconductor device according to claim 4, further comprising: a first resistor connected between the collector and the base of the bipolar transistor; and a second resistor connected between the collector and the base of the bipolar transistor. .