JPH11260817A - Semiconductor integrated circuit wiring method - Google Patents

Abstract

(57) Abstract: A technology for connecting wiring layers of a semiconductor integrated circuit having three or more wiring layers. The I-th via connecting the I-th layer to the I + 1-th layer, the I + 1-th via connecting the I + 1-th layer to the I + 2-th layer are stacked, and the I + 1-th layer is arranged so as to surround the I-th via and the I + 1-th via. The wiring interlayer connection component is connected to the I-th via and the (I + 1) -th via after the wiring by the signal pin portion of the functional block or the automatic wiring device.
The vias are arranged at the stacked positions, and the definition data of the functional blocks used in the automatic wiring device are expressed only by the portions of the I-th layer and the (I + 2) -th layer.
For the layer, the (I + 1) -th component of the wiring interlayer connection component
Replace with layer part. In the stack position of the (I) -th via and the (I + 1) -th via, wiring by an automatic wiring device using the (I + 1) -th layer becomes possible, thereby shortening the wiring time of a semiconductor integrated circuit, improving wiring efficiency, and achieving high integration. .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for connecting different wiring layers in a semiconductor integrated circuit having three or more wiring layers.

[0002]

2. Description of the Related Art Conventionally, in a wiring of a semiconductor integrated circuit having a plurality of wiring layers, connecting a first layer and a third layer at one position is realized by a stack of a first via and a second via. I was

[0003]

However, according to the above-described conventional method, the first layer and the third layer can be connected, but the second via is located at the position where the first via and the second via are stacked. Layer cannot be used. FIG. 10 is an elevational view in the case where the first and third layers are connected in three wiring layers using the above-described conventional technology. FIG. 11 is a plan view and an elevation view showing a first component via for connecting the first layer and the second layer according to the related art.
FIG. 2 is a plan view and an elevation view showing a second component via for connecting a second layer and a third layer according to the related art. In FIG. 10, reference numeral 1001 denotes a first layer portion;
2 is the first via, 1003 is the second layer portion, 1004 is the second layer
Via 1005 is a third layer portion. In FIG.
1101 is a first layer portion, 1102 is a first via, 1103
Is a second layer portion. In FIG. 12, reference numeral 1201 denotes a second layer portion, 1202 denotes a second via, and 1203 denotes a third layer portion.

[0004] In order to realize the configuration of FIG.
In addition, when the first component via and the second component via shown in FIG. 12 are registered by a CAD device, and the first layer and the third layer are connected at the same position, the first component via and the second component via are connected. By stacking, for the second layer, data duplication is avoided by selecting either the second layer part of the first component via or the second layer part of the second component via by ORing the data, There is a method of creating mask data.

According to the structure shown in FIG. 10 realized by the above-described method, the connection between the first layer and the third layer becomes possible. At this time, the second layer is connected to the first layer via the first via. Then, it is connected to the third layer via the second via. In such a structure,
The second layer is always at the same potential as the first layer and the third layer, and at the position where the first via and the second via are stacked, a signal different from the signal using the first layer and the third layer is transmitted to the second layer. The wiring cannot be performed using the layers, and the wiring efficiency between the functional blocks on the chip deteriorates, and the chip area increases.

FIG. 13 is a diagram showing a case where the second layer is wired near the position where the first via and the second via are stacked. In FIG. 13, reference numeral 1301 denotes a first via and a second via stacked according to the structure of FIG. 10, 1302 denotes a first layer wiring used for a first signal, and 1303 denotes a third layer used for a first signal. The wiring 1304 is a second-layer wiring used for a second signal different from the first signal. FIG.
In 3, the signal wiring to be routed by the second layer must bypass the second layer part because the second layer part is present at the joint between the first via and the second via. Accordingly, the wiring length of the signal wiring is increased, and when the wiring is congested, there is a possibility that the signal wiring path is eliminated.

[0007]

SUMMARY OF THE INVENTION Accordingly, the present invention is to solve the above-mentioned problem. First, the I-th via and the (I + 1) -th via are arranged at the same position. Is placed on a signal pin of an arbitrary functional block by arranging a component for connection between wiring layers, which is completely or partially surrounded by a space of a finite value, and is disposed on a signal pin of an arbitrary functional block. In the definition data of the function block to be used, the signal pins of the function block are expressed only by the portions of the I-th layer and the (I + 2) -th layer of the component for connection between the wiring layers. The portion included in the (I + 1) th layer portion of the wiring interlayer connection component is deleted along the (I + 1) th layer portion of the wiring interlayer connection component, and And it replaces the +1 layer portion.

Second, when the I-th component via and the (I + 1) -th component via are arranged at the positions of the signal pins of the functional block, the portions included in the (I + 1) -th layer portion of the component for connecting between wiring layers are connected to the wiring. Without removing along the (I + 1) th layer portion of the component for interlayer connection,
The (I + 1) th layer part of the (I + 1) th component via or the (I +) th layer of the (I + 1) th component via
One layer portion is overlapped.

Third, when the I-th component via and the (I + 1) -th component via are arranged at the same position after the automatic wiring, the I-th component via and the (I +)-th component via are arranged in the same position.
It is characterized in that one set of one component via is replaced with a component for connection between wiring layers.

Fourth, in the definition data of the top cell used in the automatic wiring device, the third component for wiring interlayer connection replaced with one set of the I-th component via and the (I + 1) th component via is the I-th layer. And I
+2 layer portion is assigned to an arbitrary signal pin, and a node connected to the I layer layer portion of the I component via and a node connected to the I layer layer of the I component via are connected to a net connected to the I component via and the I + 1 component via. A node connected to the I + 2 layer portion is added, and additional automatic wiring is performed.

Fifth, in the first to fourth definition data of the top cell used in the automatic wiring device, a virtual via is arranged at the position of the component for connection between wiring layers, and a virtual via is placed between the virtual via and the I-th via. , And a constraint that prohibits stacking of vias between the virtual via and the (I + 1) th via is provided.

[0012]

Since the present invention has the above configuration, firstly, it is possible to connect the wirings of the I-th layer and the I + 2-th layer to the signal pins of the functional block, and to use the I + 1-th layer at the same position as the signal pins. Thus, it becomes possible to automatically wire a signal different from the signal pin.

Second, the first processing can be performed, and the same signal as the signal pin can be automatically wired.

Third, it is possible to wire a signal different from the I-th via and the (I + 1) -th via using the (I + 1) -th layer at a position where the I-th via and the (I + 1) -th via are stacked other than the signal pins. become.

Fourth, a third additional automatic wiring becomes possible.

Fifth, in the first to fourth wirings, the wiring of the (I + 1) th layer limited to signals different from those of the (I) th via and the (I + 1) th via of the wiring interlayer connection component can be realized.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a plan view and an elevation view of a component for connection between wiring layers in a semiconductor integrated circuit having three wiring layers according to an embodiment of the present invention. . In FIG. 1, 101 is a first layer portion, 10
2 is a first via, 103 is a second layer portion, 104 is a second via, 105 is a third layer portion, 106 is a pin portion of the first layer in the definition data of the automatic wiring device, and 107 is definition data of the automatic wiring device. , A pin portion 108 of the third layer is a component for connection between wiring layers. In FIG. 1, the first
The layer portion 101 and the third layer portion 105 include a first via 102,
Although the connection is made via the second via 104, in the automatic wiring device, only the pin portion 106 of the first layer in the definition data of the automatic wiring device and the pin portion 107 of the third layer in the definition data of the automatic wiring device should be expressed. Accordingly, since there is no expression of the second layer in the definition data of the automatic wiring device between the pin portion 106 of the first layer and the pin portion 107 of the third layer, the automatic wiring device using the second layer Wiring becomes possible.

FIG. 2 is a diagram showing signal pins of a functional block used in an automatic wiring device, according to the first embodiment of the present invention. In FIG. 2, 201 is a first layer portion,
202 is the third layer portion, 203 is the center of the signal pin, 204
Is a second layer region. In the wiring of the automatic wiring device using the second layer, the second layer region 204 can be used.

FIG. 3 is a diagram showing a case where two different signals are wired using the structure of FIG. In FIG. 3, reference numeral 301 denotes a component for connecting between wiring layers in FIG.
2 is a first via and a second via of a component for connecting between wiring layers.
Vias, 303, a second layer portion of the wiring layer connection component, 304, a first layer wiring connected to the first via and the second via for the first signal wiring, and 305, a first signal wiring A third-layer wiring 306 connected to the first via and the second via for wiring, and a second-layer wiring 306 for a second signal different from the first signal. In FIG. 3, the second signal is used by using the second layer without bypassing the wiring layer connecting component 301 arranged to route the first signal using the first layer and the third layer. The configuration of the second layer wiring 306 is possible.

FIG. 4 is a view showing a wiring step of the second layer, showing an embodiment of the first aspect of the present invention. In FIG. 4, reference numeral 401 denotes a second-layer wiring, and 402 denotes a center position of a component for connecting between wiring layers. Reference numeral 108 denotes a component for connecting between wiring layers in FIG. 1, 103 denotes a second layer portion of the component for connecting between wiring layers, and 109 denotes first and second vias of the component for connecting between wiring layers. As shown in FIG. 4, in step 1, signals are wired using the second layer. In step 2, the component area for connecting the wiring layers of the second layer signal is deleted. By arranging the component 108 at the center position 403 of the component for wiring interlayer connection, the first via and the second via 10 of the component for wiring interlayer connection are formed by the second layer portion 103 of the component for wiring interlayer connection.
9, the wiring 401 of the second layer is connected.

FIG. 5 is a view showing a second-layer wiring step, showing an embodiment of the second aspect of the present invention. In FIG. 5, reference numeral 501 denotes a second layer wiring, 502 denotes a first component via, 503 denotes a second layer portion of the first component via,
04 indicates the center position of the first component via. Reference numeral 108 denotes a component for connecting between wiring layers in FIG.
03 is the second layer portion of the component for wiring interlayer connection, 1
Reference numeral 09 denotes a first via and a second via of a component for connection between wiring layers. As shown in FIG.
The signal is wired using the layers, the first component via 502 is arranged in Step 2, and the wiring layer connection component 108 is arranged in the center position 504 of the first component via in Step 3. By the steps 1 to 3, the second component wiring 501, the second component part 503 of the first component via, and the second component of the component for interconnection between wirings are located at the center position 504 of the first component via.
Since the layer portions 103 overlap, when the second layer wiring is formed by the OR processing of the data, the wiring 501 of the second layer is connected to the first via and the second via 109 and uses the wiring interlayer connection component shown in FIG. In addition, it is possible to connect a second layer wiring to the first via and the second via of the wiring layer connecting component.

FIG. 6 is a diagram showing a wiring flow showing an embodiment of the third aspect of the present invention. In FIG.
Reference numeral 1 denotes wiring by an automatic wiring device, 602: extraction of a via stack position, 603: replacement of a component for connection between wiring layers, 604: wiring using the second layer at the via stack position, 605: CAD data output, and 606: via The processing of the second layer at the stack position, 607 indicates output of mask data. In the above wiring flow, after the wiring 601 is completed by the automatic wiring device, the stack position of the first component via and the second component via is extracted in via stack position extraction 602. The extraction is DR
In the case where the condition of the via stack is satisfied in C, this is realized by processing such as outputting the position. After the completion of the extraction, the process proceeds to the process 603 of replacing the component for connection between wiring layers. The replacement 603 of the wiring layer connection component is realized by deleting the first component via and the second component via at the position extracted by the via stack position extraction 602, and disposing the wiring layer connection component at the same position. I do. After the replacement 603 of the components for connecting the wiring layers, the wiring 604 using the second layer at the via stack position becomes possible. Wiring 6 using second layer at via stack position
After completion of the step 04, when CAD data output 605 is performed, CAD data using the second layer at the via stack position is output. The second layer of the CAD data includes signal wiring,
Since there is an overlap between the second layer portion of the first component via, the second layer portion of the second component via, and the second layer portion of the component for wiring interlayer connection, the second layer at the via stack position is used to eliminate the overlap. Is performed 606. Processing 606 of the second layer at the via stack position
If there is no first component via or second component via, this is realized by steps 1 to 3 of FIG.
If there is a first component via or a second component via, this is realized by steps 1 to 3 in FIG. After the processing 606 of the second layer at the via stack position is completed, the output 607 of the mask data is performed, and the wiring in the semiconductor integrated circuit according to claim 3 of the present invention is completed.

FIG. 7 is a diagram showing a wiring flow showing an embodiment of the fourth aspect of the present invention. In FIG. 7, 7
01 is wiring by an automatic wiring device, 702 is extraction of a via stack position, 703 is replacement of a component for connection between wiring layers, 704 is creation of a signal pin at a via stack position, and 705 is correspondence between wiring information after automatic wiring and a netlist. Data output; 706, addition of signal pin connection node in netlist; 707, additional input of wiring information after automatic wiring and corresponding data of netlist; 708, additional wiring by automatic wiring device; 709, output of CAD data , 710 indicate processing of the second layer at the via stack position, and 711 indicates output of mask data. In the wiring flow, after the wiring 701 is completed by the automatic wiring device, a stack position of the first component via and the second component via is extracted in a via stack position extraction 702. The extraction is realized by processing such as outputting the position when the condition of the via stack is satisfied in the DRC.
After the completion of the extraction, the process proceeds to a process 703 of replacing the component for wiring interlayer connection. In the replacement 703 of the component for connection between wiring layers, the extraction 70 of the via stack position is performed.
This is realized by deleting the first component via and the second component via at the position extracted by Step 2 and arranging the wiring interlayer connection component at the same position. Replacement of component for connection between wiring layers 703
After completion, creation of a signal pin at the via stack position 70
Perform 4. At this time, as in FIG. 2, the signal pins for the automatic wiring device are formed only in the first and third layers. After the creation 704 of the signal pin at the via stack position, the output 705 of the correspondence information between the wiring information and the netlist after the automatic wiring, and the addition 706 of the signal pin connection node in the netlist
I do. The addition of the signal pin connection node 706 in the netlist searches the position of the via stack from the wiring information after automatic wiring and the corresponding data of the netlist, and adds the signal pin connection node This is achieved by adding a description. After the addition of the signal pin connection node 706 in the netlist is completed, additional input of the correspondence information between the wiring information after automatic wiring and the netlist 7
07, and additional wiring 708 is performed by the automatic wiring device based on the additional input data. The additional wiring 708 by the automatic wiring device enables the wiring of the second layer at the position of the via stack, and when the output 709 of the CAD data is performed,
CAD data using the second layer at the via stack position is output. The second layer of the CAD data includes signal wiring,
Since there is an overlap between the second layer portion of the first component via, the second layer portion of the second component via, and the second layer portion of the component for wiring interlayer connection, in order to eliminate the overlap, the second layer portion of the via stack is removed. Processing 710 is performed.
The process 710 of the second layer in the via stack is realized by Steps 1 to 3 in FIG. 4 when there is no first component via or the second component via, and when there is the first component via or the second component via in FIG. This is realized by Steps 1 to 3 of Step 5. After the processing 710 of the second layer is completed, the mask data output 711 is performed, and the wiring in the semiconductor integrated circuit according to claim 4 of the present invention is completed.

FIG. 8 is a diagram showing an additional pin connection node in the netlist of the top cell, showing an embodiment of the fourth aspect of the present invention. In FIG. 8, reference numeral 801 denotes a part of a layout for automatic wiring of a top cell;
A logic block, 803 is a second logic block, 804 is an additional pin of the top cell, 805 is a netlist of the top cell, 806 is net data, 807 is node data, 8
08 denotes graphic data, and 809 denotes an additional pin connection node. As shown in FIG. 8, after adding an additional pin 804 of the top cell to a part 801 of the layout of the top cell, the OUT of the first logic block 802 is changed to the second logic block 803.
In order to wire the signals up to IN, the netlist 805 of the top cell after the additional pin connection node 809 is inserted
When the additional wiring of the automatic wiring device is performed according to the above, wiring is performed on the first layer and the third layer of the additional pin 804 of the top cell, respectively, and the second layer is used at the same position as the additional pin 804 of the top cell. . In the actual layout of the top cell, components for connecting the wiring layers are arranged at the positions of the additional pins 804 of the top cell, and when there is no first component via or second component via, FIG.
Steps 1 to 3 realize the signal wiring of the second layer different from the signals of the first via and the second via of the component for connecting between wiring layers, and realize the first component via or the second component via.
When there is a component via, the signal wiring of the second layer connected to the first via and the second via of the component for wiring interlayer connection is realized by steps 1 to 3 in FIG.

FIG. 9 is a diagram showing signal pins of a functional block used in an automatic wiring device according to a fifth embodiment of the present invention. Reference numeral 901 denotes a first layer portion, 902 denotes a third layer portion, 903 denotes a center of a signal pin, 904 denotes a second layer region, and 905 denotes a virtual via. In FIG. 9, the first via and the second via are arranged between the first layer portion 901 and the third layer portion 902 by restricting the stacking of the virtual via 905 with the first via and the second via. The first layer portion 901 and the third layer portion 9
02 is transmitted to the first layer portion 90 via the first via.
First, it is no longer connected to the third layer portion 902 via the second via. As for FIG. 9, claims 1 to 4
In this case, the present invention is applied to a case where wiring is performed by the second layer by limiting signals to signals different from those of the first via and the second via of the wiring interlayer connection component.

[0026]

As described above, in the semiconductor integrated circuit of the present invention, first, the signal pins of the function block can be connected to the wirings of the I-th layer and the (I + 2) -th layer, and the same as the signal pins. It becomes possible to wire a signal different from the signal pin by using the (I + 1) th layer at the position.

Second, the I-th layer and the (I + 2) -th signal are applied to the signal pins.
Layer wiring can be connected, and the same signal as the signal pin can be wired using the (I + 1) th layer at the same position as the signal pin.

Third, signal wiring becomes possible using the (I + 1) th layer at a position where the (I) th via and the (I + 1) th via are stacked other than the signal pins.

Fourth, additional automatic wiring of signals is enabled by using the (I + 1) th layer at a position where the (I) th via and the (I + 1) th via are stacked other than the signal pins.

Fifth, in the first to fourth wirings, the wiring of the (I + 1) th layer limited to signals different from those of the (I) th via and the (I + 1) th via of the component for wiring interlayer connection becomes possible.

According to the first to fifth aspects, the wiring layer located between the I-th layer and the I + 2-th layer can be formed by using the (I + 1) -th layer without bypassing the position where the (I) -th via and the (I + 1) -th via are stacked. Wiring by the automatic wiring device of the same or different signal as the signal of the I-th via and the (I + 1) -th via becomes possible,
Shortening of wiring time, improvement of wiring efficiency and high integration of a semiconductor integrated circuit having three or more wiring layers are realized.

[Brief description of the drawings]

FIG. 1 shows a semiconductor integrated circuit having three wiring layers.
FIG. 1 is a plan view and an elevation view of a component for connecting between wiring layers, showing an embodiment of claim 1 of the present invention.

FIG. 2 is a diagram showing signal pins of a functional block used in the automatic wiring device, according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a case where two different signals are wired using the structure of FIG. 1;

FIG. 4 shows a second embodiment of the present invention.
The figure which shows the wiring process of a layer.

FIG. 5 shows a second embodiment of the present invention.
The figure which shows the wiring process of a layer.

FIG. 6 is a diagram showing a wiring flow representing an embodiment of the third embodiment of the present invention.

FIG. 7 is a diagram showing a wiring flow, showing an embodiment according to claim 4 of the present invention.

FIG. 8 is a diagram showing an additional pin connection node in a netlist of a top cell, showing an embodiment of claim 4 of the present invention.

FIG. 9 is a diagram showing signal pins of a functional block used in an automatic wiring device according to a fifth embodiment of the present invention.

FIG. 10 is an elevational view when a first layer and a third layer are connected in three wiring layers using a conventional technique.

FIG. 11 is a plan view and an elevation view showing a first component via for connecting a first layer and a second layer according to the related art.

FIG. 12 is a plan view and an elevation view showing a second component via for connecting a second layer and a third layer according to the related art.

FIG. 13 is a diagram showing a case where a second layer is wired near a position where a first via and a second via are stacked;

[Explanation of symbols]

101: first layer portion 102: first via 103: second layer portion 104: second via 105: third layer portion 106: first in the definition data of the automatic wiring device Pin portion of one layer 107: Pin portion of third layer in definition data of the automatic wiring device 108: Component for connection between wiring layers 109: First via and second via 201 of component for connection between wiring layers ..First layer part 202... Third layer part 203... Center of signal pin 204... Second layer area 301. Layer of first via and second via 303... Second layer portion of component for wiring interlayer connection 304... First via and second via for wiring of first signal
Wiring of the first layer connected to the via 305... The first via and the second for the wiring of the first signal
Wiring of the third layer connected to the via 306... Wiring of the second layer of the second signal different from the first signal 401. Wiring of the second layer 402. Center position 501: Wiring of second layer 502: First component via 503: Second layer portion of first component via 504: Center position of first component via 601: Automatic wiring device 602: Extraction of via stack position 603: Replacement of components for wiring interlayer connection 604: Wiring using second layer at via stack position 605: CAD data output 606: Via Processing of second layer at stack position 607: Output of mask data 701: Wiring by automatic wiring device 702: Extraction of via stack position 703: Replacement of components for connection between wiring layers 704: Creation of signal pins at via stack positions 705: Output of wiring information and data corresponding to netlist after automatic wiring 706: Signal pins in netlist Addition of connection node 707: Additional input of wiring data after automatic wiring and corresponding data of netlist 708: Additional wiring by automatic wiring device 709: Output of CAD data 710: At via stack position Processing of second layer 711: Output of mask data 801: Part of layout for automatic wiring of top cell 802: First logical block 803: Second logical block 804: Top cell Additional pin 805: Top cell net list 806: Net data 807: Node data 808: graphic data 809: additional pin connection node 901: first layer portion 902: third layer portion 903: center of signal pin 904: second layer region 905 ..Virtual via 1001 first layer portion 1002 first via 1003 second layer portion 1004 second via 1005 third layer portion 1101 first layer portion 1102 1st via 1103 2nd layer portion 1201 2nd layer portion 1202 2nd via 1203 3rd layer portion 1301 Stacked by the structure of FIG. First
Vias and second vias 1302: First-layer wiring used for first signal 1303: Third-layer wiring used for first signal 1304: Used for second signal Second layer wiring

Claims (5)

[Claims] 1. A semiconductor having three or more wiring layers (hereinafter referred to as a first layer, a second layer,..., An N-th layer from the lower layer, and the first layer may not be a wiring layer). A wiring method for an integrated circuit, comprising: a contact hole (hereinafter referred to as an I-th via) formed in an I-th interlayer insulating film for insulating an I-th (I ≧ 1) layer and an I + 1-th layer; A contact hole (hereinafter, referred to as an (I + 1) th via) formed in an (I + 1) th interlayer insulating film for insulating an (I + 2) th layer is arranged at the same position, and the Ith via and the (I + 1) th via are finite in space. In this case, the wiring layer connection component formed by arranging the (I + 1) th layer so as to completely or partially surround it is arranged on a signal pin of an arbitrary functional block, and a component of the functional block used in the automatic wiring apparatus is arranged. In the definition data, the signal pins of the functional block Part I of components for wiring interlayer connection
For the (I + 1) th layer wired after the automatic wiring, the portion included in the (I + 1) th layer part of the wiring interlayer connection component is represented by the (I + 1) th layer of the wiring interlayer connection component. Removed along the layer portion, and the (I + 1)
A wiring method for a semiconductor integrated circuit, wherein the wiring method is replaced with a layer portion. 2. The wiring method for a semiconductor integrated circuit according to claim 1, wherein a component having a sandwich structure including the I-th layer, the I-th via, and the I + 1-th layer after automatic wiring at a position of a signal pin of the functional block. In the case where components having a sandwich structure composed of an (I + 1) th component via, an (I + 1) th layer, the (I + 1) th via, and an (I + 2) th layer (hereinafter, referred to as an (I + 1) th component via) are disposed, the wiring interlayer connection is performed. The component included in the (I + 1) th layer portion of the component for wiring connection is not deleted along the (I + 1) th layer portion of the component for connection between wiring layers, and the component via for the Ith component via is added to the (I + 1) th layer portion of the component for wiring interlayer connection. Layer I + 1,
Alternatively, a wiring method for a semiconductor integrated circuit, wherein the (I + 1) th layer via of the (I + 1) th component via overlaps. 3. The wiring method for a semiconductor integrated circuit according to claim 1, wherein said I-component via and said I +
When one component via is placed at the same position,
A wiring method for a semiconductor integrated circuit, wherein one set of the I-th component via and the (I + 1) -th component via is replaced with the wiring interlayer connection component. 4. The method for wiring a semiconductor integrated circuit according to claim 3, wherein the definition data of the top cell used in the automatic wiring device includes:
4. The wiring layer connection component replaced with a set of the I-th component via and the (I + 1) -th component via according to claim 3, wherein a portion of the I-th layer and the (I + 2) -th layer is assigned to an arbitrary signal pin. A node connected to the I-th layer portion of the I-th component via and a node connected to the I-th layer portion of the I + 1-th component via are added to a net connected to the I + 1-th component via, and additional automatic wiring is performed. A wiring method for a semiconductor integrated circuit. 5. The wiring method for a semiconductor integrated circuit according to claim 1, wherein a virtual via is arranged at a position of the wiring interlayer connection component in the definition data of the top cell used in the automatic wiring device, Arrangement of vias at the same position between the virtual via and the I-th via and between the virtual via and the I + 1-th via (hereinafter, referred to as a stack)
A wiring method for a semiconductor integrated circuit, wherein a constraint is imposed to prohibit the wiring.