[go: up one dir, main page]

JPH1126806A - Photo coupler type semiconductor relay - Google Patents

Photo coupler type semiconductor relay

Info

Publication number
JPH1126806A
JPH1126806A JP17430897A JP17430897A JPH1126806A JP H1126806 A JPH1126806 A JP H1126806A JP 17430897 A JP17430897 A JP 17430897A JP 17430897 A JP17430897 A JP 17430897A JP H1126806 A JPH1126806 A JP H1126806A
Authority
JP
Japan
Prior art keywords
electrically connected
relay
light
ldmosfet
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17430897A
Other languages
Japanese (ja)
Inventor
Masamichi Takano
仁路 高野
Masahiko Suzumura
正彦 鈴村
Yuji Suzuki
裕二 鈴木
Yoshiki Hayazaki
嘉城 早崎
Yoshifumi Shirai
良史 白井
Takashi Kishida
貴司 岸田
Takeshi Yoshida
岳司 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP17430897A priority Critical patent/JPH1126806A/en
Publication of JPH1126806A publication Critical patent/JPH1126806A/en
Pending legal-status Critical Current

Links

Landscapes

  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
  • Electronic Switches (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a photo coupler type semiconductor relay which never increases the output terminal capacitance at the time of the relay off. SOLUTION: A relay comprises a solar cell 1 to be a photo detector on a GND terminal frame 4 and LDMOSFETs 2, 3 each having an ISO structure on floating frames 5a, 5b electrically independent of the external potential in a resin package 8. The anodes 1a, 1b of the cell 1 are electrically connected to the gate electrodes 2a, 3a of the LDMOSFETs 2, 3 through bonding wires 6; a cathode 1c of the cell 1 and source electrodes 2b, 3b of the LDMOSFETs 2, 3 are electrically connected to the GND frame 4 through bonding wires 6, and the drain electrodes 2c, 3c of the LDMOSFETs 2, 3 are electrically connected to output terminal frames 7a, 7b through bonding wires 6.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、発光素子と受光素
子とを光結合し、受光素子の出力によってMOSFET
にスイッチング動作を行わせる光結合型半導体リレ−に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device and a light receiving device which are optically coupled to each other.
The present invention relates to an optically coupled semiconductor relay that causes a switching operation to be performed.

【0002】[0002]

【従来の技術】図2に示すように、従来の縦型MOSF
ETを出力用MOSFETとして用いたフォトモスリレ
−は、受光素子である太陽電池1がGND端子フレ−ム
4上に配設され、このGND端子フレ−ム4の両側に並
設された出力端子フレ−ム7a,7b上に縦型MOSF
ET9,10が配設されている。
2. Description of the Related Art As shown in FIG.
A photo-MOS relay using an ET as an output MOSFET is such that a solar cell 1 as a light receiving element is disposed on a GND terminal frame 4 and output terminal frames arranged side by side on both sides of the GND terminal frame 4. Vertical MOSF on the memory 7a, 7b
ETs 9 and 10 are provided.

【0003】また、図3に示すように、GND端子フレ
−ム4に対向して配置された入力端子フレ−ム12上に
は発光素子である発光ダイオ−ド11が配設され、太陽
電池1のアノ−ド1a,1bと縦型MOSFET9,1
0のゲ−ト電極9a,10aとは、それぞれボンディン
グワイヤ6により電気的に接続され、太陽電池1のカソ
−ド1c及び縦型MOSFET9,10のソ−ス電極9
b,10bは、ボンディングワイヤ6によりGND端子
フレ−ム4に電気的に接続されている。
[0003] As shown in FIG. 3, a light emitting diode 11 as a light emitting element is provided on an input terminal frame 12 arranged opposite to the GND terminal frame 4, and a solar cell is provided. 1 and the vertical MOSFETs 9, 1
The gate electrodes 9a and 10a of the solar cell 1 are electrically connected by bonding wires 6, respectively, and the cathode 1c of the solar cell 1 and the source electrodes 9 of the vertical MOSFETs 9 and 10 are connected.
b and 10b are electrically connected to the GND terminal frame 4 by bonding wires 6.

【0004】そして、全体を不透明な樹脂パッケ−ジ8
でモ−ルドして1パッケ−ジ化し、太陽電池1と発光ダ
イオ−ド11との間を透明なシリコン樹脂13からなる
導光路により光結合し、発光ダイオ−ド11からの光を
受光素子である太陽電池1で受光できるようになってい
る。
An opaque resin package 8 is formed as a whole.
To form a package, and optically couples the solar cell 1 and the light emitting diode 11 by a light guide path made of a transparent silicon resin 13, and receives light from the light emitting diode 11 as a light receiving element. The solar cell 1 can receive light.

【0005】このように構成されたフォトモスリレ−
は、発光ダイオ−ド11を外部駆動信号で発光させ、そ
の発光ダイオ−ド11からの光を受光した太陽電池1は
電圧を発生し、この電圧が一定レベルに達すると出力用
の縦型MOSFET9,10がスイッチングし、フォト
モスリレ−がオン、またはオフする。
[0005] The photo mosley relay constructed as described above.
The light emitting diode 11 emits light by an external drive signal, and the solar cell 1 receiving the light from the light emitting diode 11 generates a voltage. When the voltage reaches a certain level, the output vertical MOSFET 9 is turned on. , 10 are switched, and the photo MOS relay is turned on or off.

【0006】また、上述のようなフォトモスリレ−にお
いては、出力端子フレ−ム7a,7bの間に負荷をかけ
る場合と、一方の出力端子フレ−ム7a,7bとGND
端子フレ−ム4との間に負荷をかける場合とで、交流電
流用途と直流電流用途とに使い分けることが可能であ
る。
In the above-mentioned photo mosley relay, a load is applied between the output terminal frames 7a and 7b, and one of the output terminal frames 7a and 7b is connected to GND.
When a load is applied between the terminal frame 4 and the terminal frame 4, it can be selectively used for AC current application and DC current application.

【0007】ところで、このようなフォトモスリレ−に
おいて、リレ−の出力端子間容量は、リレ−オフ時の絶
縁特性に関わる重要な特性である。出力端子間容量は、
出力用MOSFETの特性によって決まり、出力端子間
容量が小さいほど、リレ−の高周波絶縁性は大きくな
る。
Incidentally, in such a photomos relay, the capacitance between the output terminals of the relay is an important characteristic related to the insulation characteristics when the relay is off. The capacitance between output terminals is
Determined by the characteristics of the output MOSFET, the smaller the capacitance between the output terminals, the greater the high-frequency insulation of the relay.

【0008】近年、リレ−オフ時の出力容量低減化を目
的として、出力用MOSFETとして縦型MOSFET
9,10の代わりに、SOI(Silicon on Insulato
r)構造を有する横型2重拡散MOS電解効果トランジ
スタ、いわゆるLDMOSFET(Lateral Double D
iffused MOSFET)が用いられている。
In recent years, a vertical MOSFET has been used as an output MOSFET for the purpose of reducing the output capacitance at the time of relay-off.
Instead of 9 and 10, SOI (Silicon on Insulato)
r) Lateral double diffusion MOS field effect transistor having a structure, so-called LDMOSFET (Lateral Double D)
iffused MOSFET).

【0009】これは、MOSFETの出力容量は、ドレ
イン・ソ−ス関容量Cds、ゲ−ト・ドレイン間容量Cgd
の和で表され、SOI構造を有するLDMOSFETは
縦型MOSFETに比べ、ドレイン・ソ−ス間容量Cds
を大幅に小さくできるからである。
This is because the output capacitance of the MOSFET is a drain-source capacitance Cds, a gate-drain capacitance Cgd.
The LDMOSFET having the SOI structure is compared with the vertical MOSFET in that the drain-source capacitance Cds
Is significantly reduced.

【0010】図4に示すように、SOI構造を有するL
DMOSFET2,3を出力用MOSFETとして用い
たフォトモスリレ−は、出力用MOSFETとして縦型
MOSFET9,10を用いた場合と同様、受光素子で
ある太陽電池1がGND端子フレ−ム4上に配設され、
このGND端子フレ−ム4の両側に並設された出力端子
フレ−ム7a,7b上にLDMOSFET2,3が配設
されている。そして、太陽電池1のアノ−ド1a,1b
とLDMOSFET2,3のゲ−ト電極2a,3aと
は、それぞれボンディングワイヤ6により電気的に接続
され、太陽電池1のカソ−ド1c及びLDMOSFET
2,3のソ−ス電極2b,3bは、ボンディングワイヤ
6によりGND端子フレ−ム4に電気的に接続され、L
DMOSFET2,3のドレイン電極2c,3cは出力
端子フレ−ム7a,7bにボンディングワイヤ6により
電気的に接続されている。
As shown in FIG. 4, L having an SOI structure
In a photo-MOS relay using DMOSFETs 2 and 3 as output MOSFETs, a solar cell 1 which is a light receiving element is disposed on a GND terminal frame 4 in the same manner as when vertical MOSFETs 9 and 10 are used as output MOSFETs.
LDMOSFETs 2 and 3 are arranged on output terminal frames 7a and 7b arranged on both sides of the GND terminal frame 4, respectively. Then, the anodes 1a and 1b of the solar cell 1
And the gate electrodes 2a and 3a of the LDMOSFETs 2 and 3 are electrically connected by bonding wires 6, respectively.
A few source electrodes 2b and 3b are electrically connected to a GND terminal frame 4 by bonding wires 6,
The drain electrodes 2c and 3c of the DMOSFETs 2 and 3 are electrically connected to output terminal frames 7a and 7b by bonding wires 6.

【0011】[0011]

【発明が解決しようとする課題】ところが、SOI構造
を有するLDMOSFET2,3を出力用MOSFET
として用いた場合においては、出力用MOSFETが出
力端子フレ−ム7a,7b上に配設されていると、リレ
−オフ時の出力端子間容量の増加を引き起こしてしまう
という問題が発生する。
However, the LDMOSFETs 2 and 3 having the SOI structure are replaced with output MOSFETs.
When the output MOSFET is provided on the output terminal frames 7a and 7b, there arises a problem that the capacitance between the output terminals at the time of relay-off is increased.

【0012】つまり、LDMOSFET2,3におい
て、リレ−オフ時の出力端子間容量は、通常、ドレイン
・ソ−ス間容量Cdsとゲ−ト・ドレイン間容量Cgdの和
であるが、図4に示すような実装状態において出力端子
フレ−ム7a,7bの電位が上がった場合には、図5に
示すように、LDMOSFET2,3の支持基板14a
がドレインの電位まで上昇するので、埋込酸化膜14b
を介してゲ−ト・支持基板間容量Cgsubとソ−ス・支持
基板間容量Cssubが発生する。
That is, in the LDMOSFETs 2 and 3, the capacitance between the output terminals when the relay is turned off is usually the sum of the capacitance Cds between the drain and the source and the capacitance Cgd between the gate and the drain, as shown in FIG. When the potential of the output terminal frames 7a, 7b rises in such a mounting state, as shown in FIG.
Rises to the potential of the drain, the buried oxide film 14b
A capacitance Cgsub between the gate and the supporting substrate and a capacitance Cssub between the source and the supporting substrate are generated through the gate.

【0013】その結果、図6に示すように、通常のドレ
イン・ソ−ス間容量Cds,ゲ−ト・ドレイン間容量Cgd
に加え、ゲ−ト・支持基板間容量Cgsub,ソ−ス・支持
基板間容量Cssubが並列に重畳されるため、出力端子間
容量の増加を引き起こしてしまうことになる。
As a result, as shown in FIG. 6, a normal drain-source capacitance Cds and a gate-drain capacitance Cgd are obtained.
In addition, since the capacitance Cgsub between the gate and the supporting substrate and the capacitance Cssub between the source and the supporting substrate are superposed in parallel, the capacitance between the output terminals is increased.

【0014】本発明は、上記の点に鑑みて成されたもの
であり、その目的とするところは、リレ−オフ時の出力
端子間容量の増加を引き起こすことのない光結合型半導
体リレ−を提供することにある。
The present invention has been made in view of the above points, and an object of the present invention is to provide an optically coupled semiconductor relay which does not cause an increase in capacitance between output terminals when the relay is turned off. To provide.

【0015】[0015]

【課題を解決するための手段】請求項1記載の発明は、
入力側の信号に応答して発光する発光素子と、該発光素
子からの光信号を受けて光起電力を発生する受光素子
と、該受光素子の光起電力に呼応してオン/オフする出
力開閉素子とから成る光結合型半導体リレ−において、
前記出力開閉素子としてSOI構造を有するLDMOS
FETを用い、前記受光素子はGND端子フレ−ム上に
配設され、前記LDMOSFETは電気的に浮遊状態で
外部電位に依存しないフロ−ティングフレ−ム上に配設
され、前記受光素子のアノ−ドと前記LDMOSFET
のゲ−ト電極とが電気的に接続され、前記受光素子のカ
ソ−ド及び前記LDMOSFETのソ−ス電極が前記G
ND端子フレ−ムに電気的に接続され、前記LDMOS
FETのドレイン電極が出力端子フレ−ムに電気的に接
続されて成ることを特徴とするものである。
According to the first aspect of the present invention,
A light-emitting element that emits light in response to a signal on the input side, a light-receiving element that generates a photovoltaic power by receiving an optical signal from the light-emitting element, and an output that is turned on / off in response to the photovoltaic power of the light-receiving element In an optical coupling type semiconductor relay comprising a switching element,
LDMOS having SOI structure as output switching element
Using an FET, the light receiving element is disposed on a GND terminal frame, the LDMOSFET is disposed in an electrically floating state on a floating frame that does not depend on an external potential, and the light receiving element is anodized. And the LDMOSFET
Are electrically connected to each other, and the cathode of the light receiving element and the source electrode of the LDMOSFET are connected to the G electrode.
The LDMOS is electrically connected to an ND terminal frame.
The drain electrode of the FET is electrically connected to the output terminal frame.

【0016】[0016]

【発明の実施の形態】以下、本発明の一実施形態につい
て図面に基づき説明する。図1は、本発明の一実施形態
に係るSOI構造を有するLDMOSFET2,3を出
力用MOSFETとして用いたフォトモスリレ−の実装
状態を示す略平面図である。本実施形態に係るフォトモ
スリレ−は、受光素子である太陽電池1がGND端子フ
レ−ム4上に配設され、樹脂パッケ−ジ8内に収納さ
れ、電気的に外部電位に依存しない浮遊状態のフロ−テ
ィングフレ−ム5a,5b上に、SOI構造を有するL
DMOSFET2,3が配設されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic plan view showing a mounted state of a photo MOSFET using LDMOSFETs 2 and 3 having an SOI structure as output MOSFETs according to an embodiment of the present invention. In the photo-MOS relay according to the present embodiment, a solar cell 1 as a light receiving element is disposed on a GND terminal frame 4 and housed in a resin package 8 so that the solar cell 1 is in a floating state that does not depend on an external potential electrically. L having an SOI structure is provided on the floating frames 5a and 5b.
DMOSFETs 2 and 3 are provided.

【0017】また、太陽電池1のアノ−ド1a,1bと
LDMOSFET2,3のゲ−ト電極2a,3aとがボ
ンディングワイヤ6により電気的に接続され、太陽電池
1のカソ−ド1c及びLDMOSFET2,3のソ−ス
電極2b,3bとがボンディングワイヤ6によりGND
端子フレ−ム4に電気的に接続され、LDMOSFET
2,3のドレイン電極2c,3cは出力端子フレ−ム7
a,7bにそれぞれボンディングワイヤ6により電気的
に接続されている。
The anodes 1a and 1b of the solar cell 1 are electrically connected to the gate electrodes 2a and 3a of the LDMOSFETs 2 and 3 by bonding wires 6, and the cathode 1c and the LDMOSFET 2 of the solar cell 1 are connected. 3 is connected to the source electrode 2b, 3b by the bonding wire 6.
LDMOSFET electrically connected to terminal frame 4
A few drain electrodes 2c and 3c are output terminal frames 7
a and 7b are electrically connected by bonding wires 6, respectively.

【0018】従って、本実施形態においては、LDMO
SFET2,3のソ−ス電極2b,3bがフロ−ティン
グフレ−ム5a,5bを介さずにGND端子フレ−ム4
に接続されているので、フロ−ティングフレ−ム5a,
5bは、外部電位にもLDMOSFET2,3のソ−ス
電極2b,3bの電位にも依存しない。このため、LD
MOSFET2,3の支持基板に起因する寄生容量成分
が発生せず、出力端子間容量は低減化される。
Therefore, in this embodiment, the LDMO
The source electrodes 2b, 3b of the SFETs 2, 3 are connected to the GND terminal frame 4 without passing through the floating frames 5a, 5b.
Connected to the floating frame 5a,
5b does not depend on the external potential or the potentials of the source electrodes 2b and 3b of the LDMOSFETs 2 and 3. For this reason, LD
No parasitic capacitance component is generated due to the support substrates of the MOSFETs 2 and 3, and the capacitance between the output terminals is reduced.

【0019】なお、本実施形態においては、GND端子
フレ−ム4を介してLDMOSFET2,3のソ−ス電
極2b,3bと太陽電池1のカソ−ド1cとを接続する
ようにしたので、出力端子フレ−ム7a,7b間に負荷
をかける交流電流用途だけでなく、出力端子フレ−ム7
a,7bとGND端子フレ−ム4との間に負荷をかける
直流電流用途にも使用できる。
In this embodiment, since the source electrodes 2b and 3b of the LDMOSFETs 2 and 3 and the cathode 1c of the solar cell 1 are connected via the GND terminal frame 4, the output is In addition to the use of alternating current for applying a load between the terminal frames 7a and 7b, the output terminal frame 7
It can also be used for direct current application in which a load is applied between a, 7b and the GND terminal frame 4.

【0020】また、本実施形態においては、LDMOS
FET2,3として図5に示すようなn型MOSFET
を用いたが、これに限定される必要はなく、p型MOS
FETを用いても良い。
In this embodiment, the LDMOS
N-type MOSFET as shown in FIG.
However, the present invention is not limited to this.
An FET may be used.

【0021】更に、本実施形態においては、出力開閉素
子としてSOI構造を有するLDMOSFET2,3を
用いたが、これに限定される必要はなく、SOI構造を
有するJFET,IGBT,UMOSFET,バイポ−
ラトランジスタでも良く、また、エピ基板上に形成され
たLDMOSFET,JFET,IGBT,UMOSF
ETでも良く、また、バルク基板上に形成されたLDM
OSFET,JFET,IGBT,UMOSFETでも
良い。
Further, in this embodiment, the LDMOSFETs 2 and 3 having the SOI structure are used as the output switching elements. However, the present invention is not limited to this, and JFETs, IGBTs, UMOSFETs, and bipolars having the SOI structure are used.
Transistor, or an LDMOSFET, JFET, IGBT, UMOSF formed on an epi-substrate.
ET may be used, and LDM formed on bulk substrate
OSFET, JFET, IGBT, UMOSFET may be used.

【0022】[0022]

【発明の効果】請求項1記載の発明は、入力側の信号に
応答して発光する発光素子と、発光素子からの光信号を
受けて光起電力を発生する受光素子と、受光素子の光起
電力に呼応してオン/オフする出力開閉素子とから成る
光結合型半導体リレ−において、出力開閉素子としてS
OI構造を有するLDMOSFETを用い、受光素子は
GND端子フレ−ム上に配設され、LDMOSFETは
電気的に浮遊状態で外部電位に依存しないフロ−ティン
グフレ−ム上に配設され、受光素子のアノ−ドとLDM
OSFETのゲ−ト電極とが電気的に接続され、受光素
子のカソ−ド及びLDMOSFETのソ−ス電極がGN
D端子フレ−ムに電気的に接続され、LDMOSFET
のドレイン電極が出力端子フレ−ムに電気的に接続され
て成るので、LDMOSFETの支持基板に起因する寄
生容量成分が発生せず、リレ−オフ時の出力端子間容量
の増加を引き起こすことのない光結合型半導体リレ−を
提供することができた。
According to the first aspect of the present invention, there is provided a light emitting element which emits light in response to a signal on the input side, a light receiving element which generates a photoelectromotive force by receiving an optical signal from the light emitting element, and a light receiving element for receiving light. In an optically coupled semiconductor relay comprising an output switching element which is turned on / off in response to an electromotive force, S
An LDMOSFET having an OI structure is used. The light receiving element is disposed on a GND terminal frame. The LDMOSFET is disposed in an electrically floating state on a floating frame which does not depend on an external potential. Anode and LDM
The gate electrode of the OSFET is electrically connected, and the cathode of the light receiving element and the source electrode of the LDMOSFET are GN.
LDMOSFET electrically connected to the D terminal frame
Since the drain electrode is electrically connected to the output terminal frame, no parasitic capacitance component due to the supporting substrate of the LDMOSFET is generated, and the capacitance between the output terminals at the time of relay off does not increase. An optically coupled semiconductor relay can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態に係るSOI構造を有する
LDMOSFETを出力用MOSFETとして用いたフ
ォトモスリレ−の実装状態を示す略平面図である。
FIG. 1 is a schematic plan view showing a mounted state of a photo MOSFET using an LDMOSFET having an SOI structure according to an embodiment of the present invention as an output MOSFET.

【図2】従来例に係る縦型MOSFETを出力用MOS
FETとして用いたフォトモスリレ−の実装状態を示す
略平面図である。
FIG. 2 shows a conventional vertical MOSFET connected to an output MOS.
FIG. 5 is a schematic plan view showing a mounted state of a photomoss relay used as an FET.

【図3】従来例に係るフォトモスリレ−の概略構成図で
ある。
FIG. 3 is a schematic configuration diagram of a photo mosley relay according to a conventional example.

【図4】従来例に係るSOI構造を有するLDMOSF
ETを出力用MOSFETとして用いたフォトモスリレ
−の実装状態を示す略平面図である。
FIG. 4 shows a conventional LDMOSF having an SOI structure.
FIG. 11 is a schematic plan view showing a mounting state of a photo-mosley relay using ET as an output MOSFET.

【図5】従来例に係るフォトモスリレ−のLDMOSF
ETの略断面図である。
FIG. 5 shows a conventional photo MOS relay LDMOSF.
It is a schematic sectional drawing of ET.

【図6】従来例に係るフォトモスリレ−のLDMOSF
ETの出力端子間容量の等価回路図である。
FIG. 6 is a photoMOS relay LDMOSF according to a conventional example.
It is an equivalent circuit diagram of the capacitance between output terminals of ET.

【符号の説明】[Explanation of symbols]

1 太陽電池 1a,1b アノ−ド 1c カソ−ド 2,3 LDMOSFET 2a,3a ゲ−ト電極 2b,3b ソ−ス電極 2c,3c ドレイン電極 4 GND端子フレ−ム 5a,5b フロ−ティングフレ−ム 6 ボンディングワイヤ 7a,7b 出力端子フレ−ム 8 樹脂パッケ−ジ 9,10 縦型MOSFET 9a,10a ゲ−ト電極 9b,10b ソ−ス電極 11 発光ダイオ−ド 12 入力端子フレ−ム 13 シリコン樹脂 14a 支持基板 14b 埋込酸化膜 14c SOI層 15 p型ウェル領域 16 n+型ドレイン領域 17 n+型ソ−ス領域 DESCRIPTION OF SYMBOLS 1 Solar cell 1a, 1b Anode 1c Cathode 2, 3 LDMOSFET 2a, 3a Gate electrode 2b, 3b Source electrode 2c, 3c Drain electrode 4 GND terminal frame 5a, 5b Floating frame 6 Bonding wire 7a, 7b Output terminal frame 8 Resin package 9, 10 Vertical MOSFET 9a, 10a Gate electrode 9b, 10b Source electrode 11 Light emitting diode 12 Input terminal frame 13 Silicon Resin 14a Support substrate 14b Buried oxide film 14c SOI layer 15 p-type well region 16 n + -type drain region 17 n + -type source region

───────────────────────────────────────────────────── フロントページの続き (72)発明者 早崎 嘉城 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 白井 良史 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 岸田 貴司 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 吉田 岳司 大阪府門真市大字門真1048番地松下電工株 式会社内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshiki Hayasaki 1048 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Works, Ltd. (72) Inventor Takashi Kishida 1048 Kazuma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Works Co., Ltd. (72) Inventor Takeshi Yoshida 1048 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Works, Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 入力側の信号に応答して発光する発光素
子と、該発光素子からの光信号を受けて光起電力を発生
する受光素子と、該受光素子の光起電力に呼応してオン
/オフする出力開閉素子とから成る光結合型半導体リレ
−において、前記出力開閉素子としてSOI構造を有す
るLDMOSFETを用い、前記受光素子はGND端子
フレ−ム上に配設され、前記LDMOSFETは電気的
に浮遊状態で外部電位に依存しないフロ−ティングフレ
−ム上に配設され、前記受光素子のアノ−ドと前記LD
MOSFETのゲ−ト電極とが電気的に接続され、前記
受光素子のカソ−ド及び前記LDMOSFETのソ−ス
電極が前記GND端子フレ−ムに電気的に接続され、前
記LDMOSFETのドレイン電極が出力端子フレ−ム
に電気的に接続されて成ることを特徴とする光結合型半
導体リレ−。
1. A light-emitting element that emits light in response to a signal on an input side, a light-receiving element that generates a photoelectromotive force by receiving an optical signal from the light-emitting element, and In an optically coupled semiconductor relay comprising an ON / OFF switching element, an LDMOSFET having an SOI structure is used as the output switching element, and the light receiving element is disposed on a GND terminal frame, and the LDMOSFET is electrically operated. A floating state, which is disposed on a floating frame which does not depend on an external potential, and is connected to the anode of the light receiving element and the LD.
The gate electrode of the MOSFET is electrically connected, the cathode of the light receiving element and the source electrode of the LDMOSFET are electrically connected to the GND terminal frame, and the drain electrode of the LDMOSFET is output. An optically coupled semiconductor relay, which is electrically connected to a terminal frame.
JP17430897A 1997-06-30 1997-06-30 Photo coupler type semiconductor relay Pending JPH1126806A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17430897A JPH1126806A (en) 1997-06-30 1997-06-30 Photo coupler type semiconductor relay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17430897A JPH1126806A (en) 1997-06-30 1997-06-30 Photo coupler type semiconductor relay

Publications (1)

Publication Number Publication Date
JPH1126806A true JPH1126806A (en) 1999-01-29

Family

ID=15976394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17430897A Pending JPH1126806A (en) 1997-06-30 1997-06-30 Photo coupler type semiconductor relay

Country Status (1)

Country Link
JP (1) JPH1126806A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8901585B2 (en) 2003-05-01 2014-12-02 Cree, Inc. Multiple component solid state white light
JP2023044950A (en) * 2021-09-21 2023-04-03 株式会社東芝 Semiconductor device
JP2024125324A (en) * 2021-02-18 2024-09-18 株式会社東芝 Semiconductor Device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8901585B2 (en) 2003-05-01 2014-12-02 Cree, Inc. Multiple component solid state white light
JP2024125324A (en) * 2021-02-18 2024-09-18 株式会社東芝 Semiconductor Device
JP2023044950A (en) * 2021-09-21 2023-04-03 株式会社東芝 Semiconductor device
US12094862B2 (en) 2021-09-21 2024-09-17 Kabushiki Kaisha Toshiba Semiconductor device

Similar Documents

Publication Publication Date Title
CN1156978C (en) Solid-state relay
US8803161B2 (en) Semiconductor device and solid state relay using same
US8022477B2 (en) Semiconductor apparatus having lateral type MIS transistor
JP2005528804A (en) Trench gate semiconductor device
CN107800281A (en) Boostrap circuit and drive circuit for high voltage half-bridge gate drive circuit
US6441654B1 (en) Inductive load driving circuit
US7968943B2 (en) Semiconductor device reducing output capacitance due to parasitic capacitance
JPH1126806A (en) Photo coupler type semiconductor relay
JP3468033B2 (en) Optically coupled semiconductor relay
KR960006107B1 (en) Low output capacitance, double-diffused field effect transistor
JPH1154787A (en) Optically coupled semiconductor relay
JPH1126805A (en) Photo coupler type semiconductor relay
JP3513851B2 (en) Semiconductor device
JP3319999B2 (en) Semiconductor switch element
JPH03147378A (en) solid state relay
JP2943922B2 (en) Output contact element for semiconductor relay
JP3282571B2 (en) Semiconductor device
JP2740435B2 (en) Solid state relay
JP3562282B2 (en) Semiconductor device
JP2006093684A (en) Semiconductor device and optical semiconductor relay device using it
JP4988707B2 (en) MOSFET device for controlling a MOSFET device
JPH11220133A (en) Semiconductor device
JPH11191627A (en) Semiconductor device
JPH04107865A (en) Semiconductor device
JPH11186559A (en) Semiconductor device