JPH1126740A - Solid-state imaging device - Google Patents

Abstract

[PROBLEMS] To provide a solid-state imaging device capable of reducing a power supply voltage input to an amplification type MOS solid-state imaging device, preventing an afterimage, and obtaining an imaging output with a high conversion gain. SOLUTION: A photodiode PD formed on a semiconductor substrate, an amplification transistor Amp for inputting a signal of the photodiode PD to a gate, address means for activating the amplification transistor Amp, and a signal of the photodiode PD A unit cell 1 having at least a reset transistor R to be discharged is provided, and a booster circuit 7 is mounted in the same chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a solid-state imaging device, and more particularly to an amplification type MOS solid-state imaging device.

[0002]

2. Description of the Related Art FIG. 6 is a schematic diagram showing a circuit arrangement of a conventional amplification type MOS solid-state imaging device. In FIG. 6, a portion surrounded by a dotted line indicates one cell 1. Generally, a plurality of cells 1 are arranged in a two-dimensional matrix to form a cell array 2. Photoelectrons generated by photoelectric conversion in the photodiode PD are sent to the detection unit DN through the transfer transistor T. Since the detection unit DN is connected to the gate of the amplification transistor Amp, the gate voltage of the amplification transistor Amp is modulated by the number of photoelectrons. The amplification transistor Amp forms a source follower circuit together with the load transistor Load provided above or below the cell 1 part, and a voltage corresponding to the gate potential of the amplification transistor Amp appears on the vertical signal line Sig. Thus, it is possible to know the magnitude of the light that has entered the photodiode PD through the voltage of the vertical signal line Sig. The power supply voltage Vdd is applied to the drain D.

An address transistor Ad is included to select a row. When the photoelectrons of the detection unit DN are discharged to the drain D through the reset transistor R, the detection unit D
N is reset. One of the advantages of the MOS solid-state imaging device over the CCD solid-state imaging device is ground (Vss =
0V) and the power supply voltage Vdd. The three wires of the address, reset, and transfer gates extending in the horizontal direction are set to 0 V (= V) by the vertical shift register 3 provided on the left or right side or both of the cell 1 part.
ss) and the power supply voltage Vdd. In some cases, a noise canceller circuit 5 is mounted to compensate for variations in characteristics between the cells 1. The output voltage of the cell 1 is sequentially read out to the horizontal signal line by the horizontal shift register 4,
The signal is output from the solid-state imaging device through the output amplifier 6.

One of the features of the amplification type MOS solid-state imaging device is that it can be driven at a lower voltage than a CCD solid-state imaging device which is currently mainstream. CCD requires a high voltage of, for example, 15 V, but an amplification type MO
The S-type solid-state imaging device operates at a voltage of, for example, 5V. However, if a power supply voltage common to other systems such as a memory and a logic is required in the future, it is expected that further measures for lowering the voltage will be required. The points that become obstacles in that case will be described below.

FIG. 7 is a potential diagram conceptually showing the operation of the conventional cell 1. In FIG. From the left, a photodiode PD,
Transfer transistor T, detection unit DN, reset transistor R, drain D, amplification transistor Amp, diffusion layer F shared by amplification transistor Amp and address transistor Ad, address transistor Ad, vertical signal line Sig, load transistor Load, ground Vss It is drawn in order. The downward direction is the positive potential direction. The photodiode PD and a place where electrons transferred from the photodiode PD accumulate are indicated by oblique lines. Vertical signal line potential Vsi
g is determined as follows. When the detection unit DN is reset, its potential substantially matches the channel potential Vch (R) when the reset transistor R is turned on. When the reset transistor R is turned on, the gate voltage is Vdd, so that Vch (R) is determined by the threshold voltage drop of the reset transistor R from Vdd. When photoelectrons of the photodiode PD are introduced into the detection unit DN through the transfer transistor T, the potential of the detection unit DN changes to a minus side by an amount indicated by oblique lines. Since the gate of the amplification transistor Amp is connected to the detection unit DN, its gate voltage is equal to the voltage of the detection unit DN, and its channel voltage is the amplification transistor A from the voltage of the detection unit DN.
It is determined by the threshold drop of mp. The potential of the diffusion layer F corresponding to the source voltage further increases the potential of the amplifying transistor Amp.
It is reduced by N resistance. When the cell 1 is selected, since the power supply voltage Vdd is applied to the gate of the address transistor Ad, the voltage Vsig which is lower than the potential of the diffusion layer F by the ON resistance of the address transistor Ad is applied to the vertical signal line Sig. appear. This voltage Vs
Although ig is the output of the cell 1, when Vsig becomes smaller than the channel voltage Vch (load) of the load transistor Load, that is, when Vsig comes to the upper side in FIG. 7, the linearity of the output is impaired. Here, Vch (lo
ad) is a potential higher than Vss by the ON resistance of the load transistor Load. In this way, the sum of the ON resistance of the three transistors, the drop in the threshold voltage of the two transistors, and the change due to the signal electrons is represented by the power supply voltage Vd.
d or less. Conversely, amplified MO
The power supply voltage input to the S-type solid-state imaging device cannot be reduced to a voltage lower than the sum of the ON resistances of the three transistors, the threshold drop of the two transistors, and the change due to the signal electrons. For this purpose, for example, 3.3V
Alternatively, with a power supply voltage of 1.5 V or less, it is difficult to sufficiently secure the operation margin of the cell 1 in consideration of the variation of each transistor.

Further, this operation has the following disadvantages in characteristics. FIG. 8 is a potential diagram drawn in the order of the photodiode PD, the transfer transistor T, the detection unit DN, the reset transistor R, and the drain D from the left.

FIG. 8A shows a state after resetting the electrons of the detection unit DN. The transfer transistor T and the reset transistor R are turned off by inputting 0 V to the gate voltage, and the potential of the detection unit DN is reset transistor. It is almost equal to the channel voltage Vch (R) when the power supply voltage Vdd is inserted into the gate of R and turned on.

[0008] Photoelectrons accumulate in the photodiode PD as indicated by oblique lines. Next, when the transfer transistor T is turned on, the state shown in FIG. At this time, some of the electrons of the photodiode PD flow into the detection unit DN, and the potentials of the photodiode PD and the detection unit DN become equal. Next, when the transfer transistor T is turned off, FIG.
The state shown in FIG. At this time, electrons existing in the channel of the transfer transistor T are distributed to the photodiode PD and the detection unit DN, and the photodiode PD and the detection unit DN
Are electrically separated. In this state, the optical signal is read out to the vertical signal line Sig.

If the power supply voltage is applied to the gate voltage of the reset transistor R before the next signal is read out and the reset transistor R is turned on, the signal electrons of the detection section DN are discarded to the drain, and the state shown in FIG. The reset transistor R is turned off to return to the state shown in FIG. In this operation, photoelectrons are transferred to the photodiode P in FIG.
Since all of the data cannot be transferred from D to the detection unit DN,
Unless the photodiode PD is reset, photoelectrons remain in the photodiode PD, and an afterimage is generated when a signal is read out from the next time. This problem does not occur when the photodiode PD is completely depleted at a low potential and can transfer electrons completely, as in the case of a CCD. However, in a MOS type solid-state imaging device, since the transistor exists in the cell 1, its operation is guaranteed. Therefore, it is necessary to increase the well concentration, so that the photodiode P is completely depleted.
Fabrication of D is very difficult. Further, since the photoelectrons are distributed between the photodiode PD and the detection unit DN, the conversion gain (the signal amplitude per photoelectron) decreases.

[0010]

As described above, in the amplifying MOS type solid-state imaging device, the threshold value of the transistor and O
It was impossible to operate with a power supply voltage lower than the value determined by the N resistance. Further, the signal electrons of the photodiode PD could not be completely transferred, resulting in an afterimage. Also, the conversion gain was small.

According to the present invention, a power supply voltage input to an amplification type MOS solid-state imaging device is reduced, and an afterimage is prevented.
It is an object to provide a solid-state imaging device that obtains an imaging output with a high conversion gain.

[0012]

According to the present invention, the following means have been taken in order to solve the above-mentioned problems. In the present invention,
The amplification type MOS solid-state imaging device is characterized in that the boosting circuit 7 is mounted on the solid-state imaging device (within the same chip).

The output of the booster circuit 7 is input to the gate wiring of the reset transistor R of the cell 1. Alternatively, the signal is input to the gate wiring of the address transistor Ad of cell 1 at the same time.

The value of the boosted voltage input to the gate wiring of the reset transistor R is set in a range where the reset transistor R operates in a linear region. The gate voltage when the transfer transistor T is turned on is made lower than the gate voltage when the reset transistor R is turned on, regardless of whether the booster circuit 7 is mounted. Alternatively, the threshold value of the transfer transistor T is set higher than the threshold value of the reset transistor R.

A booster circuit 7 is provided in the amplification type MOS solid-state imaging device.
The power supply voltage can be reduced without increasing the power supply voltage input from the outside or increasing the number of power supply voltages.

The boosting circuit 7 does not boost many terminals, but introduces a boosted voltage to the gate of the reset transistor R to enable low-voltage driving. This is because the circuits other than the cell 1 are basically logic circuits, so that it is easy to lower the voltage. However, only the cell 1 is difficult to lower the voltage due to the circumstances described in the section of the prior art. This is because a drop in the threshold value of the reset transistor R is a factor that lowers the voltage and eliminates the margin. For example, when the power supply voltage is Vdd = 3.3 V and the threshold value of the reset transistor is 0.6 V, the voltage of the detection unit DN is approximately 2.2 due to the drop in the threshold value in consideration of the substrate bias effect.
The voltage drops by about 1.1V from V and Vdd.
Voltage drop due to transistor ON resistance is 0.1V ~
Since the voltage is about 0.3 V, preventing the threshold value of the reset transistor R from dropping is most effective. Referring to FIG. 7 described in the section of the prior art, if the gate voltage of the reset transistor R is boosted, the channel voltage Vch
(R) increases, and the vertical signal line Sig voltage V
Since sig also becomes high, Vsig and load transistor Lo
The difference in the channel voltage Vch (load) of ad becomes large, and an operation margin can be obtained. This is because the increase in the voltage of only the gate of the reset transistor R, which does not allow the DC current to flow, suppresses an increase in power consumption, and the current driving capability of the booster circuit 7 can be small. Easy to mount.

When the gate voltage of the reset transistor R is boosted, a stable operation can be achieved by setting the boosted voltage in a range where the reset transistor R operates in a linear region. This is because the detection unit D after reset
This is because the N potential is equal to the power supply voltage and does not reflect variations in the boosted voltage. If the boosted voltage is set in a range in which the reset transistor R operates in the saturation region, the potential of the detection unit DN after reset becomes a value obtained by subtracting the threshold value of the reset transistor R from the boosted voltage. As it is, the voltage of the detection unit DN varies.

When the booster circuit 7 is employed, it is operationally advantageous to boost the gate voltage of the address transistor Ad together with the reset transistor R. Since the address transistor Ad is provided only for selecting a row, it is desirable that the resistance be as small as possible when it is ON. If the gate voltage of the address transistor Ad is increased, the ON resistance of the address transistor Ad is reduced, and the operation margin is accordingly increased.

Regardless of whether or not the booster circuit 7 is mounted, the gate voltage of the transfer transistor T is made lower than the gate voltage of the reset transistor R, or the threshold value of the transfer transistor T is set lower than the threshold value of the reset transistor R. By increasing the value, it is possible to obtain an output with a high conversion gain without afterimages. The principle of the present invention will be described with reference to FIG. FIG. 1 is a potential diagram of the photodiode PD, the transfer transistor T, the detection unit DN, the reset transistor R, and the drain D in order from the left, and the lower side is drawn in a positive direction. FIG. 1A shows a case where the transfer gate and the gate of the reset transistor R are driven by the power supply voltage Vdd as in the conventional case. In order to facilitate comparison, from the photodiode PD to the drain D in FIG. Are basically the same as those shown in FIG. In this case, as described above, an afterimage exists and the conversion gain is small.

FIG. 1B shows that the transfer transistor T is increased by increasing the gate voltage of the reset transistor R.
Shows a state in which the gate voltage is set to be lower than the gate voltage of the reset transistor R. At this time, by sufficiently taking the difference between the gate voltages of the reset transistor R and the transfer transistor T, the photodiode P
Even if all the photoelectrons read from D accumulate in the detection unit DN, the voltage of the detection unit DN is
Is higher than the channel voltage Vch (T), photoelectrons can be read from the photodiode PD in a state where no electrons remain in the channel portion of the transfer transistor T. Therefore, according to the present invention, the transfer transistor T
Can be prevented from returning to the photodiode PD and causing an afterimage. According to the present invention,
Since all photoelectrons for one cycle of the photodiode PD can be read out to the detection unit DN, the conversion gain is large.

In the above description, the case where the gate of the reset transistor R is boosted has been described. However, the same effect can be obtained by lowering the gate voltage of the transfer transistor T. An example of this case is shown in FIG. FIG. 1C shows a case where the gate voltage of the reset transistor R is Vdd and the gate voltage of the transfer transistor T is set to a lower voltage. Even in this case, the respective gate voltages Vch (T) and Vc
Since a sufficient difference can be made between h (R) and electrons can be prevented from remaining below the channel of the transfer gate even at the time of reading, prevention of afterimage and improvement of conversion gain can be obtained. Note that, even when the gate voltages of the reset transistor R and the transfer transistor T are the same, by making the threshold value of the transfer transistor T larger than the threshold value of the reset transistor R, the circuit shown in FIG. Since the state can be realized, the same effect is obtained.

[0022]

Embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing a basic circuit configuration of the solid-state imaging device according to the first embodiment of the present invention. 2, the same parts as those in FIG. 6 are denoted by the same reference numerals, and detailed description will be omitted. FIG. 2 differs from FIG.
The point is that the booster circuit 7 is added to the device (that is, in the same chip).

The output VH of the booster circuit 7 is input to the gate wiring of the reset transistor R through the level shifter 8. The gate wiring of the reset transistor R is driven by the vertical shift register 3 with the binary value of this boosted voltage VH and ground 0V. You. The gate wiring of the transfer transistor T and the address transistor Ad is the vertical shift register 3
And driven by two values of the power supply voltage Vdd and the ground 0V. With this configuration, the reset transistor R
Satisfies the condition that it is driven at a higher voltage than the gate of the transfer transistor T.

In the above configuration, the power supply voltage Vd
d was set to 3.3 V, and the boosted voltage VH was set to 5.5 V. The threshold values of the reset (R), amplification (Amp), and address (Ad) transistors were 0.6 V, and the transfer transistor T was 1.0 V.

The reason why the reset transistor R operates in the linear region is that, according to actual measurement, the boosted voltage VH is expressed as follows: VH> Vdd × 1.25 + Vth (R) (where Vdd: power supply voltage, Vth (R): reset transistor R Of the boosted voltage is 5.5 V, the value of the boosted voltage is 5.5 V.
The range is set so that the reset transistor R operates in a linear region with a margin for threshold variation.

FIG. 3 shows a potential map obtained by combining the cell 1 and the load transistor Load. The drain voltage is 3.3 V which is the power supply voltage. Since the reset transistor R operates in the linear region, the voltage of the detection unit DN immediately after the reset is almost 3.3 V, and hardly changes even if the boosted voltage varies. The channel voltage of the transfer transistor T is 1.8 V, and the detecting unit D
In N, photoelectrons can be stored up to this voltage without a problem of a decrease in conversion gain or an afterimage. Actually, from the relationship with the capacitance of the photodiode PD, the voltage of the detection unit DN is 2.3 V even when the photoelectrons are read out to the maximum, so that the voltage of the detection unit DN is 2.3 V to 3 V depending on the amount of photoelectrons. 3V
, And will always operate without any problem. Since this voltage enters the gate of the amplification transistor Amp,
The channel voltage of the amplifying transistor Amp is now determined by the threshold drop of the amplifier (Amp), and this value is 1.4 to 2.2V. The amplification transistor Amp operates in the saturation region, and the potential of the diffusion layer F is lower by the ON resistance of the amplification transistor Amp, and is 1.1 to 1.9 V. The address transistor Ad operates in the linear region, and the voltage Vsig output to the signal line is lower by the ON resistance of the address transistor Ad, and is 1.0 to 1.8 V. The lower 1.0V of this value is the load transistor Loa.
There is a margin of 0.5V to 0.5V for the channel voltage of d,
There is a sufficient margin for variations in threshold voltage and power supply voltage. 0.8 V, which is the amplitude of Vsig, is a value sufficient for a practical solid-state imaging device.

As described above, according to the solid-state imaging device of the present invention, 3.3 V of a device having a sufficient operation margin is obtained.
Operation can be realized. It is also apparent that the power supply voltage can be further reduced by adjusting the threshold values of the transfer transistor T and the reset transistor R.

FIG. 4 shows a block diagram of a solid-state imaging device according to a second embodiment of the present invention. 4, the same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description will be omitted.
The second embodiment is different from the first embodiment in that the cell 1
Address transistor Ad and amplification transistor Amp
And that the boosted voltage is input to both the address transistor Ad and the reset transistor R.

In the second embodiment, since the address transistor Ad is on the drain side, when the gate of the address transistor Ad is set to the same power supply voltage Vdd as the drain, the address transistor Ad operates only in the saturation region. A threshold drop occurs and the ON resistance increases. Therefore, the operation margin is narrowed by the sum of the two, and it is difficult to reduce the voltage. In this case, the operation margin can be expanded in the same manner as described above by introducing the boosted voltage only to the gate of the reset transistor R. However, as in the present embodiment, the operation margin is increased between the gate of the reset transistor R and the gate of the address transistor Ad. Even better results are obtained by introducing a boosted voltage. This will be described with reference to the potential diagram of FIG.

The power supply voltage, the boosted voltage, and the threshold value of each transistor are the same as in the first embodiment. Therefore, the detection unit D
The voltage of N ranges from 2.3 V to 3.3 V depending on the number of photoelectrons as in the first embodiment. Further, the first reason is that the channel voltage of the transfer transistor T is 1.8 V and the voltage of the detection unit DN is always higher than that.
This is the same as the embodiment.

In this embodiment, the address transistor A
Since the boosted voltage is also input to the gate of d and the input boosted voltage is the same as the gate of the reset transistor R, the address transistor Ad also operates in a linear region with a sufficient margin. Therefore, the voltage of the diffusion layer F is 3.2 V, which is lower than the drain voltage by the ON resistance of the address transistor Ad. The channel voltage of the amplification transistor Amp is determined by the threshold voltage drop of the amplification transistor Amp from the voltage of the detection unit DN, and its value is 1.4 to 2.2V. The voltage of the vertical signal line Sig decreases from this value by the ON resistance of the amplification transistor Amp, and becomes 1.1 to 1.9 V. This value is at least 0. 1 from the channel voltage 0.5V of the load transistor Load.
A margin of 6V can be taken.

As described above, by applying the second embodiment according to the present invention, even if the address transistor Ad, which has been conventionally difficult, is disposed on the drain side of the amplifying transistor Amp, the address transistor Ad can be replaced with the third transistor. It can operate with a sufficient operation margin at .3V. Also,
By lowering the threshold value of the transfer transistor T, it is possible to cope with further lowering the voltage. The present invention is not limited to the above embodiments of the present invention, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

[0033]

According to the present invention, the following effects can be obtained. As described in detail above, according to the present invention, it is possible to provide a solid-state imaging device that secures an operation margin with a low power supply voltage, has less afterimages, and has a high conversion gain.

[Brief description of the drawings]

FIG. 1 is a potential diagram showing the operation of the present invention.

FIG. 2 is a block diagram showing a first embodiment of the present invention.

FIG. 3 is a potential diagram showing the operation of the first embodiment of the present invention.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a potential diagram showing an operation 2 of the embodiment of the present invention.

FIG. 6 is a block diagram of a conventional amplification type MOS solid-state imaging device.

FIG. 7 is a potential diagram showing the operation of a conventional cell.

FIG. 8 is a potential diagram showing a problem of a conventional cell operation.

[Explanation of symbols]

1 cell, 2 cell array, 3 vertical shift register,
4: horizontal shift register, 5: noise canceller circuit,
6: output amplifier, 7: booster circuit, PD: photodiode, DN: detector, T: transfer transistor, Amp: amplifier transistor, Ad: address transistor, R: reset transistor, D: drain, F: amplifier transistor and address Diffusion layer between transistors, Load ...
Load transistor, Sig: vertical signal line, Vss: ground (0 V), Vdd: power supply voltage, VH: boost voltage, V
sig: vertical signal line potential, Vch (load): load transistor channel potential, Vch (T): transfer transistor channel potential, Vch (R): reset transistor channel potential.

──────────────────────────────────────────────────の Continuing on the front page (51) Int.Cl. ⁶ Identification symbol FI H04N 5/335 (72) Inventor Nagataka Tanaka 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba R & D Center Co., Ltd. (72) Inventor Ryohei Miyakawa 1 Kobayashi Toshiba-cho, Yuki-ku, Kawasaki City, Kanagawa Prefecture

Claims (6)

[Claims] 1. A photodiode formed on a semiconductor substrate, an amplification transistor for inputting a signal of the photodiode to a gate, address means for activating the amplification transistor, and a reset transistor for discharging a signal of the photodiode. A solid-state imaging device using a unit cell having at least a booster circuit in the same chip. 2. The solid-state imaging device according to claim 1, wherein
An output of the booster circuit is input to a gate of the reset transistor. 3. The solid-state imaging device according to claim 2, wherein
An output of the booster circuit is set in a range in which the reset transistor operates in a linear region. 4. A photodiode formed on a semiconductor substrate, an amplification transistor for inputting a signal of the photodiode to a gate, an address transistor for activating the amplification transistor, and a reset transistor for discharging a signal of the photodiode. In a solid-state imaging device using a unit cell having at least a booster circuit mounted on the same chip, an output of the booster circuit is input to a gate of the reset transistor and a gate of the address transistor. Solid-state imaging device. 5. A photodiode formed on a semiconductor substrate, a transfer transistor for transferring a signal of the photodiode, an amplifying transistor for inputting the transferred signal to a gate, and an address for activating the amplifying transistor. Means for driving a solid-state imaging device using a unit cell having at least a reset transistor for discharging a signal of a photodiode, wherein a gate voltage for activating the transfer transistor is lower than a gate voltage for activating the reset transistor. And driving the transfer transistor. 6. A photodiode formed on a semiconductor substrate, a transfer transistor for transferring a signal of the photodiode, an amplification transistor for inputting the transferred signal to a gate, and an address for activating the amplification transistor. And a solid-state imaging device using a unit cell having at least a reset transistor for discharging a photodiode signal, wherein the threshold value of the transfer transistor is higher than the threshold value of the reset transistor. apparatus.