JPH1126654A - Resin-sealed semiconductor device and its manufacture - Google Patents
Resin-sealed semiconductor device and its manufactureInfo
- Publication number
- JPH1126654A JPH1126654A JP17416797A JP17416797A JPH1126654A JP H1126654 A JPH1126654 A JP H1126654A JP 17416797 A JP17416797 A JP 17416797A JP 17416797 A JP17416797 A JP 17416797A JP H1126654 A JPH1126654 A JP H1126654A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- circuit board
- semiconductor device
- potting material
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000004382 potting Methods 0.000 claims abstract description 41
- 239000000463 material Substances 0.000 claims abstract description 35
- 239000000945 filler Substances 0.000 claims abstract description 15
- 239000007788 liquid Substances 0.000 claims abstract description 9
- 239000011347 resin Substances 0.000 claims description 18
- 229920005989 resin Polymers 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 8
- 229920001296 polysiloxane Polymers 0.000 abstract description 16
- 230000008646 thermal stress Effects 0.000 abstract description 5
- 238000010276 construction Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 abstract 1
- 230000035882 stress Effects 0.000 description 11
- 238000001723 curing Methods 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- 239000003795 chemical substances by application Substances 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- 239000000126 substance Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000003672 processing method Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000003094 microcapsule Substances 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は樹脂封止型半導体
装置及びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device and a method of manufacturing the same.
【0002】[0002]
【従来の技術】従来、回路基板上に配置された表面実装
部品(SMD)は外部雰囲気や振動等から保護するため
にポッティング樹脂にて覆うようにしている。この場
合、回路基板と表面実装部品との間に隙間が形成される
ようなフリップチップ(FC)やクォドフラットパッケ
ージ(QFP)やスモールアウトライン型パッケージ
(SOP)に代表される表面実装部品は、その隙間にポ
ッティング樹脂が入り込み、その回路基板との接続部位
(通常、半田付け部)にポッティング樹脂の熱応力(熱
が加わった時の作用力)が加わり、寿命の低下を招いた
り破壊にいたらしめる場合がある。このために、ポッテ
ィング樹脂の化学的組成の変更(例えば、網目構造にお
ける網目を大きくする)にてポッティング樹脂自身の低
応力化を図ることにより対処してきた。2. Description of the Related Art Conventionally, a surface mount component (SMD) arranged on a circuit board is covered with a potting resin to protect it from an external atmosphere or vibration. In this case, a surface mount component such as a flip chip (FC), a quad flat package (QFP), or a small outline type package (SOP), in which a gap is formed between the circuit board and the surface mount component, is used. Potting resin enters into the gap, and thermal stress (operating force when heat is applied) of the potting resin is applied to a connection portion (usually, a soldered portion) with the circuit board, resulting in shortening of life or destruction. There are cases. To cope with this, the stress of the potting resin itself has been reduced by changing the chemical composition of the potting resin (for example, by increasing the size of the network in the network structure).
【0003】[0003]
【発明が解決しようとする課題】しかしながら、上記の
方法では、化学組成の変更が必要であるとともに、その
組成変更に伴い加工方法の変更も必要となり、コストア
ップを招いたり防湿性の低下を招く等の不具合があっ
た。However, in the above method, the chemical composition needs to be changed, and the processing method needs to be changed in accordance with the change in the chemical composition, resulting in an increase in cost and a decrease in moisture resistance. There was a problem such as.
【0004】そこで、この発明の目的は、新規な構成に
て容易に熱応力による不具合を解消することができる樹
脂封止型半導体装置及びその製造方法を提供することに
ある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a resin-sealed semiconductor device and a method for manufacturing the same, which can easily solve the problem caused by thermal stress with a novel structure.
【0005】[0005]
【課題を解決するための手段】請求項1に記載の樹脂封
止型半導体装置は、表面実装部品の全体を覆うポッティ
ング材の中に微小な気泡を散在したことを特徴としてい
る。According to a first aspect of the present invention, there is provided a resin-encapsulated semiconductor device, wherein minute bubbles are scattered in a potting material covering the entire surface-mounted component.
【0006】このような構成をとると、回路基板の上と
表面実装部品との間にポッティング材が存在し、このポ
ッティング材に温度が加わった場合には、ポッティング
材が熱伸縮して回路基板と表面実装部品との電気接続部
位に応力が加わろうとする。しかし、このとき、ポッテ
ィング材中の気泡が変形代(潰し代)になって応力緩和
が図られる。With this configuration, a potting material exists between the circuit board and the surface-mounted component. When a temperature is applied to the potting material, the potting material thermally expands and contracts. Attempts to apply stress to the electrical connection between the device and the surface mount component. However, at this time, the bubbles in the potting material serve as deformation allowances (crushing allowances) to achieve stress relaxation.
【0007】また、一般的なポッティング樹脂(例え
ば、一般的なシリコーンゲル等)を用いることによりコ
ストアップを招くこともない。請求項2に記載の発明に
よれば、第1工程により、回路基板の上に表面実装部品
が配置され、第2工程により、樹脂に中空球フィラーを
混入させたポッティング材にて表面実装部品の全体が覆
われる。Further, the use of a general potting resin (for example, a general silicone gel) does not increase the cost. According to the second aspect of the present invention, in the first step, the surface-mounted component is arranged on the circuit board, and in the second step, the surface-mounted component is formed of a potting material obtained by mixing a hollow sphere filler in a resin. The whole is covered.
【0008】その結果、請求項1に記載の樹脂封止型半
導体装置が製造される。ここで、請求項3に記載のよう
に、前記第2工程において、硬化前の液状樹脂に中空球
フィラーを混入させた溶液を、前記部品の表面に配置
し、その後に、硬化処理を施すと、実用上好ましいもの
となる。As a result, the resin-sealed semiconductor device according to the first aspect is manufactured. Here, as described in claim 3, in the second step, a solution obtained by mixing a hollow resin with a liquid resin before curing is disposed on the surface of the component, and thereafter, a curing process is performed. This is practically preferable.
【0009】[0009]
【発明の実施の形態】以下、この発明を具体化した実施
の形態を図面に従って説明する。図1には、本実施形態
における樹脂封止型半導体装置の斜視図を示す。また、
図2には、樹脂封止型半導体装置の縦断面を示す。図2
のA部を拡大したものを図3に示す。本例の樹脂封止型
半導体装置は内燃機関における点火装置に用いられるも
のである。つまり、点火コイルにより高電圧を発生させ
て点火プラグに供給するための装置である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view of a resin-sealed semiconductor device according to the present embodiment. Also,
FIG. 2 shows a longitudinal section of the resin-sealed semiconductor device. FIG.
FIG. 3 shows an enlarged portion A of FIG. The resin-sealed semiconductor device of this example is used for an ignition device in an internal combustion engine. That is, it is a device for generating a high voltage by the ignition coil and supplying it to the ignition plug.
【0010】図1,2において、ケース1の内部には混
成集積回路基板2が配置され、回路基板2の上面には導
体パターン(例えば、図中、符号3a,3bにて示す)
が形成されるとともに、導体パターン3a,3bの間に
は厚膜抵抗4が配置されている。回路基板2の上面には
フリップチップタイプのIC(以下、ICチップとい
う)5やクォドフラットパッケージ(QFP)6等の部
品が表面実装されるとともに、抵抗7等の部品が実装さ
れている。この厚膜抵抗4や実装部品5〜7等により点
火制御回路が形成されている。In FIGS. 1 and 2, a hybrid integrated circuit board 2 is disposed inside a case 1, and a conductor pattern (for example, indicated by reference numerals 3a and 3b in the drawings) is provided on an upper surface of the circuit board 2.
Is formed, and a thick film resistor 4 is arranged between the conductor patterns 3a and 3b. On the upper surface of the circuit board 2, components such as a flip-chip type IC (hereinafter referred to as an IC chip) 5 and a quad flat package (QFP) 6 are mounted on the surface, and components such as a resistor 7 are mounted. An ignition control circuit is formed by the thick film resistor 4, the mounted components 5 to 7, and the like.
【0011】ICチップ5は、図3に示すように、底面
に複数の半田バンプ8が設けられている。このICチッ
プ5の各半田バンプ8が、回路基板2の上面の導体パタ
ーン9の上に搭載され半田付けされている。この半田バ
ンプ8の半田接合によりICチップ5と導体パターン9
とが電気的に接続されている。ここで、回路基板2の上
面とICチップ5の下面との間には隙間AGが形成され
ている。As shown in FIG. 3, the IC chip 5 is provided with a plurality of solder bumps 8 on the bottom surface. Each solder bump 8 of the IC chip 5 is mounted on the conductor pattern 9 on the upper surface of the circuit board 2 and soldered. By the solder bonding of the solder bumps 8, the IC chip 5 and the conductor pattern 9 are formed.
And are electrically connected. Here, a gap AG is formed between the upper surface of the circuit board 2 and the lower surface of the IC chip 5.
【0012】また、図1,2に示すように、外部接続端
子(リードピン)10a,10bが回路基板2に立設さ
れており、この外部接続端子10a,10bも回路基板
2の上面の導体パターンと電気的に接続されている。外
部接続端子10a,10bに点火コイルやバッテリが接
続される。As shown in FIGS. 1 and 2, external connection terminals (lead pins) 10a and 10b are erected on the circuit board 2, and the external connection terminals 10a and 10b are also provided on the conductor pattern on the upper surface of the circuit board 2. Is electrically connected to An ignition coil and a battery are connected to the external connection terminals 10a and 10b.
【0013】さらに、ケース1の内部にはポッティング
材11が充填されており、このポッティング材11が、
図3に示すように、回路基板2の上面とICチップ5の
下面との隙間AGにも充填されている。図3において、
ポッティング材11は母材としてシリコーンゲル12が
用いられ、このシリコーンゲル12の中に微小な気泡
(中空球)13が多数散在している。気泡13の径は、
80μm程度である。ポッティング材11はポアソン比
が0.4程度である。つまり、シリコーンゲル12単体
のポアソン比は0.5程度であるが、微小な気泡13を
散在することによりポアソン比が0.4程度になってい
る。このポッティング材11により、回路基板2側の導
体パターンと実装部品との電気接続部位(半田付け部)
が保護されている。Further, the inside of the case 1 is filled with a potting material 11.
As shown in FIG. 3, the gap AG between the upper surface of the circuit board 2 and the lower surface of the IC chip 5 is also filled. In FIG.
As the potting material 11, a silicone gel 12 is used as a base material, and a large number of fine bubbles (hollow spheres) 13 are scattered in the silicone gel 12. The diameter of the bubble 13 is
It is about 80 μm. The potting material 11 has a Poisson's ratio of about 0.4. That is, the Poisson's ratio of the silicone gel 12 alone is about 0.5, but the Poisson's ratio is about 0.4 due to the scattered fine bubbles 13. With this potting material 11, an electrical connection portion (soldering portion) between the conductor pattern on the circuit board 2 side and the mounted component is provided.
Is protected.
【0014】このように、表面実装部品としてのICチ
ップ5やクォドフラットパッケージ(QFP)6はポッ
ティング材11にて全体が覆われ、衝撃や振動に耐え、
外気から保護されている(湿気や腐食から保護されてい
る)。As described above, the IC chip 5 and the quad flat package (QFP) 6 as the surface mount components are entirely covered with the potting material 11 to withstand shock and vibration.
Protected from the outside air (protected from moisture and corrosion).
【0015】このポッティング材11は熱が加わった際
に体積が変化するが、散在した気泡13が変形代(潰し
代)になって熱応力が吸収される。そのため、熱が加わ
った際に、ICチップ5での半田接合部に対して熱応力
が加わりにくい。Although the volume of the potting material 11 changes when heat is applied, the scattered bubbles 13 become deformation allowances (crushing allowances) to absorb thermal stress. Therefore, when heat is applied, thermal stress is less likely to be applied to the solder joints of the IC chip 5.
【0016】即ち、図4に示すように、気泡13が混入
していない場合には特性線P1にて示すようにICチッ
プ5には歪み量δに比例した大きな力Fが加わるが、気
泡13を混入することにより気泡13が潰れ代となり、
特性線P2にて示すように所定の歪み量δ1までは殆ど
力FがICチップ5に加わらない。That is, as shown in FIG. 4, when the bubbles 13 are not mixed, a large force F proportional to the amount of strain δ is applied to the IC chip 5 as shown by the characteristic line P1, , The bubble 13 becomes a crushing allowance,
As shown by the characteristic line P2, almost no force F is applied to the IC chip 5 up to the predetermined distortion amount δ1.
【0017】同様のことがクォドフラットパッケージ
(QFP)6についても言える。つまり、回路基板2の
上面とクォドフラットパッケージ(QFP)6の下面と
の間にも隙間が形成され、この隙間に微小な気泡13を
散在したポッティング材11が充填され、温度が加わっ
た際に電気接続部位に応力が加わろうとするが、気泡1
3が変形代(潰し代)になって応力緩和が図られる。The same applies to the quad flat package (QFP) 6. That is, a gap is also formed between the upper surface of the circuit board 2 and the lower surface of the quad flat package (QFP) 6, and the gap is filled with the potting material 11 in which minute bubbles 13 are scattered. Attempts to apply stress to the electrical connection site
3 serves as a deformation allowance (crushing allowance) to achieve stress relaxation.
【0018】次に、このように構成した樹脂封止型半導
体装置の製造方法を説明する。まず、回路基板2の上に
ICチップ5およびクォドフラットパッケージ(QF
P)6を表面実装するとともに、抵抗7等の部品を実装
する。同時に、回路基板2の上に外部接続端子10a,
10bを実装する。そして、この回路基板2をケース1
の内部に配置し、固定する。このとき、回路基板2の上
面とICチップ5の下面との間に隙間AGが形成される
とともに、回路基板2の上面とクォドフラットパッケー
ジ(QFP)6の下面との間に隙間が形成される。Next, a method for manufacturing the resin-encapsulated semiconductor device thus configured will be described. First, an IC chip 5 and a quad flat package (QF
P) 6 is mounted on the surface, and components such as the resistor 7 are mounted. At the same time, the external connection terminals 10a,
10b is mounted. Then, this circuit board 2 is attached to case 1
Place inside and secure. At this time, a gap AG is formed between the upper surface of the circuit board 2 and the lower surface of the IC chip 5, and a gap is formed between the upper surface of the circuit board 2 and the lower surface of the quad flat package (QFP) 6. .
【0019】一方、図5に示すように、硬化前の液状樹
脂としてのポッティング材(11)を用意する。つま
り、まず、液状シリコーンゲルを用意するとともに、図
6に示す中空球フィラー(マイクロカプセル)20を用
意する。中空球フィラー20は、その径Dが80μm程
度の微粒体である。中空球フィラー20としては、例え
ば、日本フィライト社製DU−80を用いる。そして、
液状シリコーンゲルゲルと適量の中空球フィラー20と
を混合させる(図5に示す混合工程)。On the other hand, as shown in FIG. 5, a potting material (11) is prepared as a liquid resin before curing. That is, first, a liquid silicone gel is prepared, and a hollow sphere filler (microcapsule) 20 shown in FIG. 6 is prepared. The hollow sphere filler 20 is a fine particle having a diameter D of about 80 μm. As the hollow sphere filler 20, for example, DU-80 manufactured by Nippon Philite Co., Ltd. is used. And
The liquid silicone gel is mixed with an appropriate amount of the hollow sphere filler 20 (mixing step shown in FIG. 5).
【0020】引き続き、液状シリコーンゲルに中空球フ
ィラー20を混入させた溶液を、前述のケース1内に注
入する(図5に示す注入工程)。このとき、ICチップ
5の下の隙間AGやクォドフラットパッケージ(QF
P)6の下の隙間に、硬化前シリコーンゲル溶液が入り
込む。Subsequently, a solution in which the hollow sphere filler 20 is mixed into the liquid silicone gel is injected into the case 1 (injection step shown in FIG. 5). At this time, the gap AG under the IC chip 5 and the quad flat package (QF
The silicone gel solution before curing enters the gap below P) 6.
【0021】さらに、加熱にて硬化前シリコーンゲル溶
液を硬化させる(図5に示す熱硬化工程)。その結果、
液状シリコーンゲルに中空球フィラー20が分散した状
態のまま固化される。Further, the silicone gel solution before curing is cured by heating (a heat curing step shown in FIG. 5). as a result,
The hollow sphere filler 20 is solidified while being dispersed in the liquid silicone gel.
【0022】このようにして、図1〜3に示す樹脂封止
型半導体装置が製造される。このように本実施形態は、
下記の特徴を有する。 (イ)回路基板2の上に表面実装部品5,6を表面実装
し、ポッティング材で封止した樹脂封止型半導体装置に
おいて、ポッティング材11の中に微小な気泡13を散
在した。Thus, the resin-sealed semiconductor device shown in FIGS. 1 to 3 is manufactured. Thus, this embodiment is
It has the following features. (A) In the resin-sealed semiconductor device in which the surface-mounted components 5 and 6 are surface-mounted on the circuit board 2 and sealed with a potting material, minute bubbles 13 are scattered in the potting material 11.
【0023】よって、回路基板2の上と表面実装部品
5,6との間にポッティング材11が存在し、このポッ
ティング材11に温度が加わった場合には、ポッティン
グ材11が熱伸縮して回路基板2と表面実装部品5,6
との電気接続部位に応力が加わろうとする。しかし、こ
のとき、ポッティング材11中の気泡13が変形代(潰
し代)になって応力緩和が図られる。Therefore, the potting material 11 exists between the upper surface of the circuit board 2 and the surface mount components 5 and 6, and when the potting material 11 is heated, the potting material 11 expands and contracts due to heat. Substrate 2 and surface mount components 5, 6
Attempts to apply stress to the electrical connection site with. However, at this time, the bubbles 13 in the potting material 11 serve as deformation allowances (crush allowances), so that stress is relaxed.
【0024】また、一般的なシリコーンゲルを用いてい
るのでコストアップを招くこともない。つまり、ポッテ
ィング樹脂の化学的組成の変更(例えば、網目構造にお
ける網目を大きくする)にてポッティング樹脂自身の低
応力化を図ると、化学組成の変更および組成変更に伴う
加工方法の変更にてコストアップを招いてしまうが、本
実施形態においては、一般的なシリコーンゲルを用いて
加工方法の変更も不要である。Further, since a general silicone gel is used, there is no increase in cost. That is, if the potting resin itself is reduced in stress by changing the chemical composition of the potting resin (for example, by increasing the size of the mesh in the network structure), the cost will be reduced due to the change in the chemical composition and the processing method accompanying the change in the composition. However, in this embodiment, it is not necessary to change the processing method using a general silicone gel.
【0025】また、ポッティング樹脂の化学的組成の変
更は行っておらずシリコーンゲルの有する防湿性を利用
して確実に表面実装部品5,6を外気から保護できる。 (ロ)回路基板2の上に表面実装部品5,6を配置し
(第1工程)、樹脂に中空球フィラー20を混入させた
ポッティング材にて表面実装部品5,6の全体を覆う
(第2工程)ことにより、上記(イ)に記載の樹脂封止
型半導体装置が製造される。 (ハ)特に、前記第2工程において、硬化前の液状樹脂
に中空球フィラー20を混入させた溶液を、表面実装部
品5,6の表面に配置し、その後に、硬化処理を施す
と、実用上好ましいものとなる。Further, the chemical composition of the potting resin is not changed, and the surface mount components 5, 6 can be reliably protected from the outside air by utilizing the moisture-proof property of the silicone gel. (B) The surface-mounted components 5 and 6 are arranged on the circuit board 2 (first step), and the entire surface-mounted components 5 and 6 are covered with a potting material in which the hollow sphere filler 20 is mixed in the resin (second step). Through the two steps), the resin-encapsulated semiconductor device described in (a) above is manufactured. (C) In particular, in the second step, a solution in which the hollow sphere filler 20 is mixed in the liquid resin before curing is arranged on the surface of the surface mount components 5 and 6, and thereafter, a curing treatment is performed. It becomes more preferable.
【0026】これまで説明してきた実施の形態以外にも
下記のように実施してもよい。図7に示すように、表面
実装部品(半導体モールドパッケージ)30は側面から
延びるリード31,32を有している。そして、回路基
板2の上において表面実装部品30のリード31,32
が回路基板2上面の導体33,34の上に搭載され、半
田付けにて接合されている。また、回路基板2の上面と
表面実装部品30の下面との間には隙間AGが形成され
ている。この隙間AGを含めた表面実装部品30の周囲
にはポッティング材(防湿膜;ヒューミシール)35が
塗布されている。ポッティング材35はポリイミド(ま
たはポリアミド)36を母材とし、ポリイミド36に微
小な気泡37を散在したものである。つまり、硬化前の
ポリイミド36に中空フィラー(マイクロバルーン)を
混入し、表面実装部品30に塗布した後に硬化したもの
である。このポッティング材35により熱サイクルが加
わったときにも、回路基板2の上面と表面実装部品30
の下面との隙間AGにおいてポッティング材35が伸縮
しようとするが、気泡37によりその応力が吸収され、
回路基板2と表面実装部品30との間に応力が加わった
際において、ポッティング材35中の気泡37が変形代
(潰し代)になって応力緩和が図られる。In addition to the embodiment described above, the present invention may be implemented as follows. As shown in FIG. 7, the surface mount component (semiconductor mold package) 30 has leads 31 and 32 extending from side surfaces. Then, the leads 31 and 32 of the surface mount component 30 are mounted on the circuit board 2.
Are mounted on the conductors 33 and 34 on the upper surface of the circuit board 2 and joined by soldering. A gap AG is formed between the upper surface of the circuit board 2 and the lower surface of the surface mount component 30. A potting material (moisture proof film; HumiSeal) 35 is applied around the surface mounting component 30 including the gap AG. The potting material 35 is made of polyimide (or polyamide) 36 as a base material and fine bubbles 37 dispersed in the polyimide 36. That is, a hollow filler (microballoon) is mixed into the polyimide 36 before curing, applied to the surface mount component 30, and then cured. Even when a thermal cycle is applied by the potting material 35, the upper surface of the circuit board 2 and
The potting material 35 attempts to expand and contract in the gap AG with the lower surface of the cell, but the stress is absorbed by the bubbles 37,
When a stress is applied between the circuit board 2 and the surface mount component 30, the bubbles 37 in the potting material 35 become deformation allowances (crush allowances), so that stress is relaxed.
【0027】また、封止樹脂の硬化は加熱を用いたが、
紫外線照射等の手法により行ってもよい。また、表面実
装部品の基板側への接合は、半田付け以外にも導電性接
着剤にて行い、部品側電極と基板側導体とを接合しても
よい。In addition, although heating was used for curing the sealing resin,
It may be performed by a method such as ultraviolet irradiation. In addition, bonding of the surface-mounted component to the substrate side may be performed by a conductive adhesive other than soldering, and the component-side electrode and the substrate-side conductor may be bonded.
【図1】 実施形態における樹脂封止型半導体装置の斜
視図。FIG. 1 is a perspective view of a resin-sealed semiconductor device according to an embodiment.
【図2】 樹脂封止型半導体装置の縦断面図。FIG. 2 is a longitudinal sectional view of a resin-sealed semiconductor device.
【図3】 図2のA部の拡大図。FIG. 3 is an enlarged view of a portion A in FIG. 2;
【図4】 歪み量と力との関係を示す特性図。FIG. 4 is a characteristic diagram showing a relationship between a strain amount and a force.
【図5】 樹脂封止型半導体装置の製造工程を説明する
ための工程図。FIG. 5 is a process chart for explaining a manufacturing process of the resin-sealed semiconductor device.
【図6】 中空球フィラーの断面図。FIG. 6 is a sectional view of a hollow sphere filler.
【図7】 別例の樹脂封止型半導体装置の断面図。FIG. 7 is a cross-sectional view of another example of a resin-sealed semiconductor device.
2…回路基板、5…ICチップ、6…クォドフラットパ
ッケージ、11…ポッティング材、13…気泡、20…
中空球フィラー、30…表面実装部品、35…ポッティ
ング材、37…気泡。2 circuit board, 5 IC chip, 6 quad flat package, 11 potting material, 13 bubbles, 20
Hollow sphere filler, 30: surface mount component, 35: potting material, 37: air bubble.
Claims (3)
た樹脂封止型半導体装置において、 前記ポッティング材の中に微小な気泡を散在したことを
特徴とする樹脂封止型半導体装置。1. A resin-encapsulated semiconductor device comprising: a circuit board; a surface-mounted component disposed on the circuit board; and a potting material that covers the entire surface-mounted component. A resin-encapsulated semiconductor device characterized in that minute bubbles are scattered in the semiconductor device.
第1工程と、 樹脂に中空球フィラーを混入させたポッティング材にて
前記表面実装部品の全体を覆う第2工程と、を備えたこ
とを特徴とする樹脂封止型半導体装置の製造方法。2. A first step of disposing a surface mount component on a circuit board, and a second step of covering the entire surface mount component with a potting material obtained by mixing a hollow sphere filler in a resin. A method for manufacturing a resin-encapsulated semiconductor device, comprising:
空球フィラーを混入させた溶液を、前記部品の表面に配
置し、その後に、硬化処理を施すものである請求項2に
記載の樹脂封止型半導体装置の製造方法。3. The method according to claim 2, wherein, in the second step, a solution in which a hollow sphere filler is mixed in a liquid resin before curing is disposed on the surface of the component, and thereafter, a curing treatment is performed. Of manufacturing a resin-sealed semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17416797A JPH1126654A (en) | 1997-06-30 | 1997-06-30 | Resin-sealed semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17416797A JPH1126654A (en) | 1997-06-30 | 1997-06-30 | Resin-sealed semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1126654A true JPH1126654A (en) | 1999-01-29 |
Family
ID=15973885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17416797A Pending JPH1126654A (en) | 1997-06-30 | 1997-06-30 | Resin-sealed semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1126654A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11138585A (en) * | 1997-11-14 | 1999-05-25 | Denso Corp | Sealing method by rubber composition |
| WO2007015344A1 (en) * | 2005-08-04 | 2007-02-08 | Murata Manufacturing Co., Ltd. | Coil antenna |
| EP1729554A3 (en) * | 2005-05-31 | 2007-08-01 | Fujitsu Limited | Soldering method, electronic part, and part-exchanging method |
| WO2008050635A1 (en) * | 2006-10-19 | 2008-05-02 | Panasonic Corporation | Semiconductor element mounting structure and semiconductor element mounting method |
| CN100435027C (en) * | 2001-08-10 | 2008-11-19 | 三星电子株式会社 | Charge transfer compound, organic photoacceptor, electrophotographic imaging device and electrophotographic imaging method |
| WO2017051919A1 (en) * | 2015-09-26 | 2017-03-30 | 京セラ株式会社 | Thermal head and thermal printer |
-
1997
- 1997-06-30 JP JP17416797A patent/JPH1126654A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11138585A (en) * | 1997-11-14 | 1999-05-25 | Denso Corp | Sealing method by rubber composition |
| CN100435027C (en) * | 2001-08-10 | 2008-11-19 | 三星电子株式会社 | Charge transfer compound, organic photoacceptor, electrophotographic imaging device and electrophotographic imaging method |
| EP1729554A3 (en) * | 2005-05-31 | 2007-08-01 | Fujitsu Limited | Soldering method, electronic part, and part-exchanging method |
| WO2007015344A1 (en) * | 2005-08-04 | 2007-02-08 | Murata Manufacturing Co., Ltd. | Coil antenna |
| US7425929B2 (en) | 2005-08-04 | 2008-09-16 | Murata Manufacturing Co., Ltd. | Coil antenna |
| JPWO2008050635A1 (en) * | 2006-10-19 | 2010-02-25 | パナソニック株式会社 | Semiconductor element mounting structure and semiconductor element mounting method |
| WO2008050635A1 (en) * | 2006-10-19 | 2008-05-02 | Panasonic Corporation | Semiconductor element mounting structure and semiconductor element mounting method |
| US8106521B2 (en) | 2006-10-19 | 2012-01-31 | Panasonic Corporation | Semiconductor device mounted structure with an underfill sealing-bonding resin with voids |
| JP5066529B2 (en) * | 2006-10-19 | 2012-11-07 | パナソニック株式会社 | Semiconductor element mounting structure and semiconductor element mounting method |
| WO2017051919A1 (en) * | 2015-09-26 | 2017-03-30 | 京セラ株式会社 | Thermal head and thermal printer |
| CN108025559A (en) * | 2015-09-26 | 2018-05-11 | 京瓷株式会社 | Thermal head and thermo printer |
| JPWO2017051919A1 (en) * | 2015-09-26 | 2018-06-28 | 京セラ株式会社 | Thermal head and thermal printer |
| US10279596B2 (en) | 2015-09-26 | 2019-05-07 | Kyocera Corporation | Thermal head and thermal printer |
| CN108025559B (en) * | 2015-09-26 | 2019-09-27 | 京瓷株式会社 | Thermal head and thermal printer |
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