JPH11266003A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: A semiconductor having a charge-coupled device that can reduce the cell size of a solid-state imaging device, has no backflow when transferring signal charges, can sufficiently secure the capacity of signal charges, and has high sensitivity. An apparatus and a method for manufacturing the same are provided. The semiconductor layer includes a conductive impurity of a first conductivity type, a gate insulating film formed on the semiconductor layer, and a first layer formed on the gate insulating film.
A gate electrode 30, a second gate electrode 31 insulated from the first gate electrode 30 and formed on an upper layer of the gate insulating film 20 in an adjacent portion, and a second gate electrode 31 at a position facing the first gate electrode 30. And an inversion layer 13 containing a conductive impurity of the second conductivity type formed in the semiconductor layer 11 in the side region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a charge-coupled device and a method of manufacturing the same.

[0002]

2. Description of the Related Art Charge coupled devices (Charge Coupled devices)
; Hereinafter, referred to as CCD) generally includes an interline system, a frame transfer system, and the like. In the frame transfer method, for example, a plurality of light receiving elements called pixels are formed on the surface of a p-type silicon substrate, and are divided into a light receiving section and a transfer (accumulation) section. A gate electrode is formed on a pixel provided in each section via a gate insulating film. By applying a positive potential to the gate electrode, a potential well is formed on a surface portion, and light is transmitted to a pixel of the light receiving section. When irradiated for a certain time, signal charges proportional to the amount of light are accumulated in the potential well. For example, when a clock voltage pulse having two different timings is applied to the gate electrodes of a plurality of arranged pixels,
The barrier of the potential well is sequentially opened and closed, and the signal charges are sequentially transferred from the light receiving section to the transfer section. Further, the transferred signal charges are output by a clock having a timing different from the clock in the register section, and can be output as a video signal via an output amplifier or the like.
As described above, the CCD can convert an optical signal into a signal charge, and is currently widely used in industrial and consumer imaging devices.

As the above-mentioned CCD, those having various structures such as a two-, three- or four-phase driving type according to the number of clock phases for transferring signal charges have been developed. For example, FIG. 9A is a cross-sectional view of a semiconductor device having a buried channel type single-phase driving CCD having a virtual gate structure. A channel forming region 11 made of a silicon layer containing an n-type conductive impurity is formed on a p-type silicon semiconductor substrate 10, and a gate insulating film 20 of, for example, silicon oxide is formed thereover. A gate electrode 32 made of, for example, polysilicon is formed in an upper layer. An inversion layer 13 containing a p-type conductive impurity is formed in the channel forming region 11 in the gap between the gate electrodes 32, and serves as a virtual gate region. From one gate electrode 32 and one virtual gate,
One CCD cell (also referred to as a pixel) is configured.

In a part of the channel forming region 11 below the gate electrode 32, a region 14 containing an n-type conductive impurity having a higher concentration than the channel forming region 11 is formed, and a PW portion is formed. doing. The region under the gate electrode 32 in the region other than the PW portion is the PB portion. The inversion layer 13 formed in each virtual gate region is fixed at the substrate potential. A region 15 containing a higher concentration of n-type conductive impurities than the channel forming region 11 is formed in a part of the lower layer of the inversion layer 13 to form a VW portion. The region below the inversion layer 13 except for the VW portion is VB
Department.

As described above, the PB, PW, VB,
And one CCD cell from the four phases of the VW section. The lengths of these four phases in the signal charge transfer direction are, for example, 1.4 μm, 2.1 μm, 1.4 μm, and 2.1 μm, respectively, and the total width of one cell is 7.0 μm.

The above PB, PW, VB and V
FIG. 9B shows the potentials of the four phases in the W portion. The gate electrode 32 of each cell is supplied with a common voltage pulse (high (High) and low (Low)), while in the virtual gate region, the gate electrode 32 is not affected by the adjacent gate electrode by the inversion layer 13 and has a constant potential. Become. In other words, the virtual gate region operates in the same manner as the case where there is an electrode having a constant potential even without an electrode. Thus, a semiconductor device having a single-phase drive type CCD is provided. The signal charge changes from the PW portion to the VW portion when the gate electrode 32 changes from high (High) to low (Low), and changes from low (Low) to high (High).
When the state changes to h), the data is transferred from the VW unit to the PW unit.
At this time, the PB unit and V
Part B functions as a barrier to prevent backflow of signal charges,
The PW section and the VW section function as wells for storing signal charges.

A semiconductor device having a buried channel type single-phase driving CCD having the above-described virtual gate structure has a structure in which a polysilicon gate electrode is not provided in a virtual gate region. There is an advantage that the efficiency of signal conversion is high and the sensitivity as a solid-state imaging device is high.

[0008]

However, in view of miniaturization of the semiconductor device and cost reduction, in the semiconductor device having the CCD having the above-mentioned virtual gate structure, it is required to reduce the angle of view, that is, the cell size. Have been. To reduce the cell size, the above PB section, P
The length of each of the four phases W, VB, and VW must be reduced. However, the PB portion and the VB portion, which are barriers for preventing backflow, must have a certain length in order to suppress two-dimensional potential modulation, and therefore, a PW portion for storing signal charges. And the length of the VW section must be further reduced. As a result, there is a problem that it is difficult to sufficiently secure the capacity of the well for storing the signal charges.

Further, as shown in FIG. 9A, ions are selectively implanted into portions indicated by "+" in the boundary between the PB portion and the PW portion and the boundary between the VB portion and the VW portion. , The position of this boundary portion, that is, the length of the PB portion and the VB portion, which are barrier portions, depends on the mask alignment accuracy at the ion implantation level,
Determined by the resist patterning accuracy. The fact that the variation in the process must be suppressed to a certain level or less during mass production is another factor that makes it impossible to shorten the lengths of the PB portion and the VB portion in accordance with the reduction in the cell size.

The present invention has been made in view of the above-mentioned problems, and accordingly, the present invention can reduce the cell size. A semiconductor device having a charge-coupled device (CCD) that does not cause a problem such as a backflow and that can sufficiently secure the capacity of a well for storing signal charges, has a high efficiency of converting an optical signal into an electronic signal, and has a high sensitivity as a solid-state imaging device. And a method for producing the same.

[0011]

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor layer containing a conductive impurity of a first conductivity type formed on a semiconductor substrate; A gate insulating film formed on the upper layer, a first gate electrode formed on the upper layer of the gate insulating film, and a second gate electrode formed on the gate insulating film adjacent to the first gate electrode insulated from the first gate electrode. A gate electrode; and an inversion layer containing a second conductivity type conductive impurity formed in the semiconductor layer in a side region of the second gate electrode at a position facing the first gate electrode.

In the semiconductor device of the present invention, the first gate electrode, the second gate electrode formed adjacent to the first gate electrode, and the virtual side region of the second gate electrode at a position facing the first gate electrode. A charge-coupled device in which one cell is formed by a gate. The virtual gate region is not affected by the adjacent first and second gate electrodes due to the inversion layer containing the conductive impurity of the second conductivity type, and has a constant potential, while the first and second gate electrodes have the same potential. The semiconductor device has a buried channel type two-phase drive type CCD having a virtual gate structure, which can transfer charges by applying different voltage pulses to each of them.

According to the semiconductor device of the present invention, since it has a virtual gate structure, the efficiency of converting an optical signal into an electronic signal is high, and the sensitivity as a solid-state image sensor is high. In addition, since there is no region serving as a barrier for preventing backflow at the time of charge transfer, the size of the cell can be reduced. By controlling the timing of pulses applied to the first gate electrode and the second gate electrode, Backflow can be prevented. In addition, since there is no region serving as a barrier, the entire surface of the semiconductor layer serving as a channel functions as a well, and sufficient capacity of the well for storing signal charges can be secured. Further, the inversion layer serving as a virtual gate region can be formed in a self-aligned manner by ion implantation or the like using the first gate electrode and the second gate electrode as a mask, so that there is no need for a margin for misalignment of the mask.
Cell size can be easily reduced.

Preferably, the above-described semiconductor device of the present invention
The film thickness of the gate insulating film below the first gate electrode is different from the film thickness of the gate insulating film below the second gate electrode, and more preferably, the film thickness of the layer below the first gate electrode. The gate insulating film is formed to be thicker than the gate insulating film below the second gate electrode. With this, even if the potentials of the pulse voltages applied to the first gate electrode and the second gate electrode are set to be the same, the depth of the potential formed by the first gate electrode and the second gate electrode can be made different. The depth of the potential formed by the second gate electrode can be made larger than the depth of the potential formed by the first gate electrode,
Charge transfer can be made smoother.

The semiconductor device of the present invention is preferably
In the semiconductor layer below the second gate electrode, a region containing the first conductive type conductive impurity at a higher concentration than the semiconductor layer is formed. Accordingly, even if the potentials of the pulse voltages applied to the first gate electrode and the second gate electrode are set to be the same, the depth of the potential formed by the second gate electrode is greater than the depth of the potential formed by the first gate electrode. And the charge transfer can be made smoother.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a gate insulating film on a semiconductor substrate; and ion-implanting the first conductive type through the gate insulating film. Forming a semiconductor layer into which impurities are introduced, forming a first gate electrode on the gate insulating film, forming an interlayer insulating film covering the first gate electrode, Forming a second gate electrode on the gate insulating film in a portion adjacent to an electrode, and introducing a second conductive type conductive impurity using the first gate electrode and the second gate electrode as a mask; Forming an inversion layer in the semiconductor layer in a side region of the second gate electrode at a position facing one gate electrode.

The method of manufacturing a semiconductor device according to the present invention described above includes:
A gate insulating film is formed over a semiconductor substrate, and a semiconductor layer into which impurities of a first conductivity type are introduced by ion implantation through the gate insulating film is formed to form a channel formation region. Next, a first gate electrode is formed on the gate insulating film, an interlayer insulating film covering the first gate electrode is formed, and a second gate electrode is formed on the gate insulating film adjacent to the first gate electrode. Form. Next, a conductive impurity of the second conductivity type is introduced using the first gate electrode and the second gate electrode as masks, and the semiconductor layer in the side region of the second gate electrode facing the first gate electrode is introduced into the semiconductor layer. An inversion layer is formed to serve as a virtual gate region.

According to the method of manufacturing a semiconductor device of the present invention, the first gate electrode and the second gate electrode formed adjacent to the first gate electrode are formed.
A charge-coupled device in which one cell is formed by the gate electrode and a virtual gate in a side region of the second gate electrode facing the first gate electrode can be formed. Since it has a virtual gate structure, the efficiency of converting an optical signal into an electronic signal is high, the sensitivity as a solid-state imaging device is high, and there is no barrier region for preventing backflow during charge transfer. Therefore, it is possible to reduce the size of the cell, to prevent the backflow by controlling the timing of the pulse applied to the first gate electrode and the second gate electrode, and to have no barrier region. The entire surface of the semiconductor layer serving as a well functions as a well, sufficient capacity of the well for storing signal charges can be secured, and the inversion layer serving as a virtual gate region is self-aligned by ion implantation using the first and second gate electrodes as a mask. Since there is no need for allowance for misalignment of the mask, the embedded gate having a virtual gate structure can be easily reduced in size. It is possible to manufacture a semiconductor device having a two-phase drive type CCD flannel type.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, after the step of forming the first gate electrode and before the step of forming the second gate electrode, the method further includes a step of thinning the gate insulating film in a region excluding the first gate. Thereby, the thickness of the gate insulating film below the first gate electrode can be made larger than the thickness of the gate insulating film below the second gate electrode, and the thickness of the first gate electrode and the second gate electrode can be reduced. Even if the potential of the applied pulse voltage is set to be the same, the depth of the potential formed by the second gate electrode can be made deeper than the depth of the potential formed by the first gate electrode. A smooth semiconductor device can be manufactured.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, after the step of forming the first gate electrode and before the step of forming the second gate electrode, the conductive impurity of the first conductivity type is introduced using the first gate electrode as a mask. A step of forming a region containing the first conductive type conductive impurity at a higher concentration than the semiconductor layer in the semiconductor layer in a region other than the first gate electrode. Accordingly, a region containing a conductive impurity of the first conductivity type at a higher concentration than the semiconductor layer can be formed in the semiconductor layer below the second gate electrode, and the first gate electrode and the second gate electrode can be formed. Even if the potential of the pulse voltage applied to the electrodes is set to be the same, the depth of the potential formed by the second gate electrode can be made deeper than the depth of the potential formed by the first gate electrode. Can be manufactured.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1A is a sectional view of a semiconductor device according to this embodiment. Channel formation region 1 made of silicon layer containing n-type conductive impurity on p-type silicon semiconductor substrate 10
1, a gate insulating film 20 of, for example, silicon oxide is formed on the upper layer, and a first gate electrode 30 made of, for example, polysilicon is formed on the upper layer. An interlayer insulating film 21 of, for example, silicon oxide is formed to cover the first gate electrode 30. The first of the upper layers
A second gate electrode 31 made of, for example, polysilicon is formed adjacent to the gate electrode 30. An inversion layer 13 containing a p-type conductive impurity is formed in the channel forming region 11 on the side of the second gate electrode 31 at a position facing the first gate electrode 30 and serves as a virtual gate region.
In the channel formation region 11 below the second gate electrode,
A region 12 (indicated by + in the figure) containing an n-type conductive impurity at a higher concentration than the channel formation region 11 is formed. As described above, one CCD cell is constituted by the first gate electrode 31, the second gate electrode 31, and the virtual gate.

The channel formation region 11 under the first gate electrode 30 becomes the P1 portion and contains a higher concentration of n-type conductive impurities than the channel formation region 11 of the channel formation region 11 under the second gate electrode 31. The area 12 to be used is the P2 part. The inversion layer 13 formed in each virtual gate region is fixed at the substrate potential, and this region is
Department.

As described above, part P1, part P2, and V
One CCD cell is formed from the three phases of the P portion. The length of these three phases in the signal charge transfer direction is the same as that of the conventional CCD.
Since it does not have a barrier region such as a cell, for example, each is set to about 1.4 to 2.1 μm and 3
The width of one cell in total of the phases can be reduced to about 5.0 μm.

The above P1, P2, and VP 3
FIG. 1B shows the phase potential. The first gate electrode 30 and the second gate electrode 31 of each cell are supplied with clocked voltage pulses (high (High) and low (Low)) as shown in FIG. On the other hand, in the virtual gate region, the inversion layer 13 is not affected by the adjacent gate electrode and has a constant potential. In other words, the virtual gate region operates in the same manner as the case where there is an electrode having a constant potential even without an electrode. When both the first gate electrode 30 and the second gate electrode 31 are high (High),
The signal charge is stored in the portion P2. Next, after changing the first gate electrode 30 from high (High) to low (Low),
The second gate electrode is changed from high (High) to low (Low). At this time, the signal charges stored in the P2 section are transferred to the VP section. First, the first gate electrode 30 is set high (Hig).
The reason for changing from h) to low is to act as a barrier for preventing backflow of signal charges. Next, the first gate electrode is changed from low (Low) to high (High). At this time, the signal charge is transferred from the VP section to the P1 section. Next, the second gate electrode 31 is changed from low (Low) to high (High). At this time, the signal charges are transferred from the P1 portion to the P2 portion. By applying the pulse voltage clock-controlled as described above to the first gate electrode 30 and the second gate electrode 31, the signal charges do not flow backward.
Can be transferred. At this time, the P1, P2, and VP sections each serve as a well for storing signal charges, and can sufficiently secure the capacity of the well for storing signal charges.

Since the semiconductor device of the present embodiment has a virtual gate structure, the efficiency of converting an optical signal into an electronic signal is high, and the sensitivity as a solid-state imaging device is high. Also,
The inversion layer serving as a virtual gate region can be formed in a self-aligned manner by ion implantation or the like using the first gate electrode and the second gate electrode as a mask. It is easy to reduce the size. Further, a channel formation region 1 under the second gate electrode
In FIG. 1, a region 12 (shown by + in the drawing) containing an n-type conductive impurity at a higher concentration than the channel forming region 11 is formed, so that the region 12 is given to the first gate electrode and the second gate electrode. Even if the potential of the pulse voltage is set to be the same, the depth of the potential of the portion P2 can be made deeper than the depth of the potential of the portion P1, and the second gate electrode 31 can be lowered (L
When the signal charge is changed from “ow” to “high”, the signal charges are quickly transferred from the P1 portion to the P2 portion without backflow, and the transfer of the charges can be made smoother.

The method of manufacturing the semiconductor device according to the present embodiment will be described with reference to the drawings. First, FIG.
As shown in FIG. 1, a thermal oxidation method or a CVD (Chemical Vapor Deposit) is formed on a p-type silicon semiconductor substrate 10.
For example, a silicon oxide layer having a thickness of, for example, 700 ° is formed by an ion (Ion) method and the gate insulating film 20 is formed. next,
For example, an n-type conductive impurity D1 such as phosphorus is ion-implanted over the entire surface to form an n-type channel forming region 11.

Next, as shown in FIG.
A first gate electrode 30 is formed by depositing polysilicon on the gate insulating film 20 by the VD method and patterning the polysilicon by a photolithography process.

Next, as shown in FIG. 3 (c), an n-type conductive impurity D2 such as phosphorus is ion-implanted using the first gate electrode 30 as a mask to form the channel forming region 11.
Region 12 containing a higher concentration of n-type conductive impurities than
(Indicated by + in the figure).

Next, as shown in FIG. 4D, the first gate electrode 30 is formed by, for example, a thermal oxidation method or a CVD method.
To form a silicon oxide layer having a thickness of 500 to 1000 °, and an interlayer insulating film 21 is formed. At this time, according to the thermal oxidation method, since the growth rate of silicon oxide is slow in the upper layer portion of the gate insulating film 20 made of silicon oxide, it is thinner than the interlayer insulating film 21 covering the first gate electrode 30. Can be formed. Then, for example, C
The second gate electrode 31 is formed by depositing polysilicon on the interlayer insulating film 21 by the VD method and patterning the polysilicon by a photolithography process.

Next, as shown in FIG. 4E, a p-type conductive impurity D3 such as boron is ion-implanted using the first gate electrode 30 and the second gate electrode 31 as a mask to form a first gate. The inversion layer 13 containing a p-type conductive impurity is formed in the channel formation region 11 on the side of the second gate electrode 31 at a position facing the electrode 30. Above,
The semiconductor device illustrated in FIG. 1A can be formed.

According to the method of manufacturing a semiconductor device of the present embodiment, the first gate electrode 30, the second gate electrode 31 formed adjacent to the first gate electrode 30, and the first gate electrode 30 at a position facing the first gate electrode 30 are formed. A charge-coupled device in which one cell is formed by the virtual gate in the side region of the two gate electrodes 31 can be formed. Since it has a virtual gate structure, the efficiency of converting an optical signal into an electronic signal is high, the sensitivity as a solid-state imaging device is high, and there is no barrier region for preventing backflow during charge transfer. Therefore, the size of the cell can be reduced, and the first gate electrode 30 and the second gate electrode 3
Backflow can be prevented by controlling the timing of the pulse applied to the channel 1, and since there is no barrier region, the entire surface of the channel forming region 11 functions as a well and the capacity of the well for storing signal charges is reduced. The inversion layer 13 serving as a virtual gate region can be sufficiently secured and can be formed in a self-aligned manner by ion implantation using the first gate electrode 30 and the second gate electrode 31 as a mask. It is possible to manufacture a semiconductor device having a buried channel type two-phase drive type CCD having a virtual gate structure, which does not require a margin and can easily reduce the cell size.

In the method of manufacturing a semiconductor device according to the present embodiment, an n-type conductive impurity is introduced using the first gate electrode 30 as a mask, and the channel forming region 11 excluding the first gate electrode 30 is formed. Region 1 in which n-type conductive impurities are contained at a higher concentration than channel formation region 11
2 (indicated by + in the drawing), even if the potentials of the pulse voltages applied to the first gate electrode 30 and the second gate electrode 31 are set to be the same, the potential of the potential formed by the first gate electrode 30 is reduced. The depth of the potential formed by the second gate electrode 31 can be made deeper than the depth, and a semiconductor device that can transfer charges more smoothly can be manufactured.

Second Embodiment FIG. 5A is a sectional view of a semiconductor device according to this embodiment.
Except for the fact that a region containing a higher concentration of n-type conductive impurities than the channel forming region 11 is not formed in the channel forming region 11 below the second gate electrode 31, the other regions are substantially the same. Similar to the semiconductor device of the first embodiment, one CCD cell is formed from three phases, P1, P2, and VP. The length of these three phases in the signal charge transfer direction is, for example, about 1.4 to 2.1 μm, respectively, because they do not have a barrier region as in a conventional CCD cell. The width of one cell can be reduced to about 5.0 μm.

The above P1, P2, and VP 3
FIG. 5B shows the phase potential. Clock-controlled voltage pulses (high (High) and low (Low)) as shown in FIG. 6 are applied to the first gate electrode 30 and the second gate electrode 31 of each cell, respectively. Unlike the first embodiment, since a region containing a higher concentration of n-type conductive impurities than the channel forming region 11 is not formed, the potential difference between the P1 portion and the P2 portion when the potential is high (High). To generate (Hig)
At time h), a higher voltage is applied to the second gate electrode 31 than to the first gate electrode 30. When the voltage is low (Low), the first gate electrode 30 and the second gate electrode 31 have the same voltage. Therefore, when the voltage is low (Low), the height of the potential is the same in the P1 portion and the P2 portion. In the semiconductor device of the present embodiment having the above potential, the first
By the same clock control as in the embodiment, the signal charges can be transferred without flowing backward. Also, P1 part, P2
The unit and the VP unit each function as a well for storing signal charges, and can sufficiently secure the capacity of the well for storing signal charges. Further, because of the virtual gate structure, the efficiency of converting an optical signal into an electronic signal is high, and the sensitivity as a solid-state imaging device is high. The inversion layer 1 serving as a virtual gate region
3 can be formed in a self-aligned manner by ion implantation or the like using the first gate electrode 30 and the second gate electrode 31 as a mask.
The cell size can be easily reduced.

In the semiconductor device according to the present embodiment, the region containing the n-type conductive impurity at a higher concentration than the channel forming region 11 is not formed. It can be formed in the same manner as the method.

Third Embodiment FIG. 7A is a sectional view of a semiconductor device according to this embodiment.
The gate insulating film 20 under the first gate electrode 30 is formed at, for example, 1200 °, and the gate insulating film is thicker than the second gate electrode 31 having a thickness of, for example, 700 ° and the gate insulating film 20 in the virtual gate region. The semiconductor device of the second embodiment is substantially the same as the semiconductor device of the second embodiment except that a portion 20 ′ is formed and the film thickness is increased.
One CCD cell is formed from three phases, one part, P2 part, and VP part. The lengths of these three phases in the signal charge transfer direction are, for example, 1.4 to 2.
Assuming about 1 μm, the width of one cell in total of three phases is 5.0 μ
m.

The above P1, P2, and VP sections
FIG. 7B shows the phase potential. The gate insulating film 20 under the first gate electrode 30 is a thick film portion 20 '.
And is thicker than the second gate electrode 31 and the gate insulating film 20 in the virtual gate region, so that the first gate electrode 30 and the second gate electrode 30 at the time of high (High) are
Even if the potential of the pulse voltage applied to the gate electrode 31 is set to be the same, the depth of the potential of the portion P2 can be made deeper than that of the potential of the portion P1, and the charge transfer can be made smoother. When the voltage is low (Low), the first gate electrode 30 and the second gate electrode 31 have the same voltage. Therefore, when the voltage is low (Low), the height of the potential is the same in the P1 portion and the P2 portion. Also in the semiconductor device of the present embodiment having the above potential, the second
By the same clock control as in the embodiment, the signal charges can be transferred without flowing backward. Also, P1 part, P2
The unit and the VP unit each function as a well for storing signal charges, and can sufficiently secure the capacity of the well for storing signal charges. Further, because of the virtual gate structure, the efficiency of converting an optical signal into an electronic signal is high, and the sensitivity as a solid-state imaging device is high. The inversion layer 1 serving as a virtual gate region
3 can be formed in a self-aligned manner by ion implantation or the like using the first gate electrode 30 and the second gate electrode 31 as a mask, so that there is no need for a margin for misalignment of the mask, and the cell size can be easily reduced. Can be.

In the semiconductor device of the present embodiment, for example, the gate insulating film 20 is formed with a thickness of 1200 °,
After forming the first gate electrode 30, the first gate electrode 30
For example, the gate insulating film 20 in the region excluding the above is thinned to a film thickness of 700 ° by 500 ° etching by RIE (reactive ion etching) or the like, and otherwise the same as the method of manufacturing the semiconductor device of the second embodiment. Can be formed.

Fourth Embodiment FIG. 8A is a sectional view of a semiconductor device according to the fourth embodiment .
The second gate electrode 31 is formed on the gate insulating film 20, the interlayer insulating film 21 is formed on the second gate electrode 31, and the first gate electrode is formed on the upper layer adjacent to the second gate electrode 31. Except for this, the rest is substantially the same as the semiconductor device of the first embodiment.

In the semiconductor device of the present embodiment, for example, after the gate insulating film 20 is formed, the second gate electrode 3 is formed first.
1 is formed, then the interlayer insulating film 21 is formed, and then the first
Otherwise, by forming the gate electrode 30 or changing the order of the ion implantation process, the others can be formed in the same manner as the method of manufacturing the semiconductor device of the first embodiment.

The present invention is not limited to the above embodiment. For example, the first gate electrode and the second gate electrode have a single-layer structure, but may have a structure of two or more layers. Also,
Materials constituting the gate electrode and other members other than those described in the above embodiment can be used. Others
Various changes can be made without departing from the spirit of the present invention.

[0043]

According to the semiconductor device of the present invention, the cell size can be reduced, and even if the cell size is reduced, the signal charge does not cause a problem such as a backflow when transferring the signal charge. It is possible to provide a semiconductor device having a charge-coupled device (CCD) that can sufficiently secure the capacity of a storage well, has a high efficiency of converting an optical signal into an electronic signal, and has high sensitivity as a solid-state imaging device.

According to the method of manufacturing a semiconductor device of the present invention, the above-described semiconductor device of the present invention can be easily manufactured, the cell size can be reduced, and even if the cell size is reduced. A charge-coupled device that does not cause problems such as backflow when transferring signal charges, can sufficiently secure the capacity of wells for storing signal charges, has high efficiency in converting optical signals into electronic signals, and has high sensitivity as a solid-state imaging device (CCD) can be manufactured.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a schematic diagram showing the potential of the device shown in FIG. 1A.

FIG. 2 is a timing chart showing clock control for performing charge transfer of the semiconductor device shown in FIG. 1;

FIGS. 3A and 3B are cross-sectional views showing a manufacturing process of the method for manufacturing the semiconductor device shown in FIG. 1A. FIG. 3A shows a process up to an ion implantation process for forming a channel formation region, and FIG. Until the step of forming the first gate electrode, (c) shows an ion implantation step for forming a region containing n-type conductive impurities at a higher concentration than the channel formation region.

FIG. 4 shows a step that follows the step shown in FIG. 3;
(E) shows up to the step of forming the gate electrode and up to the step of forming the inversion layer.

FIG. 5A is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention, and FIG. 5B is a schematic diagram showing a potential of the device shown in FIG. 5A.

FIG. 6 is a timing chart showing clock control for performing charge transfer of the semiconductor device shown in FIG. 5;

7A is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention, and FIG. 7B is a schematic diagram illustrating a potential of the device illustrated in FIG. 7A.

8A is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention, and FIG. 8B is a schematic diagram illustrating a potential of the device illustrated in FIG. 8A.

9A is a cross-sectional view of a conventional semiconductor device, and FIG. 9B is a schematic diagram showing a potential of the device shown in FIG. 9A.

[Explanation of symbols]

10: semiconductor substrate, 11: channel formation region, 12, 1
4, 15: a region containing impurities at a higher concentration than the channel formation region; 13: inversion layer; 20: gate insulating film;
0 ': thick portion of the gate insulating film, 21: interlayer insulating film, 30
... First gate electrode, 31... Second gate electrode, 32.

Claims (7)

[Claims] A semiconductor layer containing a conductive impurity of a first conductivity type formed on a semiconductor substrate; a gate insulating film formed on the semiconductor layer; and a gate insulating film formed on the gate insulating film. A first gate electrode, a second gate electrode insulated from the first gate electrode and formed on an upper layer of the gate insulating film adjacent to the first gate electrode, and a second gate electrode at a position facing the first gate electrode. And an inversion layer containing a conductive impurity of the second conductivity type formed in the semiconductor layer in the side region. 2. The semiconductor device according to claim 1, wherein a thickness of said gate insulating film below said first gate electrode is different from a thickness of said gate insulating film below said second gate electrode. 3. The semiconductor according to claim 2, wherein a thickness of said gate insulating film below said first gate electrode is formed larger than a thickness of said gate insulating film below said second gate electrode. apparatus. 4. A semiconductor device according to claim 1, wherein said semiconductor layer under said second gate electrode has a region containing said first conductive type conductive impurity at a higher concentration than said semiconductor layer.
3. The semiconductor device according to any one of 3. 5. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a semiconductor layer containing a first conductivity type impurity by ion implantation through the gate insulating film, and an upper layer of the gate insulating film. Forming a first gate electrode, forming an interlayer insulating film covering the first gate electrode, and forming a second gate electrode on the gate insulating film adjacent to the first gate electrode. And introducing a second conductive type conductive impurity using the first gate electrode and the second gate electrode as a mask, and forming a side region of the second gate electrode at a position facing the first gate electrode. Forming an inversion layer in the semiconductor layer. 6. After the step of forming the first gate electrode,
6. The method according to claim 5, further comprising, before the step of forming the second gate electrode, a step of thinning the gate insulating film in a region excluding the first gate. 7. After the step of forming the first gate electrode,
Prior to the step of forming the second gate electrode, the first gate electrode is used as a mask to introduce the first conductivity type conductive impurity into the semiconductor layer in a region excluding the first gate electrode. 7. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of forming a region containing a conductive impurity of one conductivity type at a higher concentration than the semiconductor layer.