JPH11250168A - Square number calculation circuit, composite deferential amplifier circuit and multiplier using these circuits - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a square number calculation circuit having a square characteristic over the whole operation input voltage range that can be realized on a semiconductor integrated circuit. SOLUTION: A MOS differential pair is formed by MOS transistors(TRs) M1, M2 of which sources are mutually connected. Input voltage V1 is impressed between the gates of the TRs M1, M2. MOS TRs M3, M4 are respectively connected to the TRs M1, M2 as their loads. A tripple tail cell is formed by a constant current source 1 and MOS TRs M5 to M7 of which sources are mutually connected. Constant voltage Vc is impressed to the gate of the TR M7. Two output voltages V01 , V02 from the MOS differential pair are respectively impressed to the gates of the TRs M5, M6. A 1st output current I<+> is taken out from the drain of the TR M7 and a 2nd output current I is taken out from the drains of the TRs M5, M6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a squaring circuit, a composite differential amplifying circuit, and a multiplying circuit which can be suitably implemented on a semiconductor integrated circuit. The present invention relates to a squaring circuit, a composite differential amplifying circuit and a multiplying circuit having good linearity over the entire operating input voltage range.

[0002]

2. Description of the Related Art FIG. 19 shows a conventional squaring circuit disclosed in Japanese Patent Application Laid-Open No. Hei 6-195484. This circuit is based on MOS (Metal-Oxide-Semico) invented by the same inventor.
nductor) Give quadratic cells a squared characteristic,
It can be used as a squaring circuit. MO
To give the S quadretail cell a square characteristic, a midpoint voltage of the input voltage is required.
In the example disclosed in 195484, a resistance adder as shown in FIG. 17 is used as an input circuit.

In FIG. 19, four n-channel MOS field effect transistors (MOS Fi)
eld-Effect Transistor, MOSFET) (hereinafter referred to as MO
M101, M102, M10
3, M104 is driven by the constant current source 101 (current value: I ₀ ), and forms a quadrilateral cell. Here, the tail current is I ₀ .

[0004] MOS transistors M101, M102,
The gates of M103 and M104 each constitute an input terminal of the quadrature cell. The sources of the MOS transistors M101, M102, M103, and M104 are commonly connected to one terminal of the constant current source 101, and the other terminal of the constant current source 101 is grounded.

The drains of the MOS transistors M101 and M104 are connected to each other, and further connected to a power supply voltage line to which the power supply voltage V _DD is applied via a load resistor (resistance value: R _L ). MOS transistor M connected
The drains of 101 and M104 are
It constitutes one terminal of the output terminal pair of the cell.

The drains of the MOS transistors M102 and M103 are also connected to each other, and further connected to a power supply voltage line via a load resistor (resistance value: R _L ). The drains of the connected MOS transistors M102 and M103 constitute the other terminal of the pair of output terminals of the quadrature cell.

[0007] Two resistors having an equal resistance value R connected in series constitute a resistance adder. Both ends of this resistance adder are connected to MOS transistors M102 and M103.
Are connected to the respective gates. The intermediate point of this resistance adder is commonly connected to the gates of the MOS transistors M101 and M104.

[0008] The differential input voltage V _i, since applied to both ends of the resistor adder, MOS transistors M102 and M
Between 103 gate is directly applied differential input voltage V _i, the gate of the MOS transistor M101 and M104, the midpoint voltage of the differential input voltage V _i (V _i / 2) is applied.

Here, the currents flowing through the drains of the commonly connected MOS transistors M102 and M103 are represented by I ⁺ ,
MOS transistors M101 and M104 commonly connected
If that, the differential output current [Delta] I ^- a current flowing through the drain I (= I ⁺ -I ^-) is the square of the differential input voltage V _i (V _i ²⁾
Is proportional to In other words, this quad retail cell
It has the function of squaring circuit to the differential input voltage V _i.

A commonly connected MOS transistor M10
When the current I ⁺ is converted into a voltage by a load resistor connected to the drain of the transistor 2 and M103, an output voltage _VO1 is obtained.
Similarly, when the current I ⁻ is converted into a voltage by a load resistor connected to the drains of the commonly connected MOS transistors M101 and M104, an output voltage V _O2 is obtained. The differential output voltage ΔV (= V _O1 −V _O2 ) is also proportional to the square of the input voltage V _i (V _i ² ). Therefore, in the differential output voltage [Delta] V, the function of squaring circuit is obtained for the differential input voltage V _i.

As a conventional multiplying circuit, a quarter-square type multiplying circuit constituted by combining two squaring circuits (see Japanese Patent Application Laid-Open No. Hei 6-195484) or the above-mentioned MOS quadrature cell as a multiplier core circuit is used. And an input circuit for generating a voltage input to four input terminals of the MOS quadrature cell from two input voltages to be multiplied (Japanese Patent Laid-Open No. 8-83).
No. 314).

[0012]

In the conventional squaring circuit shown in FIG. 19, although the standardized operating input voltage range of the MOS quadrilateral cell is in the range of -2 to +2, a square characteristic is obtained. The standardized input voltage range is-(2 /
3) ^1/2 (-0.8165) to + (2/3) ^1/2 (+
0.8165). That is, there is a problem that the input voltage range having the square characteristic is only over 40% of the operating input voltage range.

Similarly, in the conventional multiplying circuit, the input voltage range having good linearity is 40 times the operating input voltage range.
There is a problem that it is only a little over 80%.

It is an object of the present invention to provide a squaring circuit having a square characteristic over the entire operating input voltage range.

Another object of the present invention is to provide a composite differential amplifier circuit capable of obtaining a differential output voltage linear with respect to two input voltages over the entire operating input voltage range.

Another object of the present invention is to provide a composite differential amplifier circuit suitable as an input circuit of a multiplication circuit.

Yet another object of the present invention is to provide a multiplier circuit having good linearity over the entire operating input voltage range.

Still another object of the present invention is to provide a multiplication circuit having a transconductance having good linearity with respect to two input voltages.

[0019]

(1) The first squaring circuit of the present invention comprises: (a) first and second source-coupled circuits;
A MOS differential pair formed by the first and second MOS transistors and having an input voltage applied between the gates of the first and second MOS transistors;
The first M connected to the drain of the OS transistor
A third MOS transistor operating as a load of the OS transistor; (c) a fourth MOS transistor connected to the drain of the second MOS transistor and operating as a load of the second MOS transistor; and (d).
A triple tail cell formed by source coupled fifth, sixth and seventh MOS transistors, wherein the fifth, sixth and seventh MOS transistors are driven by a single tail current. (E) a constant voltage is applied to the gate of the seventh MOS transistor;
(F) a first output voltage of the MOS differential pair generated at a drain of the first MOS transistor is applied to a gate of the fifth MOS transistor;
A second output voltage of the MOS differential pair generated at a drain of the second MOS transistor is applied to a gate of the MOS transistor, and (g) a drain of the fifth MOS transistor and a drain of the sixth MOS transistor are connected to each other. To form a first output terminal,
The drain of the seventh MOS transistor forms a second output terminal, and (h) an output of the squaring circuit is taken out from one of the first and second output terminals.

(2) In the first squaring circuit of the present invention, M
Third and fourth MOS transistors are used as loads of the first and second MOS transistors that constitute the OS differential pair. Therefore, the first and second output voltages of the MOS differential pair having the square characteristic with respect to the input voltage are compressed by the third and fourth MOS transistors operating as loads. As a result, the difference between the first and second output voltages (that is, the MO
The differential output voltage of the S differential pair is linear with respect to the input voltage.

The MO is linear with respect to the input voltage.
The differential output voltage of the S differential pair is applied between the gates (the input terminal pair of the triple tail cell) of the fifth and sixth MOS transistors forming the triple tail cell. At the same time, the gate of the seventh MOS transistor (triple-tail
A second constant voltage is applied to the control terminal of the cell. Therefore, the current flowing through the drain of the seventh MOS transistor (that is, the first output terminal of the squaring circuit) increases in proportion to the square of the input voltage, and the connected drains of the fifth and sixth MOS transistors (that is, the square) The current flowing through the second output terminal of the circuit) decreases in proportion to the square of the input voltage.

Thus, the first and second circuits of the squaring circuit
, An output current proportional to the square of the input voltage is generated.

These output currents generated at the first and second output terminals of the squaring circuit have square characteristics over the entire operating input voltage range. This is because the operating input voltage range of the MOS differential pair having the third and fourth MOS transistors as loads matches the operating input voltage range of the MOS triple tail cell.

(3) The second squaring circuit of the present invention comprises:
(A) a MOS differential pair formed by source-coupled first and second MOS transistors and having an input voltage applied between the gates of the first and second MOS transistors; A third MOS transistor connected to the drain of the first MOS transistor and operating as a load of the first MOS transistor;
(C) a fourth MOS transistor connected to the drain of the second MOS transistor and operating as a load of the second MOS transistor; and (d) a fifth, sixth, seventh and eighth MOS transistors coupled to the source. And a quadri-tail cell wherein the fifth, sixth, seventh and eighth MOS transistors are driven with a single tail current; and (e) the seventh and eighth MOS transistors (F) a first output voltage of the MOS differential pair generated at the drain of the first MOS transistor is applied to the gate of the fifth MOS transistor; and The gate of the sixth MOS transistor
The second output voltage of the MOS differential pair generated is applied to the drain of the second MOS transistor, and (g) the drain of the fifth MOS transistor and the sixth MOS
The drains of the transistors are connected to each other to form a first output terminal, while the drains of the seventh MOS transistor and the eighth MOS transistor are connected to each other to form a second output terminal; An output of the circuit is taken out from one of the first and second output terminals.

(4) The second squaring circuit of the present invention is obtained by replacing the triple tail cell of the first squaring circuit of the present invention with a quadritail cell.

The differential output of the MOS differential pair, which is linear with respect to the input voltage, is provided between the gates (the input terminal pair of the quadrilateral cell) of the fifth and sixth MOS transistors constituting the quadritail cell. A voltage is applied. This is the same as the case of the first squaring circuit of the present invention.

On the other hand, the gates of the seventh and eighth MOS transistors that constitute the quadrature cell are connected to each other to form a control terminal of the quadrature cell. A second constant voltage is applied to the common connection gate. Therefore, this is also substantially the same as the case of the first squaring circuit of the present invention.

Thus, in the second squaring circuit of the present invention, as in the case of the first squaring circuit of the present invention, the first
And a second output terminal generates an output current proportional to the square of the input voltage. These output currents have a square characteristic over the entire operating input voltage range.

(5) The first composite differential amplifier circuit of the present invention comprises: (a) first and second source-coupled MOS transistors;
A first MOS differential pair formed by transistors and having a first input voltage applied between the gates of the first and second MOS transistors; and (b) the first M
The first M connected to the drain of the OS transistor
A third MOS transistor operating as a load of the OS transistor; (c) a fourth MOS transistor connected to the drain of the second MOS transistor and operating as a load of the second MOS transistor; and (d).
The fifth and sixth MOS transistors are formed by source-coupled fifth and sixth MOS transistors.
A second MOS differential pair to which a second input voltage is applied between the gates of the S transistors, and (e) a seventh MOS transistor connected to the drain of the fifth MOS transistor and operating as a load of the fifth MOS transistor;
(F) an eighth MOS transistor connected to the drain of the sixth MOS transistor and operating as a load of the sixth MOS transistor; and (g) formed by source-coupled ninth and tenth MOS transistors. A third input voltage applied between the gates of the ninth and tenth MOS transistors;
A MOS differential pair, and (h) an eleventh MOS transistor connected to a drain of the ninth MOS transistor and operating as a load of the ninth MOS transistor;
(I) a twelfth MOS transistor connected to a drain of the tenth MOS transistor and operating as a load of the tenth MOS transistor;
The gates of the seventh and eighth MOS transistors are commonly applied with a first output voltage of the first MOS differential pair generated at the drain of the first MOS transistor, and are connected to the eleventh and twelfth MOS transistors. The second output voltage of the first MOS differential pair generated at the drain of the second MOS transistor is commonly applied to the gate of the MOS transistor, and (k) the fifth, sixth, ninth, and tenth The first, second, third, and fourth output voltages of the composite differential amplifier circuit are respectively extracted from the drain of the MOS transistor.

(6) In the first composite differential amplifier circuit of the present invention, the first MOS differential pair formed by the source-coupled first and second MOS transistors has the third and fourth MOS transistors as loads. , The first and second output voltages of the first MOS differential pair are proportional to the square roots of the drain currents of the first and second MOS transistors, respectively.

Similarly, the source coupled fifth and sixth
Of the second MOS differential pair formed by the second MOS differential pair uses the seventh and eighth MOS transistors as loads.
And the output voltage generated at the drain of the sixth MOS transistor, that is, the first and second output voltages of the composite differential amplifier circuit are proportional to the square roots of the drain currents of the fifth and sixth MOS transistors, respectively. .

Further, the ninth and first source-coupled
Since the third MOS differential pair formed by the zero MOS transistor uses the eleventh and twelfth MOS transistors as its load, the drains of the ninth and tenth MOS transistors of the third MOS differential pair are used. , The third and fourth output voltages of the composite differential amplifier circuit are connected to the ninth and tenth MOS transistors, respectively.
It is proportional to the square root of the drain current of the transistor.

Here, the first MOS differential pair constituting the first MOS differential pair
The difference between the square root of the drain current of the second MOS transistor and the square root of the drain current of the second MOS transistor is the above-mentioned (2)
As described above, the voltage is proportional to the first input voltage applied to the first MOS differential pair. Similarly, the difference between the square roots of the drain currents of the fifth and sixth MOS transistors forming the second MOS differential pair is proportional to the second input voltage applied to the second MOS differential pair.

Therefore, when a difference is made between the first, second, third and fourth output voltages of the composite differential amplifier circuit so that the nonlinear term is eliminated, the difference current becomes the first. Or it is proportional to the second input voltage. Therefore, a linear differential output voltage is obtained with respect to the first and second input voltages.

This linear differential output voltage is obtained over the entire operating input voltage range. This is because the operating input voltage range of the first MOS differential pair matches the operating input voltage range of the second and third MOS differential pairs.

Further, the first, second, third and fourth output voltages of the composite differential amplifier circuit can be set in a suitable form as an input voltage to the multiplier circuit. It can be suitably used as an input circuit of a multiplication circuit.

(7) The second composite differential amplifier circuit according to the present invention comprises: (a) first and second source-coupled MOS transistors;
A first MOS differential pair formed by transistors and having a first input voltage applied between the gates of the first and second MOS transistors; and (b) the first M
The first M connected to the drain of the OS transistor
A third MOS transistor operating as a load of the OS transistor; (c) a fourth MOS transistor connected to the drain of the second MOS transistor and operating as a load of the second MOS transistor; and (d).
The fifth and sixth MOS transistors are formed by source-coupled fifth and sixth MOS transistors.
A second MOS differential pair to which a second input voltage is applied between the gates of the S transistors, and (e) a seventh MOS transistor connected to the drain of the fifth MOS transistor and operating as a load of the fifth MOS transistor;
(F) an eighth MOS transistor connected to the drain of the sixth MOS transistor and operating as a load of the sixth MOS transistor; and (g) formed by source-coupled ninth and tenth MOS transistors. A third input voltage applied between the gates of the ninth and tenth MOS transistors;
A MOS differential pair, and (h) an eleventh MOS transistor connected to a drain of the ninth MOS transistor and operating as a load of the ninth MOS transistor;
(I) a twelfth MOS transistor connected to a drain of the tenth MOS transistor and operating as a load of the tenth MOS transistor;
The first output voltage of the first MOS differential pair generated at the drain of the first MOS transistor is commonly applied to the gates of the seventh and twelfth MOS transistors. The second output voltage of the first MOS differential pair generated at the drain of the second MOS transistor is commonly applied to the gate of the MOS transistor, and (k) the fifth, tenth, sixth, and ninth The first, second, third, and fourth output voltages of the composite differential amplifier circuit are respectively extracted from the drain of the MOS transistor.

(8) The second composite differential amplifier circuit of the present invention is the same as the first composite differential amplifier circuit of the present invention, except that
The polarity at the time of applying the second input voltage to the OS differential pair is 2M
The polarity corresponds to the reverse of the polarity when the second input voltage is applied to the OS differential pair.

Therefore, for the same reason as described in the first composite differential amplifier circuit of the present invention, a differential output voltage linear with respect to the first and second input voltages over the entire operating input voltage range. can get. Further, the composite differential amplifier circuit can be suitably used as an input circuit of a multiplier circuit.

(9) In a preferred example of the first and second composite differential amplifier circuits of the present invention, the first and second MOS transistors forming the first MOS differential pair are:
The fifth and sixth MOS transistors forming the second MOS differential pair have the same polarity as the ninth and tenth MOS transistors forming the third MOS differential pair. In this case, since it can be constituted only by MOS transistors having the same polarity, there is an advantage that the circuit configuration is simplified.

In another preferred embodiment of the first and second composite differential amplifier circuits of the present invention, the first and second MOS transistors forming the first MOS differential pair are connected to the second MOS differential pair. The fifth and sixth MOs forming
The S transistor and the ninth and tenth MOS transistors forming the third MOS differential pair have opposite polarities. In this case, there is an advantage that the power supply voltage can be lowered.

In still another preferred embodiment of the first and second composite differential amplifier circuits according to the present invention, the first and second MOS transistors forming the first MOS differential pair include the first and second MOS transistors. The fifth and sixth MOS transistors having the same polarity as the third and fourth MOS transistors operating as the load of the second MOS transistor and forming the second MOS differential pair are the fifth and sixth MOS transistors. The ninth and tenth MOS transistors having the same polarity as the seventh and eighth MOS transistors operating as the load of the sixth MOS transistor and forming the third MOS differential pair are connected to the ninth and tenth MOS transistors. It has the same polarity as the eleventh and twelfth MOS transistors operating as loads of the ten MOS transistors. In this case, since it can be constituted only by MOS transistors having the same polarity, there is an advantage that the circuit configuration is simplified.

In still another preferred embodiment of the first and second composite differential amplifier circuits according to the present invention, the first and second MOS transistors forming the first MOS differential pair include the first and second MOS transistors. The fifth and sixth MOS transistors forming the second MOS differential pair have polarities opposite to those of the third and fourth MOS transistors operating as loads of the second MOS transistor. The ninth and third MOS differential pairs forming the third MOS differential pair have polarities opposite to those of the seventh and eighth MOS transistors operating as loads of the sixth and sixth MOS transistors.
And the tenth MOS transistor have polarities opposite to those of the eleventh and twelfth MOS transistors operating as loads of the ninth and tenth MOS transistors. In this case, there is an advantage that the power supply voltage can be lowered.

(10) A third composite differential amplifier circuit according to the present invention comprises: (a) converting a first input voltage applied to an input terminal pair to obtain a difference between the first input voltage and the first input voltage proportional to the first input voltage; A first voltage-current conversion circuit for outputting a dynamic output current to an output terminal pair; and (b) a load of the first voltage-current conversion circuit connected to the output terminal pair of the first voltage-current conversion circuit, respectively. And (c) converting a second input voltage applied to the input terminal pair and outputting a second pair of differential output currents proportional to the second input voltage to the output terminal. A second voltage-current conversion circuit for outputting to the pair, and (d) third and operation circuits respectively connected to the output terminal pair of the second voltage-current conversion circuit and operating as loads of the second voltage-current conversion circuit. A fourth bipolar transistor, and (e) an input terminal Wherein it is applied to the paired second
A third voltage-current conversion circuit for converting an input voltage and outputting a third pair of differential output currents proportional to the second input voltage to an output terminal pair; and (f) a third voltage-current conversion circuit. Fifth and sixth bipolar transistors respectively connected to the output terminal pair and operating as loads of the third voltage-current conversion circuit; and (g) the third and fourth bipolar transistors.
The first output voltage of the first voltage-to-current conversion circuit generated by one of the first pair of differential output currents of the first voltage-to-current conversion circuit is commonly applied to the base of the bipolar transistor. In addition, the bases of the fifth and sixth bipolar transistors are connected to the second of the first voltage-current conversion circuit generated by the other of the first pair of differential output currents of the first voltage-current conversion circuit. (H) first and second output voltages of the composite differential amplifier circuit are respectively taken out from an output terminal pair of the second voltage-current conversion circuit, and (h) the third voltage-current The third and fourth output voltages of the composite differential amplifier circuit are respectively extracted from the output terminal pair of the conversion circuit.

(11) The third composite differential amplifier circuit of the present invention is the same as that of the first composite differential amplifier circuit of the present invention.
A differential pair and a MOS transistor as a load are connected to a voltage −
This corresponds to a current conversion circuit and a bipolar transistor, respectively.

Therefore, for the same reason as described in the first composite differential amplifier circuit of the present invention, a differential output voltage linear with respect to the first and second input voltages over the entire operating input voltage range. can get. Further, the composite differential amplifier circuit can be suitably used as an input circuit of a multiplier circuit.

(12) A fourth composite differential amplifier circuit according to the present invention comprises: (a) converting a first input voltage applied to an input terminal pair to a difference between the first pair in proportion to the first input voltage; A first voltage-current conversion circuit for outputting a dynamic output current to an output terminal pair; and (b) a load of the first voltage-current conversion circuit connected to the output terminal pair of the first voltage-current conversion circuit, respectively. And (c) converting a second input voltage applied to the input terminal pair and outputting a second pair of differential output currents proportional to the second input voltage to the output terminal. A second voltage-current conversion circuit for outputting to the pair, and (d) third and operation circuits respectively connected to the output terminal pair of the second voltage-current conversion circuit and operating as loads of the second voltage-current conversion circuit. A fourth bipolar transistor, and (e) an input terminal Wherein it is applied to the paired second
A third voltage-current conversion circuit for converting an input voltage and outputting a third pair of differential output currents proportional to the second input voltage to an output terminal pair; and (f) a third voltage-current conversion circuit. A fifth bipolar transistor connected to the output terminal pair and operating as a load of the third voltage-current conversion circuit, and (g) the third and sixth bipolar transistors.
The first output voltage of the first voltage-to-current conversion circuit generated by one of the first pair of differential output currents of the first voltage-to-current conversion circuit is commonly applied to the base of the bipolar transistor. In addition, the bases of the fourth and fifth bipolar transistors are connected to the second of the first voltage-current conversion circuit generated by the other of the first pair of differential output currents of the first voltage-current conversion circuit. (H) first and third output voltages of the composite differential amplifier circuit are respectively taken out from an output terminal pair of the second voltage-current conversion circuit, and the third voltage-current The second and fourth output voltages of the composite differential amplifier circuit are respectively taken out from the output terminal pair of the conversion circuit.

(13) The fourth composite differential amplifier circuit of the present invention is the same as that of the second composite differential amplifier circuit of the present invention.
A differential pair and a MOS transistor as a load are connected to a voltage −
This corresponds to a current conversion circuit and a bipolar transistor, respectively.

Therefore, for the same reason as described in the first composite differential amplifier circuit of the present invention, a differential output voltage linear with respect to the first and second input voltages over the entire operating input voltage range. can get. Further, the composite differential amplifier circuit can be suitably used as an input circuit of a multiplier circuit.

(14) The first multiplying circuit of the present invention is a quarter-square type multiplying circuit, wherein (a) first, second and second input voltages corresponding to the input first and second input voltages, respectively.
An input circuit that outputs third and fourth output voltages;
(B) the first, second, and second signals output from the input circuit;
(C) a first squaring circuit in which two of the third and fourth output voltages are respectively input to the input terminal pair;
A second squaring circuit that receives two other voltages of the first, second, third, and fourth output voltages output from the input circuit, respectively, to an input terminal pair; )
The output terminal pair of the first squaring circuit and the output terminal pair of the second squaring circuit are connected to each other to form a differential output terminal pair. (E) each of the first and second squaring circuits according to the first aspect of the present invention, wherein a differential output including a multiplication result of the input voltage of 2 is taken out.
Alternatively, it is characterized by comprising a second squaring circuit.

(15) In the first multiplication circuit of the present invention,
Since the first and second squaring circuits are each constituted by the first or second squaring circuit of the present invention having a square characteristic over the entire operating input voltage range, good linearity over the entire operating input voltage range. have. Also, the first
Alternatively, the transconductance has good linearity with respect to the second input voltage.

(16) In a preferred example of the first multiplication circuit of the present invention, the input circuit comprises a resistance adder. In this case, there is an advantage that the circuit configuration is simplified.

(17) The second multiplication circuit of the present invention comprises:
(A) an input circuit that outputs first, second, third, and fourth output voltages corresponding to the input first and second input voltages; and (b) the input circuit that is output from the input circuit. A first squaring circuit in which two of the first, second, third, and fourth output voltages are respectively input to an input terminal pair; and (c) the first and second output circuits output from the input circuit. A second squaring circuit in which the other two voltages of the second, third and fourth output voltages are respectively input to the input terminal pair; and (d) an output terminal pair of the first squaring circuit. The output terminal pair of the second squaring circuit is connected to each other to form a differential output terminal pair, and the differential output terminal pair includes a differential signal including a multiplication result of the first and second input voltages. In a quarter-square type multiplication circuit from which an output is taken out, (e) the input circuit Be comprised of any of the first to fourth composite differential amplifier circuit of the invention is characterized in.

(18) In the second multiplication circuit of the present invention,
Since the input circuit is constituted by any of the first to fourth composite differential amplifier circuits of the present invention having a good linearity over the entire operation input voltage range, a good linearity is provided over the entire operation input voltage range. Have sex. Further, the transconductance has good linearity with respect to the first or second input voltage.

(19) The third multiplying circuit of the present invention comprises:
12. A multiplication circuit comprising: (a) an input circuit; and a multiplier core circuit that receives an output of the input circuit and outputs a multiplication result. (B) The input circuit according to any one of claims 3 to 11, (C)
The multiplier core circuit is formed by first, second, third and fourth transistors having an emitter or a source coupled thereto, wherein the first, second, third and fourth transistors are a single transistor. (D) wherein the bases or gates of the first, second, third and fourth transistors are the first, second, and third cells of the quadrilateral cell, respectively. (E) collectors or drains of the second and third transistors are connected together to form a first and a second input terminal, respectively,
And the collectors or drains of the first and fourth transistors are connected together to form a second output terminal of the quadrature cell, and (f) input first and fourth input terminals. First, second, and second signals output from the composite differential amplifier circuit according to a second input voltage.
Third and fourth output voltages are respectively input to the first, second, third and fourth input terminals of the quadrilateral cell, and (g) the first and second output voltages of the quadrilateral cell. A differential output including a result of multiplication of the first and second input voltages is taken out from the second output terminal.

(20) In the third multiplication circuit of the present invention,
A multiplier core circuit comprising a quadrilateral cell comprising first, second, third and fourth transistors;
Since the input circuit is composed of any one of the first to fourth composite differential amplifier circuits of the present invention, the operating input voltage range is set for the same reason as described for the second composite differential amplifier circuit of the present invention. Has good linearity throughout. Further, the transconductance has good linearity with respect to the first or second input voltage.

[0057]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
2 shows the MOS squaring circuit of the embodiment.

This squaring circuit is formed by a MOS differential pair formed by two source-coupled n-channel MOS transistors M1 and M2 and three source-coupled n-channel MOS transistors M5, M6 and M7. It has a triple-tail cell.

The sources of the MOS transistors M1 and M2 forming the MOS differential pair are a constant current source 1 (current value: I _SS ).
Grounded. This MOS differential pair is driven by the constant current I _SS generated by the constant current source 1.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M1 and M2 is K ₁ times that of the unit MOS transistor (K ₁ is a constant, but K ₁ is a constant). ₁ ≧ 1).

[0062] The gate of the MOS transistors M1, M2 forms an input terminal pair of the squaring circuit, the input voltage V _i is applied between their gate.

The n-channel MOS transistor M3 is
It operates as a load of the OS transistor M1. The source of the MOS transistor M3 is connected to the drain of the MOS transistor M1, the drain is connected to a power supply voltage line to which the power supply voltage V _DD is applied, and the bias voltage (DC constant voltage) V _B is applied to the gate.

The n-channel MOS transistor M4 is
It operates as a load of the OS transistor M2. The source of the MOS transistor M4 is connected to the drain of the MOS transistor M2, the drain is connected to a power supply voltage line to which the power supply voltage V _DD is applied, and the gate is the same bias voltage V _B as applied to the MOS transistor M3. Is applied.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M3 and M4 is K ₂ times that of the unit MOS transistor (K ₂ is a constant, but K ₂ is a constant). ₂ ≧ 1).

The sources of the n-channel MOS transistors M5, M6 and M7 forming a triple tail cell are grounded via a constant current source 2 (current value: I ₀ ). The triple-tail cell is driven by a constant current I ₀ which generates the constant current source 2, the constant current I ₀ is the tail current.

The gates of the MOS transistors M5 and M6 are connected to the drains of the MOS transistors M1 and M2, respectively. The drains of the MOS transistors M5 and M6 are connected to each other, and
Form output terminals.

The first output voltage V _O1 of the MOS differential pair generated at the drain of the transistor M1 is applied to the gate of the MOS transistor M5. The second output voltage V _O2 of the MOS differential pair generated at the drain of the transistor M2 is applied to the gate of the MOS transistor M6. The difference between these two output voltages V _O1 and V _O2 (ie,
The differential output voltage of the MOS differential pair) becomes the input voltage of the triple tail cell.

A control voltage (DC constant voltage) V _C is applied to the gate of the MOS transistor M7. The drain of the MOS transistor M7 forms the second output terminal of the squaring circuit.

The ratio (W / L) of the gate width (W) to the gate length (L) of the MOS transistors M5 and M6 is equal to the unit MOS.
Equal to that of a transistor. MOS transistor M7
The ratio (W / L) of the gate width (W) to the gate length (L) is
It is K ₃ times that of the unit MOS transistor (K ₃ is a constant, but K ₃ ≧ 1).

Two n-channel MOS transistors M1
0A, M10B and constant current source 3 (current value: I _SS ) constitute a control voltage generation circuit that generates a control voltage V _C applied to the triple tail cell. MOS transistor M1
0A, sources of M10B, drains, they are connected to each other both gates are in their gates DC constant voltage V _B is commonly applied. The drains of the MOS transistors M10A and M10B are connected to a power supply voltage line. MOS transistors M10A, M10B
Are commonly connected to one end of the constant current source 3.

The control voltage V _C is equal to the source voltage of the commonly connected MOS transistors M10A and M10B.
In other words, the control voltage V _C is generated at the sources of the commonly connected MOS transistors M10A and M10B.
The gate of the MOS transistor M7 of the triple tail cell is connected to the commonly connected MOS transistor M10.
A, are connected to the sources of M10B.

(Operation Principle) Next, the operation principle of the squaring circuit of the first embodiment shown in FIG. 1 will be described.

Assuming that the relationship between the drain current I _D and the gate-source voltage V _GS of the MOS transistor operating in the saturation region obeys the square law, ignoring the body effect and channel length modulation, the drain current I _D Is the following equation (1
a) and (1b).

[0075]

(Equation 1)

In equations (1a) and (1b), K is
Gate width (W) and gate length (L) of MOS transistor
Ratio (W / L) to that of a unit MOS transistor, β is a transconductance parameter, V _TH
Is the threshold voltage.

Assuming that the effective mobility of carriers is μ and the capacitance of the gate oxide film per unit area is C _OX , the transconductance parameter β is defined as β = μ (C _OX / 2) (W / L).

The effective mobility μ of the carrier changes according to the following equation (2) according to the absolute temperature T.

[0079]

(Equation 2)

The transconductance parameter β is also
It changes according to the following equation (3) according to the absolute temperature T.

[0081]

(Equation 3)

Is obtained.

However, in the equations (3) and (4), the suffix 300 represents μ, β, T at 300 K (= 27 ° C.).
Shows the value of

(A) MOS differential pair Assuming that the matching between the elements is good, two output currents of the MOS differential pair, that is, the MOS transistors M1 and M2
Of the drain currents I _D1 and I _D2 of
a) It is represented as (4b).

[0085]

(Equation 4)

The drain currents I _D1 and I _D2 of the MOS transistors M1 and M2 represented by the equations (4a) and (4b) are the MOS transistors M3 and M4 serving as loads, respectively.
Is converted to a voltage by the square root (root) compression.
That is, assuming that the differential output voltage of the MOS differential pair is ΔV, ΔV is expressed as follows, where A is a constant.

[0087]

(Equation 5)

Here, a and b are constants, x is a variable,
Consider the following identity (6).

[0089]

(Equation 6)

Then, in the identity (6), a, b, x
Is set as follows.

[0091]

(Equation 7)

Then, the left side of the identity expression (6) is equal to the value obtained by substituting the expressions (4a) and (4b) into the expression (5). At this time, the right side of the identity (5) is (K ₁ β) ^1/2
V _i . Therefore, the following equation (8) holds.

[0093]

(Equation 8)

As is apparent from equation (8), MO
The differential output voltage ΔV of the S differential pair, that is, equation (4a)
The difference between the square root of the square root and the drain current I _D2 of the drain current I _D1 represented by (4b) is proportional to the input voltage V _i.

Note that the differential output current of the MOS differential pair is ΔI
When _D, [Delta] I _D by using the drain current I _D1, I _D2 is expressed by the following equation (9).

[0096]

(Equation 9)

Therefore, the differential output current ΔI of the MOS differential pair
_D is the linear term

[0098]

(Equation 10)

And the nonlinear term

[0100]

[Equation 11]

It can be seen that the following is included.

[0102] When the MOS transistor M1, the voltage of the combined source of M2 forming the MOS differential pair and a common source voltage V _S1, the common source voltage V _S1 is the following formula (1
It is expressed as 2).

[0103]

(Equation 12)

[0104] In Equation (12), V _CM1 is the common mode voltage of the input voltage V _i is the input differential.

As can be seen from equation (12), since the common source voltage V _S1 is a function of the input voltage V _i , the common source voltage V _S1 fluctuates with the input voltage V _i . Further, the third term (square root term) of the equation (12) is equal to (1/2) ^1/2 of the second square root of the nonlinear term (11).
Therefore, the nonlinear term (11) of the differential output current [Delta] I _D of the MOS differential pair is found to be due to variations of the common source voltage V _S1.

This corresponds to the common source voltage V of the MOS differential pair.
_{If S1} can be fixed at a constant voltage, it means that the MOS differential pair can be operated linearly.

The output voltages V _O1 and V _O2 of the MOS differential pair having the MOS transistors M3 and M4 as loads are generated at the drains of the MOS transistors M1 and M2, respectively, as shown in the following equations (13a) and (13b). Is represented by

[0108]

(Equation 13)

Therefore, the differential output voltage ΔV of the MOS differential pair
Is represented by the following equation (14).

[0110]

[Equation 14]

In the equation (14), the ratio K ₂ between the gate width (W) and the gate length (L) of the load MOS transistors M3 and M4 is determined by the gate width of the MOS transistors M1 and M2 forming the MOS differential pair. (W) and gate length (L)
If larger ratio K _1, this MOS differential pair becomes a reverse-phase attenuator, K ₂ is if equal or K ₁ is smaller than the K _1, this MOS differential pair is an amplifier of the opposite phase.

[0112] (14) As is apparent from the equation, the differential output voltage ΔV of the MOS differential pair of MOS transistors M3, M4 and the load is proportional to the input voltage V _i. In other words, a MOS having the MOS transistors M3 and M4 as loads
The differential pair operates as a linear attenuator or amplifier for the input voltage V _i . If (K ₂ / K ₁ ) is set to a small value, a high gain can be realized.

Assuming that the common mode voltage of the output voltages V _O1 and V _O2 is V _CM2 , V _CM2 is represented by the following equation (15).

[0114]

(Equation 15)

From equation (15), it can be seen that the MOS transistor M
3, the output voltages V _O1 and V of the MOS differential pair with M4 as a load.
_O2 common mode voltage V _CM2 is equal to common source voltage V
It can be seen that _S1 (see the above equation (12)) is used.

(B) MOS Triple Tail Cell Next, the MOS transistor M5, M6, M7
The operation of the OS triple tail cell will be described.

The output current of the MOS triple-tail cell is disclosed in Japanese Patent Application Laid-Open Nos. 8-83314, 8-84037, 8-315056 by the same inventor.

In the squaring circuit of the first embodiment shown in FIG.
The output voltages V _O1 and V _O1 are connected to the gates of the MOS transistors M5 and M6 forming the input terminal pair of the triple tail cell.
_O2 is input respectively. In other words, the differential output voltage ΔV of the MOS differential pair is input between the gates of the MOS transistors M5 and M6. Therefore, the differential output current ΔI _TRIPLE of this triple tail cell is expressed as ΔI _TRIPLE = I _D5 −I _{D6 where} the drain currents of the MOS transistors M5 and M6 are I _D5 and I _D6 , respectively.

Therefore, according to Japanese Patent Application Laid-Open No. 8-83314, this triple tail
The differential output current ΔI _TRIPLE of the cell is represented by the following equation (16).

[0120]

(Equation 16)

Here, the differential output voltage ΔV of the MOS differential pair input between the gates of the MOS transistors M5 and M6
Is linear with respect to the input voltage V _i to the MOS differential pair (ie, the squaring circuit), and
Considering that each of the drain currents I _D5 and I _D6 of the MOS transistors M5 and M6 forming the cell has a square characteristic with respect to the input voltage ΔV to the triple tail cell, the square circuit of FIG. In order to output a current having characteristics, the differential output current ΔI _TRIPLE of this triple tail cell represented by the equation (16) becomes linear with respect to the input voltage ΔV, in other words, the input voltage ΔV It is necessary to be proportional.

That is, if c is a constant, it is necessary that ΔI _TRIPLE = cΔV holds.

Therefore, the coefficient of ΔV of the numerator in the equation (16) must be equal to the constant c. That is, the following equation (17) must be satisfied.

[0124]

[Equation 17]

At this time, the differential output current ΔI _TRIPLE of the triple tail cell is as follows.

[0126]

(Equation 18)

When the control voltage V _C at this time is obtained from the equation (17), the following equation (19) is obtained.

[0128]

[Equation 19]

Therefore, the differential output current ΔI _TRIPLE of this triple tail cell expressed by the above equation (16) becomes linear with respect to the input voltage ΔV, ie, the current having the square characteristic in the squaring circuit of FIG. Is output, the control voltage V _C must be set so that the equation (19) is satisfied. And the triple tail at that time
The differential output current ΔI _TRIPLE of the cell is represented by the above equation (18).

For example,

[0131]

(Equation 20)

At this time, the control voltage V _C needs to be set as follows.

[0133]

(Equation 21)

As described above, if the control voltage V _C to the MOS transistor M7 of the triple tail cell is set so that the above equation (19) holds, the above equation (1)
6), the differential output current I ⁻ of this triple tail cell becomes linear with respect to the input voltage ΔV. Then, the differential output current ΔI _TRIPLE is expressed by the above equation (18).

By the way, in the squaring circuit shown in FIG.
Since the MOS differential pair having the S transistors M3 and M4 as loads and the MOS triple tail cells are cascaded, the respective gate voltages of the MOS transistors M5, M6 and M7 forming the triple tail cells are V _O1 ,
V _O2 , (V _CM2 + V _C ). If the gate voltage (V _CM2 + V _C ) = V _{G7 of} the MOS transistor M7 becomes a constant value, the gate bias circuit for generating the control voltage V _C can be greatly simplified. Therefore, next, the conditions necessary for that are obtained.

The common mode voltage V of the output voltages V _O1 and V _O2
CM2 is represented by the above equation (15), and since the control voltage V _C satisfies the above equation (19), the MOS transistor M7
Gate voltage V _G7 = (V _CM2 + V _C ) is _calculated by the following equation (2)
It is expressed as 2). Here, d is a constant.

[0137]

(Equation 22)

As described above, in order for the squaring circuit of FIG. 1 to output a current having a square characteristic, the differential output current ΔI _TRIPLE of the triple tail cell needs to be proportional to its input voltage ΔV. Therefore, in equation (22), the coefficients of the term including the input voltage ΔV must all be zero. That is, equation (22) must be simplified as in equation (23).

[0139]

(Equation 23)

The condition required to satisfy the expression (23) is as follows in the expression (22):
(24b) is satisfied.

[0141]

(Equation 24)

Therefore, these relational expressions (24a) and (2a)
As 4b) is satisfied, when setting values such as the current value I _0, I _SS is established equation (23) is, the gate voltage V _G7 of a MOS transistor _{M7 = (V CM2 + V C} ) is constant Value. As a result, the bias circuit for generating the control voltage V _C for the MOS transistor M7 is greatly simplified as shown in FIG. And in that case,
Control voltage V _C in the circuit configuration of FIG. 1 is the equation (1
9), the differential output current ΔI of this triple tail cell is expressed by the equation (18).
_TRIPLE becomes linear with respect to the input voltage ΔV.

As described above in "(a) MOS differential pair", the input voltage .DELTA.V to the MOS triplet cell is the difference between the MOS differential pair having the MOS transistors M3 and M4 as loads. is the kinematic output voltage [Delta] V, is proportional to the input voltage V _i to the squaring circuit.

In this manner, the squaring circuit of FIG. 1 converts the output current ΔI _TRIPLE having a square characteristic with respect to the input voltage V _i into M
It is confirmed that the signal is output as the differential output current of the OS triple tail cell.

In this case, the triple tail cell formed by MOS transistors M5, M6 and M7 operates as an adaptive bias differential pair as disclosed in Japanese Patent Application Laid-Open No. 6-152275 by the same inventor. I do.

(C) Operation Input Voltage Range Next, the operation input voltage range of the squaring circuit of FIG. 1 will be described.

The drain currents I _D5 and I _D6 of the MOS transistors M5 and M6 forming the triple tail cell each have a square characteristic with respect to the input voltage ΔV to the triple tail cell.
The drain currents I _D5 , I _D6 , and I _D7 of _M5 , M6, and M7 are represented by the following equations (25a), (25b), and (25c), respectively.

[0148]

(Equation 25)

[0149] effective tail current of the MOS triple-tail cell of the differential of the two constituting the pair MOS transistors M5, M6, the output current I of the triple-tail cell ^- equally, the drain current I _D5 And I _D6 . Therefore, the following Expression (26) is obtained using Expressions (25a) and (25b).

[0150]

(Equation 26)

As is clear from equations (25c) and (26), the two output currents I ⁺ and I ⁻ of the triple tail cell
Are proportional to the square of their input voltage ΔV, so that their output currents I ⁺ and I ⁻ are both equal to their input voltage ΔV.
It has an ideal square characteristic for V.

Next, a condition is determined in which the linear input voltage range of the MOS triple tail cell and the operating input voltage range of the MOS differential pair are equal.

First, if none of the MOS transistors M5, M6 and M7 forming the MOS triple tail cell pinch off, the two output voltages V _O1 and V _{O2 of} the MOS differential pair and the control voltage V _C are respectively The following equation (27
a), (27b) and (27c).

[0154]

[Equation 27]

The expressions (27a) and (27b) are the same as the expressions (13a) and (13b).

When I _D1 = I _SS and I _D2 = 0, the above equation (2)
7a), (27b) and (27c) are as follows.

[0157]

[Equation 28]

[0158] When the formula (28a) is substituted into the equation (25a), the following equation (29) is obtained for I _D5.

[0159]

(Equation 29)

When formula (29) is arranged, the following formula (3) is obtained.
0).

[0161]

[Equation 30]

Similarly, equation (28b) is replaced by equation (25)
Substituting in b), the following equation (31) is obtained for I _D6.

[0163]

(Equation 31)

By rearranging the equation (31), the following equation (3) is obtained.
It looks like 2).

[0165]

(Equation 32)

By subtracting equation (30) from equation (32),
The following equation (33) is obtained.

[0167]

[Equation 33]

Equation (33) indicates that the MOS triple tail
It shows the maximum value of the differential input voltage ΔV to the cell.

On the other hand, the minimum value of the differential input voltage ΔV is I _D2 =
It is obtained when I _SS and I _D1 = 0, and ΔV at that time is as follows.

[0170]

(Equation 34)

Therefore, it can be seen that the range of the differential input voltage ΔV is expressed as follows.

[0172]

(Equation 35)

Further, the equation (28c) is converted to the equation (25)
Substituting in c), the following equation (36) is obtained for I _D7.

[0174]

[Equation 36]

The equation (36) is added to the equation (32).
By substituting (33) and solving this, the following equation (37) is obtained.

[0176]

(37)

Accordingly, the current values I, 2, 3 of the constant current source
_0, I _SS and, by setting the value of the ratio K ₂ thereto of unit MOS transistor of the ratio of the gate width to the gate length of the MOS transistor so as to satisfy the formula (37), the linear input voltage of the MOS triple-tail cell The range is equal to the operating input voltage range of the MOS differential pair. As a result, in the squaring circuit of FIG. 1, an ideal squaring characteristic is obtained over the entire operating input voltage range of the squaring circuit.

In this case, the MOS triple tail cell of FIG. 1 operates as an adaptive bias differential pair having the largest linear input voltage range.

The circuit configuration of the squaring circuit shown in FIG. 1 can be most simplified, for example, K ₁ = K ₂ = 1, K ₃ = 2, and I _SS = I _0.
/ 2. At this time, the value of the constant c is

[0180]

(38)

Is obtained.

[0182] Equation (38) satisfies the above equation (19), respectively the control voltage V _C constant d at this time, the following equation (39a), so that the (39 b).

[0183]

[Equation 39]

(Second Embodiment) FIG. 2 shows a MOS squaring circuit according to a second embodiment of the present invention. This squaring circuit is obtained by replacing the n-channel MOS transistor M7 with a combination of two n-channel MOS transistors M7A and M7B in the squaring circuit of the first embodiment shown in FIG. In other words, the triple-tail cell in the squaring circuit of the first embodiment shown in FIG. 1 is replaced with a quadri-tail cell. Otherwise, the configuration is the same as that of the squaring circuit of FIG. 1. Therefore, in FIG. 2, the same or corresponding elements as those of the squaring circuit of FIG.

The ratio (W / L) of the gate width (W) to the gate length (L) of the MOS transistors M7A and M7B is
The same as the transistors M5 and M6, each having the unit M
Equal to that of the OS transistor. Therefore, four MOs
Each of the S transistors M5, M6, M7A, and M7B is a unit transistor.

Since the sources, drains and gates of the MOS transistors M7A and M7B are all connected to each other, the two MOS transistors M7A and M7B are connected to each other.
M7B is the ratio of gate width (W) to gate length (L) (W /
L) is equivalent to one MOS transistor M7, which is twice as large as that of the unit MOS transistor. In other words, in the squaring circuit of FIG. 1, from the above relational expression (24a), K
₃ = 2, the MOS transistor M in FIG.
7 is divided into two unit MOS transistors M7A and M7B.

The drains of the MOS transistors M7A and M7B are connected to each other to form one output terminal of the squaring circuit. An output current I ⁺ is obtained from the output terminal.

_Assuming that the drain currents of the MOS transistors M7A and M7B are I _D7A and I _D7B , respectively, the output current I
⁺ Is represented by the following equation (40).

[0189]

(Equation 40)

The drain currents I _D5 and I _D6 are the same as those in the first embodiment, and are calculated by the above equations (25a) and (25b).
It is represented by Output current I ^- is represented by the equation (26).

[0191] As is apparent from equation (40) (26), two output currents of the quad retail cell I ⁺ and I ^- are both proportional to the square of the input voltage [Delta] V. Therefore,
The square circuit of FIG. 2 also has an ideal square characteristic with respect to the input voltage ΔV.

By satisfying the condition of the above equation (37) for making the linear input voltage range of the quadrilateral cell equal to the operating input voltage range of the MOS differential pair,
Its ideal square characteristic is obtained over the entire operating input voltage range.

[0193] Figure 3, the common mode voltage V with respect to the input voltage V _i, the output voltage V _O1, V _O2 output voltage when the K ₂ = K ₁ = 1 in the MOS differential pair in FIG. 1 and FIG. 2 Show changes in _CM2 . From FIG. 3, the MOS transistor M
It can be seen that the output voltages V _O1 and V _{O2 of the} MOS differential pair composed of M1 and M2 have ideal square characteristics over the entire standardized input voltage range.

FIG. 4 shows that K ₂ = K ₁ in the squaring circuit of FIG.
The drain current of the to to the input voltage V _i of the MOS differential pair if, quad retail cell I _D5, I _{D6,
I D7A, I D7 B, (} I D5 + I D6), (I D7A + I D7B),
(I _D5 + I _D7A), shows changes in (I _D6 + I _D7B). FIG.
Thus, the output currents I ⁺ = (I _D5 + I _D6 ) and I ⁻ = (I _D7A +
It can be seen that both I _D7B ) have good linear characteristics over the standardized operating input voltage range.

(Third Embodiment) FIG. 5 shows a MOS composite differential amplifier circuit according to a third embodiment of the present invention. This composite differential amplifier circuit uses the MOS transistors used in the first and second embodiments.
In this example, three MOS differential pairs using transistors as loads are used.

In FIG. 5, two source-coupled n
The channel MOS transistors M11 and M12 are connected to the first MO
Form an S differential pair. MOS transistors M11, M1
The source 2 is grounded via a constant current source 11 (current value: I ₀ ). This first MOS differential pair includes a constant current source 1
It is driven by a constant current I ₀ which generates the.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M11 and M12 is K ₁ times that of the unit MOS transistor (K ₁ is a constant; ₁ ≧ 1).

[0198] The gate of the MOS transistor M11, M12 forms a first input terminal pair of the composite differential amplifier circuit, the first input voltage V _x is applied between their gate.

The n-channel MOS transistor M13 is
It operates as a load of the MOS transistor M11. MO
The source of the S transistor M13 is connected to the drain of the MOS transistor M11, and the drain is connected to the power supply voltage V _DD.
There is connected to the power supply voltage line to be applied, the bias voltage (direct current constant voltage) V _B is applied to the gate.

The n-channel MOS transistor M14 is
It operates as a load of the MOS transistor M12. MO
The source of the S transistor M14 is connected to the drain of the MOS transistor M12, and the drain is connected to the power supply voltage V _DD.
Is connected to the power supply voltage line to which
The same bias voltage V _B as applied to the transistor M13 is applied.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M13 and M14 is K ₂ times that of the unit MOS transistor (K ₂ is a constant, and K ₂ is a constant). ₂ ≧ 1).

Source-coupled two n-channel MOS
The transistors M15 and M16 form a second MOS differential pair. The sources of the MOS transistors M15 and M16 are grounded via a constant current source 12 (current value: I ₀ ). The first 2MOS differential pair is driven by a constant current I ₀ which generates the constant current source 12.

[0203] The ratio of the MOS transistors M15, M16 of the gate width (W) and gate length (L) (W / L) is a _1-fold that of K in any unit MOS transistor.

The gates of the MOS transistors M15 and M16 form the second input terminal pair of the composite differential amplifier circuit, and the second input voltage _Vy is applied between the gates.

The n-channel MOS transistor M17 is
It operates as a load of the MOS transistor M15. MO
The source of the S transistor M17 is connected to the drain of the MOS transistor M15, and the drain is connected to the power supply voltage V _DD.
Is connected to the power supply voltage line to which the voltage is applied, and the gate is connected to the drain of the MOS transistor M11. MOS
The output voltage V _O1 of the first differential pair is applied to the gate of the transistor M17.

The n-channel MOS transistor M18 is
It operates as a load of the MOS transistor M16. MO
The source of the S transistor M18 is connected to the drain of the MOS transistor M16, and the drain is connected to the power supply voltage V _DD.
Is applied to the power supply voltage line, and the gate is connected to the drain of the MOS transistor M12. MOS
The output voltage V _O1 of the first differential pair is applied to the gate of the transistor M18, similarly to the MOS transistor M17.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M17 and M18 is K ₄ times that of the unit MOS transistor (K ₄ is a constant, and K ₄ is a constant). ₄ ≧ 1).

Two n-channel MOSs Source-Coupled
The transistors M19 and M20 form a third MOS differential pair. The sources of the MOS transistors M19 and M20 are grounded via a constant current source 13 (current value: I ₀ ). This third MOS differential pair is driven by a constant current I ₀ generated by a constant current source 13.

[0209] The ratio of the MOS transistor M19, the gate width of M20 (W) and gate length (L) (W / L) is a _1-fold that of K in any unit MOS transistor.

[0210] MOS transistors M19, M20 same second input voltage V _y and the 2MOS differential pair between the gate of the is applied.

The n-channel MOS transistor M21 is
It operates as a load of the MOS transistor M19. MO
The source of the S transistor M21 is connected to the drain of the MOS transistor M19, and the drain is connected to the power supply voltage V _DD.
Is applied to the power supply voltage line, and the gate is connected to the drain of the MOS transistor M12. MOS
The output voltage V _O2 of the first differential pair is applied to the gate of the transistor M21.

The n-channel MOS transistor M22 is
It operates as a load of the MOS transistor M20. MO
The source of the S transistor M22 is connected to the drain of the MOS transistor M20, and the drain is connected to the power supply voltage V _DD.
Is applied to the power supply voltage line, and the gate is connected to the drain of the MOS transistor M12. MOS
The output voltage V _O2 of the first differential pair, which is the same as the second MOS differential pair, is applied to the gate of the transistor M22.

[0213] The ratio of the MOS transistors M21, M22 of the gate width (W) and gate length (L) (W / L) are all ₄ times that of K of unit MOS transistor.

The first, second, third, and fourth output voltages V ₁ , V ₂ , and V 3 of the composite differential amplifier circuit of the third embodiment shown in FIG.
V ₃ and V ₄ are MOS transistors M15, M16, M1
9, taken out from the drain of M20.

Next, the operation principle of the composite differential amplifier circuit of the third embodiment will be described.

Assuming that the drain currents of the MOS transistors M11 and M12 are I _D11 and I _D12 , respectively, the output voltages V _O1 and V _O2 of the first MOS differential pair with the MOS transistors M13 and M14 as loads are given by the following equations ( 41
a) and (41b).

[0219]

[Equation 41]

Formulas (41a) and (41b) are respectively
Equations (13a) and (13a) described in the first embodiment
Substantially the same as b).

The first and second output voltages V ₁ and V ₂ of the composite differential amplifier circuit are generated at the drains of the MOS transistors M15 and M16 of the second MOS differential pair, respectively. Assuming that the drain currents of the MOS transistors M15 and M16 are _ID15 and _ID16 , respectively, the above equation (41)
Using a) and (41b), V ₁ and V ₂ are represented by the following equations (42a) and (42b), respectively.

[0220]

(Equation 42)

[0221] Similarly, the third and fourth output voltages V _3, V ₄ of the composite differential amplifier circuit, the first 3MOS differential pair MO
It is generated at the drain of each of the S transistors M19 and M20. MOS transistors M19, M20 of the drain current, respectively I _D19, When I _{D 20,} the above equation (41a), (41b) with a, V _3, V ₄ each following formula (43a), (43b) It is represented as

[0222]

[Equation 43]

Since the first, second and third MOS differential pairs all use MOS transistors as loads, their differential output voltages (V _O1 −V _O2 ), (V ₂ −V ₁ ), (V ₄
−V ₃ ) is proportional to the corresponding input voltages V _x , V _y . That is, the following equations (44a), (44b), and (44c) hold similarly to the above equation (18).

[0224]

[Equation 44]

Equations (41a), (41b) and (42)
a), (42b), (43a), and (43b) are expressed by the formula (4).
4a), (44b) and (44c), the term of the drain current is eliminated, and the following equations (45a) and (45c) are obtained.
b), (45c) and (45d) are obtained.

[0226]

[Equation 45]

Equation (45a) represents the differential output voltage (V ₂ −
V ₁₎ or applying (V ₄ -V ₃₎ shows that it is equivalent to applying the second input voltage V _y. Also shows that equation (45b) is applying the differential output voltage (V ₃ -V ₁₎ or (V ₄ -V ₂₎ is equivalent to applying the first input voltage V _x . Formula (45c)
Applies the differential output voltage (V ₄ −V ₁ )
Indicating that it and is equivalent to apply a sum of the input voltage V _x and the second input voltage V _y. Equation (45d) indicates that applying a differential output voltage (V ₃ -V ₂₎ is equivalent to applying a difference between the first input voltage V _x and the second input voltage V _y.

[0228] Thus, according to the MOS composite differential amplifier circuit of the third embodiment, the linear variety of differential output voltage to at least one of the first input voltage V _x and the second input voltage V _y is can get. The differential output voltage is set by appropriately setting the values of the constants K ₁ , K ₂ , and K ₄ , and the first to fourth output voltages V ₁ , V ₂ , V ₃ , and V ₄ are appropriately set. Can be easily changed and selected.

In addition, these linear differential output voltages are:
Obtained over the entire operating input voltage range. that is,
This is because the operating input voltage range of the first MOS differential pair matches the operating input voltage range of the second and third MOS differential pairs.

When configuring a multiplication circuit, the first to be multiplied
Input voltage V _x and not only the second input voltage V _y, often their sum and difference are required. If the composite differential amplifier circuit of the third embodiment is used as an input circuit of a multiplication circuit,
By appropriately setting the values of the constants K ₁ , K ₂ and K ₄ ,
A desired input voltage can be easily obtained. Therefore, the composite differential amplifier circuit can be suitably used as an input circuit of a multiplication circuit.

(Fourth Embodiment) FIG. 6 shows a MOS composite differential amplifier circuit according to a fourth embodiment of the present invention. This composite differential amplifier circuit is different from the composite differential amplifier circuit of the third embodiment described above in that the input destination of the output voltage V _O1 of the first MOS differential pair is the same as that of the third MOS transistor M17 of the second MOS differential pair.
Instead of the MOS transistor M22 of the MOS differential pair, the first
The input destination of the output voltage V _O2 of the MOS differential pair is determined by the MOS transistor M18 of the second MOS differential pair and the M transistor of the third MOS differential pair.
This is changed to the OS transistor M21. The other configuration is the same as that of the composite differential amplifier circuit of FIG. 5, and therefore, in FIG. 6, the same or corresponding elements as those of the composite differential amplifier circuit of FIG.

The composite differential amplifier circuit according to the fourth embodiment has a third
The polarity for the application of the second input voltage V _y polarities for the application of the second input voltage V _y to a 2MOS differential pair corresponding to those in the opposite to the MOS differential pair. Therefore, the following equations (46a), (46b), (46c), and (46d) are obtained in the same manner as in the composite differential amplifier circuit of the third embodiment.

[0233]

[Equation 46]

(46a), (46b), (46c),
(46d) is obtained by the above-described equations (45a), (45b),
This is the same as (45c) and (45d), and therefore, the composite differential amplifier circuit of the fourth embodiment is equivalent to the composite differential amplifier circuit of the third embodiment.

Therefore, also in the composite differential amplifier circuit of the fourth embodiment, the first and second input voltages V _x and V _y are used for the same reason as described in the composite differential amplifier circuit of the third embodiment. Are obtained over the entire operating input voltage range. Further, the composite differential amplifier circuit can be suitably used as an input circuit of a multiplier circuit.

(Fifth Embodiment) FIG. 7 shows a MOS composite differential amplifier circuit according to a fifth embodiment of the present invention.

This composite differential amplifier circuit is similar to the aforementioned third differential amplifier circuit.
In the composite differential amplifier circuit of the embodiment, the n-channel MOS transistors M11 and M12 of the first MOS differential pair
N-channel MOS operating as a load of a second MOS differential pair instead of channel MOS transistors M31 and M32
Transistors M17 and M18 are replaced with p-channel MOS transistors M37 and M38, and n-channel MOS transistors M21 operating as loads of a third MOS differential pair are provided.
M22 is replaced by p-channel MOS transistors M41, M42
In place of That is, the second and third MOs
The polarity (n channel) of the MOS transistor forming the S differential pair is opposite to the polarity (p channel) of the MOS transistor forming the first MOS differential pair.

According to this structure, the gate-source voltage of each MOS transistor becomes parallel (does not overlap) between the power supply voltage line and the ground, so that there is an advantage that the power supply voltage can be reduced.

In FIG. 7, two source-coupled p
The channel MOS transistors M31 and M32 are connected to the first MO
Form an S differential pair. MOS transistors M31, M3
The source 2 is connected to a power supply voltage line to which the power supply voltage V _DD is applied via a constant current source 21 (current value: I ₀ ). The first MOS differential pair is driven by a constant current I ₀ generated by a constant current source 21. MOS transistor M
The drains of M31 and M32 are grounded via constant current sources 22 and 23 (both have a current value of 2I ₀ ).

[0240] The ratio of the MOS transistors M31, M32 of the gate width (W) and gate length (L) (W / L) is a _1-fold that of K in any unit MOS transistor.

[0241] The gate of the MOS transistor M31, M32 forms a first input terminal pair of the composite differential amplifier circuit, the first input voltage V _x is applied between their gate.

The n-channel MOS transistor M33 is
It operates as a load of the MOS transistor M31. MO
The source of the S transistor M33 is connected to the drain of the MOS transistor M31, the drain is connected to the power supply voltage line, and the gate is bias voltage (DC constant voltage) V _B
Is applied.

[0243] The n-channel MOS transistor M34 is
It operates as a load of the MOS transistor M32. MO
The source of the S transistor M34 is connected to the drain of the MOS transistor M32, the drain is connected to the power supply voltage line, gate the same bias voltage V _B as applied to the MOS transistor M33 is applied.

[0244] The ratio of the MOS transistors M33, M34 of the gate width (W) and gate length (L) (W / L) are both _twice that of K of unit MOS transistor.

Source-coupled two n-channel MOS
The transistors M35 and M36 form a second MOS differential pair. The sources of the MOS transistors M35 and M36 are
It is grounded via a constant current source 24 (current value: I ₀ ). The first 2MOS differential pair is driven by a constant current I ₀ which generates the constant current source 24. MOS transistor M
The drains of 35 and M36 are connected to power supply voltage lines via constant current sources 25 and 26 (both have a current value: I ₀ ).

[0246] The ratio of the MOS transistors M35, M36 of the gate width (W) and gate length (L) (W / L) is a _1-fold that of K in any unit MOS transistor.

The gates of the MOS transistors M35 and M36 form a second input terminal pair of the composite differential amplifier circuit, and the second input voltage _Vy is applied between the gates.

P channel MOS transistors M37, M
38 operates as loads on the MOS transistors M35 and M36, respectively. MOS transistors M37, M3
The source of 8 is connected to the drains of the MOS transistors M35 and M36, respectively. The gates of the MOS transistors M37 and M38 are connected to the drains of the MOS transistors M31 of the first differential pair, and the output voltage V _O1 of the first differential pair is commonly applied to the gates. M
The drains of the OS transistors M37 and M38 are connected to each other.

[0249] The ratio of the MOS transistors M37, M38 of the gate width (W) and gate length (L) (W / L) are all ₄ times that of K of unit MOS transistor.

Source-coupled two n-channel MOS
The transistors M39 and M40 form a third MOS differential pair. The sources of the MOS transistors M39 and M40 are
It is grounded via a constant current source 27 (current value: I ₀ ). The first 3MOS differential pair is driven by a constant current I ₀ which generates the constant current source 27. MOS transistor M
The drains of 39 and M40 are connected to power supply voltage lines via constant current sources 28 and 29 (both are current values: I ₀ ).

[0251] The ratio of the MOS transistors M39, M40 of the gate width (W) and gate length (L) (W / L) is a _1-fold that of K in any unit MOS transistor.

The second input voltage _Vy is applied between the gates of the MOS transistors M39 and M40.

P-channel MOS transistors M41, M
42 operates as loads on the MOS transistors M39 and M40, respectively. MOS transistors M41, M4
2 is connected to the drains of the MOS transistors M39 and M40, respectively. The gates of the MOS transistors M41 and M42 are connected to the drain of the MOS transistor M32 of the first differential pair, and the output voltage V _O2 of the first differential pair is commonly applied to the gate. M
The drains of the OS transistors M41 and M42 are connected to each other.

[0254] The ratio of the MOS transistors M41, M42 of the gate width (W) and gate length (L) (W / L) are all ₄ times that of K of unit MOS transistor.

Next, M of the fifth embodiment having the above configuration
The operation principle of the OS composite differential amplifier circuit will be described.

The first differential pair of MOS transistors M31,
If the drain currents of M32 are I ₁ and I ₂ respectively,
The currents flowing through the MOS transistors M34 and M33 are also I ₁ and I ₂ , respectively. Also, assuming that drain currents flowing through the MOS transistors M35 and M36 of the second differential pair are I ₃ and I ₄ , respectively, the MOS transistors M38 and M3
The current flowing through 7 also becomes I ₁ and I ₂ , respectively. Further, since the third differential pair has the same configuration as the second differential pair, the drain currents of the MOS transistors M39 and M40 of the third differential pair are also I ₃ and I ₄ , respectively, and the MOS transistor M4
2. The currents flowing through M41 are also I ₃ and I ₄ , respectively.

Then, since I ₁ + I ₂ = I ₀ and I ₃ + I ₄ = I ₀ hold, the output voltages V _O1 , V _O of the first MOS differential pair are satisfied.
_{For O2} , the following equations (47a) and (47b) are obtained.

[0258]

[Equation 47]

In equations (47a) and (47b), V
_THn, respectively beta _n, the threshold voltage of the n-channel MOS transistor, a transconductance parameter.

The following equations (48a) and (48b) are obtained for the output voltages V ₁ and V ₂ of the second MOS differential pair.

[0261]

[Equation 48]

In equations (48a) and (48b), V
_THp, respectively beta _p, the threshold voltage of the p-channel MOS transistor, a transconductance parameter.

The following equations (49a) and (49b) are obtained for the output voltages V ₃ and V ₄ of the third MOS differential pair.

[0264]

[Equation 49]

On the other hand, the following equations (50a) and (50b) hold as described in the first embodiment.

[0266]

[Equation 50]

Therefore, the following equations (51a) and (51a)
b), (51c) and (51d) are obtained.

[0268]

(Equation 51)

[0269] Thus, also in the composite differential amplifier circuit of the fifth embodiment, the linear variety of differential output voltage is obtained for at least one of the first input voltage V _x and the second input voltage V _y . The differential output voltage is set by appropriately setting the values of the constants K ₁ , K ₂ , and K ₄ , and the first to fourth output voltages V ₁ , V ₂ , V ₃ , and V ₄ are appropriately set. Can be easily changed and selected.
Therefore, the composite differential amplifier circuit can be suitably used as an input circuit of a multiplication circuit.

In addition, these linear differential output voltages are:
Obtained over the entire operating input voltage range. that is,
This is because the operating input voltage range of the first MOS differential pair matches the operating input voltage range of the second and third MOS differential pairs.

(Sixth Embodiment) FIG. 8 shows a bipolar composite differential amplifier circuit according to a sixth embodiment of the present invention.

This composite differential amplifier circuit is the same as that of the fifth
In the MOS composite differential amplifier circuit of the embodiment (see FIG. 7), first, second, and third bipolar voltage-currents (V-) that linearly operate the first, second, and third MOS differential pairs, respectively.
I) Instead of the conversion circuits 31, 32 and 33, load MOS transistors M33, M34, M37, M38,
M41 and M42 are respectively connected to bipolar transistors Q3
3, Q34, Q37, Q38, Q41 and Q42.

Since the rest of the configuration is the same as that of the MOS composite differential amplifier circuit of FIG. 7, in FIG. 8, the same or corresponding elements as those of the composite differential amplifier circuit of FIG. I do.

In the sixth embodiment, the M of the fifth embodiment
As in the case of the OS composite differential amplifier circuit, a pnp bipolar transistor and an npn bipolar transistor are connected in parallel so that the base-emitter voltages do not overlap in two stages. Therefore, there is an advantage that the power supply voltage can be reduced.

The first VI conversion circuit 31 includes the constant current source 21
(Current value: I ₀ ). The input terminal pair of the 1V-I conversion circuit 31 has a first input voltage V _x is applied. From the output terminal pair of the 1V-I conversion circuit 31, the differential output current I _x ⁺ proportional to the first input voltage V _x applied, I _x ^- is output. The currents flowing through the load bipolar transistors Q34 and Q33 are I _x ⁺ and I _x ⁺ , respectively.
_x ^- become.

Two npn-type bipolar transistors Q
33 and Q34 operate as loads of the first VI conversion circuit 31. The emitter of the bipolar transistor Q33, Q34 are respectively connected to the output terminal pair, collector connected in common to the power-supply voltage line power supply voltage V _CC is applied, it is commonly applied bias voltage V _B to the base .

The second VI conversion circuit 32 includes a constant current source 24
(Current value: I ₀ ). The second input voltage _Vy is applied to the input terminal pair of the second VI conversion circuit 32. From the output terminal pair of the 2V-I conversion circuit 32, the differential output current I _y ⁺ which is proportional to the second input voltage V _y applied, I _y ^- is output.

Two pnp type bipolar transistors Q
37 and Q38 operate as loads of the second VI conversion circuit 32. The emitters of bipolar transistors Q37 and Q38 are respectively connected to the output terminal pair, and the collector and base are connected to one output terminal (emitter side of transistor Q33) of first VI conversion circuit 31, and the collector and the base are connected to each other. The base has a first VI conversion circuit 31
_Are applied in common.

The third VI conversion circuit 33 includes a constant current source 27
(Current value: I ₀ ). The second input voltage _Vy is applied to the input terminal pair of the third VI conversion circuit 33. From the output terminal pair of the 3V-I conversion circuit 33, the differential output current I _y ⁺ which is proportional to the second input voltage V _y applied, I _y ^- is output.

Two pnp type bipolar transistors Q
41 and Q42 operate as loads of the third VI conversion circuit 33. The emitters of the bipolar transistors Q41 and Q42 are respectively connected to the output terminal pair, and the collector and the base are connected to the other output terminal (emitter side of the transistor Q34) of the first VI conversion circuit 31. The base has a first VI conversion circuit 31
_Are applied in common.

The first and second output voltages V ₁ and V ₂ of the composite differential amplifier circuit are taken out from the output terminal pair of the _second VI conversion circuit 32, respectively. The third and fourth output voltages V ₃ and V ₄ of the composite differential amplifier circuit are equal to the _third VI conversion circuit 3.
3 output terminal pairs.

As a VI conversion circuit that operates linearly,
Various types are known.
No. 032 is preferred. Since the VI conversion circuit disclosed in this publication uses a current mirror circuit as an output circuit, a plurality of identical output currents can be easily output by increasing the number of output terminals of the current mirror circuit. Therefore, the second and third V-
This is because the I-conversion circuits 32 and 33 can be replaced with one VI conversion circuit that outputs two sets of the same output current, and the circuit configuration can be simplified.

Next, the operation principle of the composite differential amplifier circuit according to the sixth embodiment having the above configuration will be described.

The differential output current I of the first VI conversion circuit 31
_x ^+, I _x ^- satisfies the following relationship.

[0285]

(Equation 52)

Similarly, the second and third VI conversion circuits 3
The differential output current of 2,33 I _y ^+, I _y ^- satisfies the following relationship.

[0287]

(Equation 53)

[0288] Thus, the bipolar transistor Q33 current I _x ^- is, current I _x ⁺ flows through the transistor Q34. Furthermore, both current I _y is the bipolar transistor Q37, Q41 ^- flows, the transistor Q38, Q42
, A current I _y ⁺ flows.

Here, the relationship between the collector current I _C of the bipolar transistor and the base-emitter voltage V _BE is I _S
Saturation current of the bipolar transistor, when the V _T is the thermal voltage, is generally expressed by the following equation (54).

[0290]

(Equation 54)

Therefore, for the output voltages V _O1 and V _O2 of the first VI conversion circuit 31, the following equations (55a) and (5a)
5b) holds.

[0292]

[Equation 55]

In equations (55a) and (55b), I
_Sn is the saturation current of the npn-type bipolar transistor.

Similarly, for the output voltages V ₁ and V ₂ of the _second V-1 conversion circuit 32, the following equations (56a) and (56
b) holds.

[0295]

[Equation 56]

In equations (56a) and (56b), I
_Sp is a saturation current of the pnp type bipolar transistor.

The output voltage V _{3 of the third} VI conversion circuit 33,
The following equations (57a) and (57b) hold for V ₄ .

[0298]

[Equation 57]

The equations (55a), (55b) and (56)
a), (56b), ( 57a), the use of (57 b), the following equation for the first to fourth output voltage _{V 1, V 2, V 3} , V 4 (58a), (58b), ( 58c) are obtained.

[0300]

[Equation 58]

As described above, also in the bipolar composite differential amplifier circuit of the sixth embodiment, two sets of differential output currents I _x ⁺ and I _x proportional to the first input voltage V _x and the second input voltage V _y , respectively. Various differential output voltages that are linear with respect to at least one of _x ⁻ , I _y ⁺ and I _y ⁻ are obtained. Then, the differential output voltage, by combining the first to fourth output voltage _{V 1, V 2, V 3} , V 4 appropriately, easily changed, it is possible to select. Therefore, the composite differential amplifier circuit can be suitably used as an input circuit of a multiplication circuit.

Further, these linear differential output voltages are:
Obtained over the entire operating input voltage range. that is,
This is because the operation input voltage range of the first (VI) conversion circuit 31 and the operation input voltage ranges of the second and third (VI) conversion circuits 32 and 33 match each other.

(Seventh Embodiment) FIG. 9 shows a bipolar composite differential amplifier circuit according to a seventh embodiment of the present invention. This composite differential amplifier circuit is different from the MOS composite differential amplifier circuit of the third embodiment described above (see FIG. 5) in that the first to third MOs are used.
The S differential pair is replaced with first to third voltage-current (VI) conversion circuits, and the load MOS transistor is replaced with a bipolar transistor.

The first VI conversion circuit 41 includes the constant current source 11
(Current value: I ₀ ). The input terminal pair of the 1V-I conversion circuit 41 has a first input voltage V _x is applied. From the output terminal pair of the 1V-I conversion circuit 41, the differential output current I _x ⁺ proportional to the first input voltage V _x applied, I _x ^- is output.

Two npn-type bipolar transistors Q
13 and Q14 operate as a load of the first VI conversion circuit 41. The emitter of the bipolar transistor Q13, Q14 are respectively connected to the output terminal pair, collector connected in common to the power-supply voltage line power supply voltage V _CC is applied, it is commonly applied bias voltage V _B to the base .

The second VI conversion circuit 42 includes the constant current source 12
(Current value: I ₀ ). The second input voltage _Vy is applied to the input terminal pair of the second VI conversion circuit 42. From the output terminal pair of the 2V-I conversion circuit 42, the differential output current I _y ⁺ which is proportional to the second input voltage V _y applied, I _y ^- is output.

Two npn-type bipolar transistors Q
17, 18 operate as a load of the second VI conversion circuit 42. The emitters of bipolar transistors Q17 and Q18 are respectively connected to the output terminal pair, the collectors are commonly connected to a power supply voltage line, and the base is the first VI-I.
It is connected to one output terminal of the conversion circuit 41 (the emitter side of the transistor Q13), and its base is connected to the first terminal.
The output voltage V _O1 of the VI conversion circuit 41 is commonly applied.

The third VI conversion circuit 43 includes the constant current source 13
(Current value: I ₀ ). The second input voltage _Vy is applied to the input terminal pair of the third VI conversion circuit 43. From the output terminal pair of the 3V-I conversion circuit 42, the differential output current I _y ⁺ which is proportional to the second input voltage V _y applied, I _y ^- is output.

Two npn-type bipolar transistors Q
21 and Q22 operate as loads of the third VI conversion circuit 43. The emitters of bipolar transistors Q22 and Q23 are respectively connected to the output terminal pair, the collectors are commonly connected to a power supply voltage line, and the base is the first VI-VI.
It is connected to the other output terminal of the conversion circuit 41 (the emitter side of the transistor Q14), and its base is connected to the first terminal.
The output voltage V _O2 of the VI conversion circuit 41 is commonly applied.

The first and second output voltages V ₁ and V ₂ of the composite differential amplifier circuit are taken out from the output terminal pair of the _second VI conversion circuit 42, respectively. The third and fourth output voltages V ₃ and V ₄ of the composite differential amplifier circuit are the third VI conversion circuit 4
3 output terminal pairs.

The operating principle of the composite differential amplifier circuit of the seventh embodiment having the above configuration is substantially the same as that of the composite differential amplifier circuit of the sixth embodiment (see FIG. 8). Omitted.

(Eighth Embodiment) FIG. 10 shows an eighth embodiment of the present invention.
1 shows a bipolar composite differential amplifier circuit according to an embodiment. This composite differential amplifier circuit is different from the MOS composite differential amplifier circuit of the fourth embodiment described above (see FIG. 6) in that first to third M
The OS differential pair is replaced with first to third voltage-current (VI) conversion circuits, and the load MOS transistor is replaced with a bipolar transistor.

The circuit configuration and operation principle of this composite differential amplifier circuit are the same as those of the bipolar composite differential amplifier circuit of the seventh embodiment (see FIG. 9), and will not be described.

(Ninth Embodiment) FIG. 11 shows a ninth embodiment of the present invention.
1 shows a MOS multiplication circuit according to an embodiment.

This multiplication circuit is a quarter-square type obtained by combining two MOS squaring circuits of the first embodiment (see FIG. 1). Also, the first to be multiplied,
From the second input voltage V _x, V _y, as an input circuit for generating the four voltages to be applied to the input terminal thereof squaring circuit, simple resistor summing circuit of the circuit configuration is used.

Since the first squaring circuit arranged on the left side in FIG. 11 has exactly the same configuration as the squaring circuit in FIG. 1, the same reference numerals as those in FIG. 1 denote the same circuits in FIG. 11, and a description thereof will be omitted. I do.

[0317] In the second squaring circuits disposed on the right side in FIG. 11, the first two MOS transistors M10A for bias voltage V _B generated squaring circuit, for utilizing M10B, the MOS transistors M10A, M10B
The configuration is exactly the same as that of the squaring circuit in FIG. 1 except that is omitted. Therefore, the same reference numerals as those in the squaring circuit shown in FIG.

MOS transistor M of first squaring circuit
5, the drain of M6 is connected to the drain of the MOS transistor M7 of the second squaring circuit,
An output terminal is formed. An output current I ⁺ is obtained from the first output terminal. A load resistor (resistance value: R _L ) is connected between the first output terminal and the power supply voltage line.

MOS transistor M of second square circuit
5, the drain of M6 is connected to the drain of the MOS transistor M7 of the first squaring circuit,
An output terminal is formed. This is from the second output terminal an output current I ^- is taken out. A load resistor (resistance value: R _L ) is also connected between the second output terminal and the power supply voltage line.

The first and second input voltages V _x and V _y are applied to the input terminal pair of the multiplier circuit.

The resistance addition circuit operating as an input circuit
It is formed from six resistors having the same resistance value R.
Of the six resistors, two connected in series are connected between the input terminal pair of the multiplier circuit, and the middle point is connected to the gate of the MOS transistor M1. Similarly, the other two resistors connected in series have their midpoints connected to the gate of the MOS transistor M1 ′,
The other two resistors connected in series have the middle point at MO
It is connected to the gate of the S transistor M2 '.

[0322] Thus, MOS transistors M1, M2 differential input voltage between the gate of the _{(1/2) (V x -V y} ) is applied, MOS transistors M1 ', M2' between the gate of the differential input voltage _{(1/2) (V x + V} y) is applied.

[0323] connected to the constant voltage source between the gate and ground of the MOS transistor M2 generates a reference direct voltage V _G.

In the quarter square multiplication circuit of the ninth embodiment having the above configuration, two output currents I ⁺ and I ^+
- the following formula (59a), respectively represented by (59b).

[0325]

[Equation 59]

Therefore, the differential output current ΔI (= I ⁺ −
I ^-) is represented by ,, following formula (60).

[0327]

[Equation 60]

From equation (60), the differential output current ΔI is the product of the first and second input signal voltages V _x and V _y (V _x · V _y )
It turns out that it is proportional to. This means that the MOS multiplication circuit of the ninth embodiment has ideal multiplication characteristics over the entire operation input voltage range.

In this embodiment, the output current = I by two load resistors connected to the first and second output terminals.
⁺ And I ^- is the output voltage V ⁺ and V ^- are converted, respectively. From equation (60), the differential output voltage ΔV (= V ⁺ −V ⁻ ) is also the first
And it is proportional to the second input signal the product of the voltage V _x and _{V y (V x · V y} ), the voltage output having an ideal multiplication characteristic is obtained.

Further, since the circuit is constituted only by n-channel MOS transistors, there is an advantage that excellent frequency characteristics can be realized.

(Tenth Embodiment) FIG. 12 shows a MOS multiplication circuit according to a tenth embodiment of the present invention.

This multiplication circuit is a quarter-square type in which two MOS squaring circuits (see FIG. 2) according to the second embodiment are combined. In other words, in the multiplication circuit of the ninth embodiment in FIG. 11, the MOS triple tail cells of each squaring circuit are replaced with MOS quadritail cells.

The circuit configuration and operation principle of this multiplication circuit are the same as those of the multiplication circuit of the ninth embodiment.

This multiplying circuit has the same effect as the ninth embodiment.

(Eleventh Embodiment) FIG. 13 shows a MOS multiplication circuit according to an eleventh embodiment of the present invention. This multiplying circuit is of the same quarter-sharing type as the ninth and tenth embodiments described above, but uses the MOS composite differential amplifier circuit of the third embodiment shown in FIG. 5 instead of the resistance adding circuit. This is different from the first embodiment in that two MOS quadratic cells are used as the first and second squaring circuits.

The input circuit arranged on the left side in FIG. 13 has exactly the same configuration as the MOS composite differential amplifier circuit of the third embodiment (see FIG. 5). The same reference numerals are assigned to the circuits and the description is omitted.

Source-coupled four n-channel MOS
The transistors M61, M62, M63, M64 and the constant current source 51 (current value: I ₀₀ ) form a first MOS quadritail cell. MOS transistors M61, M6
2. The sources of M63 and M64 are grounded via a constant current source 51. The gate of the MOS transistor M61 includes a fourth output voltage V ₄ of the composite differential amplifier circuit is applied. The gate of the MOS transistor M62 has a first output voltage V ₁ of the composite differential amplifier circuit is applied. A control voltage V _C is commonly applied to the gates of the MOS transistors M63 and M64.

Source-coupled four n-channel MOS
The transistors M65, M66, M67, M68 and the constant current source 52 (current value: I ₀₀ ) form a second MOS quadritail cell. MOS transistors M65, M6
6, the sources of M67 and M68 are grounded via the constant current source 52. The gate of the MOS transistor M65, the third output voltage V ₃ of the composite differential amplifier circuit is applied. The gate of the MOS transistor M66, the second output voltage V ₂ of the composite differential amplifier circuit is applied. A control voltage V _C is commonly applied to the gates of the MOS transistors M67 and M68.

The MOS transistors M61, M62, M6
7, the drains of M68 are connected to each other to form a first output terminal of the multiplication circuit. The drains of the MOS transistors M63, M64, M65, M66 are connected to each other to form a second output terminal of the multiplier.

Four n-channel MOS transistors M5
1, M52, M53, M54 and constant current source 50 (current value:
I ₀ ) generates a control voltage V _C that feeds the first and second quadretail cells.

In the MOS multiplying circuit according to the eleventh embodiment, the two differential circuits represented by the above-mentioned equations (36c) and (36d) in the MOS composite differential amplifying circuit according to the third embodiment (see FIG. 5) are used. Voltages (V ₄ -V ₁ ) and (V ₃ -V ₂ ) are applied to the first and second quadretail cells, respectively. Therefore, the two differential output currents I ⁺ and I ⁻ extracted from the first and second output terminals of the multiplication circuit are:
These are represented by the following equations (61a) and (61b).

[0342]

[Equation 61]

Therefore, the differential output current △ I (= I ⁺ −
I ^-) is given by the following equation (62).

[0344]

(Equation 62)

As is clear from equation (62), the product (V _x · V _y ) of the first and second input signal voltages V _x and V _y is obtained for the differential output current ΔI. Like the multiplier circuits of the ninth and tenth embodiments, the MOS multiplier circuit of the eleventh embodiment also has ideal multiplication characteristics.

Further, since the circuit is constituted only by n-channel MOS transistors, excellent frequency characteristics can be realized.

(Twelfth Embodiment) FIG. 14 shows a MOS multiplication circuit according to a twelfth embodiment of the present invention. This multiplying circuit is of the same quarter-sharing type as that of the ninth to eleventh embodiments described above, and the MOS circuit of the fourth embodiment shown in FIG.
The point of using the composite differential amplifier circuit is the MO of the eleventh embodiment.
It is different only from the S multiplication circuit.

Therefore, in FIG. 14, the input circuits are denoted by the same reference numerals as those of the MOS composite differential amplifier circuit of FIG. 6, and the first and second squaring circuits of the eleventh embodiment of FIG. The same reference numerals as those of the MOS multiplication circuit are used, and the description thereof is omitted.

In the multiplying circuit according to the twelfth embodiment, the differential output current ΔI (= I ⁺
−I ⁻ ) is obtained, and thus has ideal multiplication characteristics. Further, since the circuit is constituted only by the n-channel MOS transistors, excellent frequency characteristics can be realized.

(Thirteenth Embodiment) In the circuit configuration of FIG. 13 or FIG. 14, a composite of the fifth to ninth embodiments shown in FIG. 7 to FIG. It is also possible to use any of the differential amplifier circuits.

FIG. 15 is a block diagram of the fifth embodiment shown in FIG.
FIG. 39 shows a MOS quadrature type multiplier circuit of a thirteenth embodiment of the present invention using an OS composite differential amplifier circuit. In FIG. 15, V _B ′ indicates a bias voltage applied to the gates of the MOS transistors M53 and M54.

In this multiplication circuit, the first and second output currents I ⁺ and I ⁻ are calculated by the following equations (63a) and (63), respectively.
b).

[0353]

[Equation 63]

Therefore, the differential output current ΔI is expressed by the following equation (64).

[0355]

[Equation 64]

From the equation (64), the product (V _x · V _y ) of the two input signal voltages V _x and V _y is obtained for the differential output current ΔI, so that the MOS quadrature type of the thirteenth embodiment is used. It can be seen that the multiplication circuit is also an ideal multiplication circuit.

The transconductance parameter β _p of the p-channel MOS transistor is erased and does not appear in the differential output current ΔI.

(Fourteenth Embodiment) FIG. 16 shows a MOS multiplication circuit according to a fourteenth embodiment of the present invention. This multiplying circuit differs from the quarter-sharing type multiplying circuits of the ninth to thirteenth embodiments in that it comprises an input circuit and a multiplier core circuit.

In the multiplication circuit according to the fourteenth embodiment, a MOS quadrature cell is used as a multiplier core circuit.
The MOS composite differential amplifier circuit shown in FIG. 5 is used for an input circuit.

The condition of the input voltage required for the MOS quadrature cell to operate as a multiplier core circuit is disclosed in
-83314. According to this,
A multiplying circuit can be realized by using any of the complex differential amplifier circuits of the third to eighth embodiments shown in FIGS.

The first to fourth output voltages V ₁ , V ₂ , and V in any of the composite differential amplifier circuits of the third to eighth embodiments.
V ₃ and V ₄ are replaced by MOS transistors M71, M72, M of a MOS quadri-tail cell constituting a multiplier core circuit.
When input to the gates of 73 and M74, respectively, an ideal multiplication circuit is realized as shown below.

In FIG. 16, the same reference numerals as those of the MOS composite differential amplifier circuit of FIG. 5 denote the input circuits, and a description thereof will be omitted.

[0364] The MOS quadri-tail cell of FIG.
It is formed by four source-coupled n-channel MOS transistors M71, M72, M73 and M74. MOS transistors M71, M72, M73, M7
The source 4 is grounded via a constant current source 71 (current value: I ₀₀ ). The drains of the MOS transistors M71 and M74 are connected to each other to form a first output terminal of the multiplier. MOS transistors M72, M7
3 are connected to each other to form the second
An output terminal is formed.

The first to fourth output voltages V ₁ , V ₂ , V ₃ and V ₄ of the composite differential amplifier circuit shown in FIG. 5 are connected to the gates of the quadrature cell MOS transistors M71, M72, M73 and M74. Each is entered.

The two output currents I ⁺ and I ⁻ taken from the first and second output terminals of the multiplication circuit are calculated by the following equation (6).
5a) and (65b).

[0366]

[Equation 65]

Therefore, the differential output current ΔI is expressed by the following equation (66).

[0368]

[Equation 66]

From equation (66), the MO of the fourteenth embodiment can be obtained.
It can be seen that the S multiplication circuit is also an ideal multiplication circuit.

In the case where the composite differential amplifier circuit of the fourth embodiment shown in FIG.
a), (65b) and (66) are obtained.

(Fifteenth Embodiment) FIG. 17 shows a multiplier core type MOS multiplier circuit according to a fifteenth embodiment of the present invention.

In the multiplying circuit according to the fifteenth embodiment, a MOS core cell is used as a multiplier core circuit.
The MOS composite differential amplifier circuit shown in FIG. 7 is used for an input circuit.

In this multiplier core type multiplication circuit, the first and second output currents I ⁺ and I ⁻ are calculated by the following equations (67a) and (6a).
7b).

[0374]

[Equation 67]

Therefore, the differential output current ΔI is expressed by the following equation (68).

[0376]

[Equation 68]

From the equation (68), the MO of the fifteenth embodiment is obtained.
It can be seen that the S multiplier core type multiplier is also an ideal multiplier.

(Sixteenth Embodiment) FIG. 18 shows a bipolar multiplier core type multiplication circuit according to a sixteenth embodiment. This multiplication circuit uses the composite differential amplification circuit shown in FIG. 8 and a bipolar quadrature cell.

Referring to FIG. 18, the bipolar quadrature cell includes four npn-type bipolar transistors Q21, Q22, Q23, and Q2 which are emitter-coupled.
4. Bipolar transistor Q2
1, the emitters of Q22, Q23 and Q24 are constant current sources 8
1 (current value: I ₀₀ ). The collectors of the bipolar transistors Q21 and Q24 are connected to each other to form a first output terminal of the multiplier.
The collectors of the bipolar transistors Q22 and Q23 are connected to each other to form a second output terminal of the multiplier.

Bipolar multiplication circuit using a bipolar composite differential amplifier circuit using a VI conversion circuit as shown in FIGS. 8 to 10 as an input circuit, and using a bipolar quadrature cell as a multiplier core circuit Is disclosed in JP-A-9-298423 by the same inventor.
The multiplier core type bipolar multiplying circuit of the sixteenth embodiment is an improvement of the bipolar multiplying circuit disclosed in Japanese Patent Application Laid-Open No. 9-298423.
It is possible to operate at a lower voltage than the bipolar multiplying circuit disclosed in Japanese Patent Application Laid-Open No. H10-209,878.

The condition of the input voltage for the bipolar quadruple cell to operate as a multiplier core circuit is disclosed in Japanese Patent Application Laid-Open No. 8-83314 by the same inventor. According to this, as shown in FIG. 18, the first to fourth output voltages V ₁ , V ₂ , V ₃ and V ₄ of the bipolar composite differential amplifier circuit shown in FIG.
Quadrature cell bipolar transistor Q2
When applied to the bases of 1, Q22, Q23, and Q24, respectively, a multiplication circuit is realized.

That is, the equation (58) obtained in the bipolar composite differential amplifier circuit of the sixth embodiment shown in FIG.
a), (58b) and (58c) are disclosed in JP-A-8-83314.
When the conditions disclosed in the above publication are applied, the output currents I ⁺ and I ⁻ are expressed by the following equations (69a) and (69b), respectively.

[0383]

[Equation 69]

[0384] However, Equation (69a), in (69b), I _x ^- a _{= I 0 -G x V x,} I x + = I 0 + G x V x.

Therefore, the differential output current ΔI is expressed by the following equation (70).

[0386]

[Equation 70]

From equation (70), it can be seen that the bipolar multiplier core type multiplier of the sixteenth embodiment is also an ideal multiplier.

In this embodiment, the bipolar composite differential amplifier circuit shown in FIG. 8 is used as the input circuit. Alternatively, the bipolar composite differential amplifier circuit shown in FIG. 9 or 10 may be used. It goes without saying that it is good.

[0389]

As described above, the first and second squaring circuits of the present invention have a square characteristic over the entire operating input voltage range.

In the first to fourth composite differential amplifier circuits of the present invention, a differential output voltage linear with respect to two input voltages can be obtained over the entire operation input voltage range. Further, it can be suitably used as an input circuit of a multiplication circuit.

The first to third multiplication circuits of the present invention have good linearity over the entire operating input voltage range. Also, the transconductance has good linearity with respect to two input voltages.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a MOS squaring circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a MOS squaring circuit according to a second embodiment of the present invention.

FIG. 3 shows a MOS using a MOS transistor as a load.
FIG. 4 is a diagram illustrating output voltage characteristics of a differential pair.

FIG. 4 is a diagram showing each output current characteristic of a MOS quadruple cell.

FIG. 5 is a circuit diagram showing a MOS composite differential amplifier circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a MOS composite differential amplifier circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a MOS composite differential amplifier circuit according to a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a bipolar composite differential amplifier circuit according to a sixth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a bipolar composite differential amplifier circuit according to a seventh embodiment of the present invention.

FIG. 10 is a circuit diagram showing a bipolar composite differential amplifier circuit according to an eighth embodiment of the present invention.

FIG. 11 is a circuit diagram of a MOS quarter-task type multiplication circuit according to a ninth embodiment of the present invention.

FIG. 12 is a circuit diagram of a MOS quadrature-type multiplication circuit according to a tenth embodiment of the present invention.

FIG. 13 is a circuit diagram of a MOS quadrature-type multiplication circuit according to an eleventh embodiment of the present invention.

FIG. 14 is a circuit diagram of a MOS quadrature-type multiplication circuit according to a twelfth embodiment of the present invention.

FIG. 15 is a circuit diagram of a MOS quadrature-type multiplication circuit according to a thirteenth embodiment of the present invention.

FIG. 16 is a circuit diagram of a MOS multiplier core type multiplication circuit according to a fourteenth embodiment of the present invention.

FIG. 17 is a circuit diagram of a MOS multiplier core type multiplication circuit according to a fifteenth embodiment of the present invention.

FIG. 18 is a circuit diagram of a bipolar multiplier core type multiplication circuit according to a sixteenth embodiment of the present invention.

FIG. 19 shows a conventional MOS using a quadritail cell.
FIG. 3 is a circuit diagram illustrating a squaring circuit.

[Explanation of symbols]

M1, M2, M3, M4, M5, M6, M7 MOS transistors M7A, M7B, M8, M10A, M10B MOS transistors M11, M12, M13, M14, M15, M16 M
OS transistor M17, M18, M19, M20, M27, M22 M
OS transistor M31, M32, M33, M34, M35, M36 M
OS transistor M37, M38, M39, M40, M41, M42 M
OS transistor M51, M52, M53, M54 MOS transistor M61, M62, M63, M64, M65, M66 M
OS transistor M67, M68 MOS transistor M71, M72, M73, M74 MOS transistor M1 ', M2', M3 ', M4', M5 ', M6' M
OS transistor M7 ', M7A', M7B 'MOS transistor Q1, Q2, Q3 bipolar transistor Q6, Q7, Q8 bipolar transistor Q13, Q14, Q17, Q18, Q21, Q22 bipolar transistor Q21, Q22, Q23, Q24 bipolar transistor Q33, Q34, Q37, Q38, Q41, Q42 Bipolar transistors 1, 2, 3, 4, 5, 6 Constant current sources 1 ', 2', 3 'Constant current sources 11, 12, 13 Constant current sources 21, 22, 23, 24, 25, 26, 27, 28, 2
9 Constant current sources 31, 32, 33 Voltage-current (VI) conversion circuits 41, 42, 43 Voltage-current (VI) conversion circuits 50, 51, 52 Constant current sources 71, 81 Constant current sources

Claims (15)

[Claims] (A) formed by source-coupled first and second MOSFETs;
A MOS differential pair to which an input voltage is applied between the gates of the first and second MOSFETs, and (b) the first MOSFET
A third MOSFET connected to the drain of the third MOSFET and operating as a load of the first MOSFET; and (c) the second MOSFET.
The second MOS connected to the drain of the MOSFET
A fourth MOSFET that operates as a load of the FET;
(D) Source coupled fifth, sixth and seventh MOs
A third tail cell formed by an SFET, wherein the fifth, sixth and seventh MOSFETs are driven by a single tail current;
A constant voltage is applied to the gate of the OSFET, and (f) the first MOSFET is connected to the gate of the fifth MOSFET.
The first output voltage of the MOS differential pair generated at the drain of T is applied to the gate of the sixth MOSFET, and the second output voltage of the MOS differential pair generated at the drain of the second MOSFET is applied to the gate of the sixth MOSFET. (G) the drain of the fifth MOSFET and the drain of the sixth MOSFET are connected together to form a first output terminal, while the drain of the seventh MOSFET forms a second output terminal; An output of the squaring circuit is obtained from one of the first and second output terminals. 2. (a) formed by source-coupled first and second MOSFETs, and
A MOS differential pair to which an input voltage is applied between the gates of the first and second MOSFETs, and (b) the first MOSFET
A third MOSFET connected to the drain of the third MOSFET and operating as a load of the first MOSFET; and (c) the second MOSFET.
The second MOS connected to the drain of the MOSFET
A fourth MOSFET that operates as a load of the FET;
(D) source coupled fifth, sixth, seventh and eighth
And their fifth,
(E) comprising a quadrature cell in which the sixth, seventh and eighth MOSFETs are driven by a single tail current;
A constant voltage is commonly applied to the gates of the seventh and eighth MOSFETs, and (f) a first output voltage of the MOS differential pair generated at the drain of the first MOSFET is applied to the gate of the fifth MOSFET. Is applied, and the gate of the sixth MOSFET is connected to the second MOSF.
A second output voltage of the MOS differential pair generated is applied to a drain of the ET, and (g) a drain of the fifth MOSFET and a drain of the sixth MOSFET are connected to each other to form a first output terminal, 7th MOSF
(H) the drain of the ET and the drain of the eighth MOSFET are connected to each other to form a second output terminal;
An output of the squaring circuit is obtained from one of the first and second output terminals. (A) formed by source-coupled first and second MOSFETs, and
A first MOS differential pair to which a first input voltage is applied between the gates of the first and second MOSFETs;
The first MOSFET connected to the drain of the SFET
A third MOSFET which operates as a load of T; (c)
A fourth MOSFET connected to the drain of the second MOSFET and operating as a load of the second MOSFET
And (d) fifth and sixth source-coupled MOSs
FETs and their fifth and sixth
A second MOS differential pair to which a second input voltage is applied between the gates of the MOSFETs, (e) a seventh MOSFET connected to the drain of the fifth MOSFET and operating as a load of the fifth MOSFET, and (f) 6th M
The sixth MOSF connected to the drain of the OSFET
An eighth MOSFET acting as a load on the ET, and (g)
The ninth and tenth MOSFETs are formed by source-coupled ninth and tenth MOSFETs.
A third MOS differential pair to which the second input voltage is applied between the gates of the SFET, (h) an eleventh MOSFET connected to a drain of the ninth MOSFET and operating as a load of the ninth MOSFET, and (i) Tenth
The 10th MO connected to the drain of the MOSFET
A twelfth MOSFET that operates as a load of an SFET; and (j) a gate of the seventh and eighth MOSFETs has a common first output voltage of the first MOS differential pair generated at the drain of the first MOSFET. And the second output voltage of the first MOS differential pair generated at the drain of the second MOSFET is commonly applied to the gates of the eleventh and twelfth MOSFETs, and (k) Fifth, sixth, ninth and tenth M
A composite differential amplifier circuit, wherein first, second, third, and fourth output voltages of the composite differential amplifier circuit are respectively taken out from a drain of the OSFET. And (a) formed by source-coupled first and second MOSFETs, and
A first MOS differential pair to which a first input voltage is applied between the gates of the first and second MOSFETs;
The first MOSFET connected to the drain of the SFET
A third MOSFET which operates as a load of T; (c)
A fourth MOSFET connected to the drain of the second MOSFET and operating as a load of the second MOSFET
And (d) fifth and sixth source-coupled MOSs
FETs and their fifth and sixth
A second MOS differential pair to which a second input voltage is applied between the gates of the MOSFETs, (e) a seventh MOSFET connected to the drain of the fifth MOSFET and operating as a load of the fifth MOSFET, and (f) 6th M
The sixth MOSF connected to the drain of the OSFET
An eighth MOSFET acting as a load on the ET, and (g)
The ninth and tenth MOSFETs are formed by source-coupled ninth and tenth MOSFETs.
A third MOS differential pair to which the second input voltage is applied between the gates of the SFET, (h) an eleventh MOSFET connected to a drain of the ninth MOSFET and operating as a load of the ninth MOSFET, and (i) Tenth
The 10th MO connected to the drain of the MOSFET
A twelfth MOSFET which operates as a load of an SFET; and (j) a gate of the seventh and twelfth MOSFETs has a common first output voltage of the first MOS differential pair generated at a drain of the first MOSFET. And the second output voltage of the first MOS differential pair generated at the drain of the second MOSFET is commonly applied to the gates of the eighth and eleventh MOSFETs, and (k) 5, tenth, sixth and ninth M
A composite differential amplifier circuit, wherein first, second, third, and fourth output voltages of the composite differential amplifier circuit are respectively taken out from a drain of the OSFET. 5. The first and second MOSFETs forming the first MOS differential pair form the third and third MOS differential pairs with the fifth and sixth MOSFETs forming the second MOS differential pair. The ninth and tenth MOs
5. The composite differential amplifier circuit according to claim 3, which has the same polarity as the SFET. 6. The first and second MOSFETs forming the first MOS differential pair form the third and fifth MOSFETs with the fifth and sixth MOSFETs forming the second MOS differential pair. The ninth and tenth MOs
5. The composite differential amplifier circuit according to claim 3, which has a polarity opposite to that of the SFET. 7. The first and second MOSFETs forming the first MOS differential pair include a first and a second MOSFET.
The fifth and sixth MOSFETs, which have the same polarity as the third and fourth MOSFETs operating as the loads of the MOSFETs and form the second MOS differential pair, are the fifth and sixth MOSFETs.
The seventh and eighth MOSFEs operating as loads
The ninth and tenth elements having the same polarity as T and forming the third MOS differential pair
Of the ninth and tenth MOSFETs
The eleventh and twelfth Ms acting as ET loads
5. The composite differential amplifier circuit according to claim 3, which has the same polarity as the OSFET. 8. The first and second MOSFETs forming the first MOS differential pair include the first and second MOSFETs.
The fifth and sixth MOSFETs, which have opposite polarities to the third and fourth MOSFETs operating as loads of the MOSFETs, form the second MOS differential pair. MOSFET
The seventh and eighth MOSFEs operating as loads
The ninth and tenth elements having a polarity opposite to T and forming the third MOS differential pair
Of the ninth and tenth MOSFETs
The eleventh and twelfth Ms acting as ET loads
5. The composite differential amplifier circuit according to claim 3, which has a polarity opposite to that of the OSFET. 9. A first voltage for converting a first input voltage applied to an input terminal pair and outputting a first pair of differential output currents proportional to the first input voltage to an output terminal pair. (B) first and second bipolar transistors respectively connected to an output terminal pair of the first voltage-current conversion circuit and operating as loads of the first voltage-current conversion circuit; c) The second applied to the input terminal pair
A second voltage-current conversion circuit for converting an input voltage and outputting a second pair of differential output currents proportional to the second input voltage to an output terminal pair; and (d) a second voltage-current conversion circuit. Third and fourth bipolar transistors respectively connected to the output terminal pair and operating as loads of the second voltage-current conversion circuit, and (e) converting the second input voltage applied to the input terminal pair. A third voltage-current conversion circuit that outputs a third pair of differential output currents proportional to the second input voltage to the output terminal pair, and (f) an output terminal pair of the third voltage-current conversion circuit. Connected to its third voltage-
Fifth and sixth bipolar transistors operating as a load of the current conversion circuit; and (g) a base of the third and fourth bipolar transistors is provided with a first pair of the first voltage-current conversion circuit. The first output voltage of the first voltage-current conversion circuit generated by one of the differential output currents is commonly applied, and the first voltage-current conversion circuit is connected to the base of the fifth and sixth bipolar transistors.
A second output voltage of the first voltage-current conversion circuit generated by the other of the first pair of differential output currents of the current conversion circuit is commonly applied; and (h) an output of the second voltage-current conversion circuit. From the terminal pair, the first and second
Of the composite differential amplifier circuit from the output terminal pair of the third voltage-current conversion circuit.
And a fourth output voltage respectively taken out. 10. A first signal applied to an input terminal pair.
A first voltage-current conversion circuit for converting an input voltage and outputting a first pair of differential output currents proportional to the first input voltage to an output terminal pair; and (b) a first voltage-current conversion circuit. First and second bipolar transistors respectively connected to the output terminal pair and operating as loads of the first voltage-current conversion circuit; and (c) converting the second input voltage applied to the input terminal pair. A second proportional to the second input voltage
A second voltage-current conversion circuit for outputting a differential output current of the pair to an output terminal pair, and (d) a second voltage-current conversion circuit connected to the output terminal pair of the second voltage-current conversion circuit, respectively. Third and fourth bipolar transistors operating as a load of a circuit, and (e) a third pair of differential outputs proportional to the second input voltage by converting the second input voltage applied to the input terminal pair A third voltage-current conversion circuit for outputting a current to an output terminal pair, and (f) operating as a load of the third voltage-current conversion circuit connected to the output terminal pair of the third voltage-current conversion circuit, respectively. And (g) a base of each of the third and sixth bipolar transistors is provided with one of a first pair of differential output currents of the first voltage-current conversion circuit. That number generated The first output voltage of the first voltage-current conversion circuit is applied in common, and the fourth and fifth
A second output voltage of the first voltage-current conversion circuit generated by the other of the first pair of differential output currents of the first voltage-current conversion circuit is commonly applied to a base of the bipolar transistor; (H) first and third output voltages of the composite differential amplifier circuit are respectively taken out from an output terminal pair of the second voltage-current conversion circuit, and the first and third output voltages are extracted from the output terminal pair of the third voltage-current conversion circuit; A composite differential amplifier circuit, wherein second and fourth output voltages of the composite differential amplifier circuit are respectively taken out. 11. A first voltage for converting a first input voltage applied to an input terminal pair and outputting a first pair of differential output currents proportional to the first input voltage to an output terminal pair. (B) first and second bipolar transistors respectively connected to an output terminal pair of the first voltage-current conversion circuit and operating as loads of the first voltage-current conversion circuit; c) The second applied to the input terminal pair
A second voltage-current conversion circuit for converting an input voltage and outputting a second pair of differential output currents proportional to the second input voltage to an output terminal pair; and (d) a second voltage-current conversion circuit. Third and fourth bipolar transistors respectively connected to the output terminal pair and operating as loads of the second voltage-current conversion circuit, and (e) converting the second input voltage applied to the input terminal pair. A third voltage-current conversion circuit that outputs a third pair of differential output currents proportional to the second input voltage to the output terminal pair, and (f) an output terminal pair of the third voltage-current conversion circuit. Connected to its third voltage-
Fifth and sixth bipolar transistors operating as a load of the current conversion circuit; and (g) a base of the third and fourth bipolar transistors is provided with a first pair of the first voltage-current conversion circuit. The first output voltage of the first voltage-current conversion circuit generated by one of the differential output currents is commonly applied, and the first voltage-current conversion circuit is connected to the base of the fifth and sixth bipolar transistors.
A second output voltage of the first voltage-current conversion circuit generated by the other of the first pair of differential output currents of the current conversion circuit is commonly applied; and (h) an output of the second voltage-current conversion circuit. From the terminal pair, the first and second
Of the composite differential amplifier circuit from the output terminal pair of the third voltage-current conversion circuit.
And a fourth output voltage respectively taken out. 12. An input circuit for outputting first, second, third and fourth output voltages corresponding to the input first and second input voltages, and A first squaring circuit in which two of the output first, second, third and fourth output voltages are respectively input to an input terminal pair; and (c) output from the input circuit. The other two voltages of the first, second, third and fourth output voltages are respectively input to the input terminal pair.
(D) an output terminal pair of the first square circuit and an output terminal pair of the second square circuit are connected to each other to form a differential output terminal pair; 2. A quarter-square type multiplication circuit from which a differential output including a multiplication result of the first and second input voltages is taken out from a dynamic output terminal pair, wherein (e) each of the first and second squaring circuits is provided. Or a quarter-square type multiplication circuit comprising the squaring circuit according to 2. 13. The quarter-square type multiplication circuit according to claim 12, wherein said input circuit comprises a resistance adder. 14. An input circuit for outputting first, second, third and fourth output voltages corresponding to the input first and second input voltages, and A first squaring circuit in which two of the output first, second, third and fourth output voltages are respectively input to an input terminal pair; and (c) output from the input circuit. The other two voltages of the first, second, third and fourth output voltages are respectively input to the input terminal pair.
(D) an output terminal pair of the first square circuit and an output terminal pair of the second square circuit are connected to each other to form a differential output terminal pair; 3. A quarter-square type multiplying circuit from which a differential output including a result of multiplication of the first and second input voltages is taken out from a dynamic output terminal pair.
A quarter-square type multiplication circuit comprising the composite differential amplification circuit according to any one of the first to third aspects. 15. A multiplication circuit comprising: (a) an input circuit; and a multiplier core circuit that receives an output of the input circuit and outputs a multiplication result, wherein: (b) the input circuit includes: (C) wherein the multiplier core circuit is formed by first, second, third and fourth transistors having an emitter or a source coupled thereto. And the first, second, third and fourth transistors are comprised of a quadri-tail cell driven by a single tail current,
(D) the bases or gates of said first, second, third and fourth transistors form first, second, third and fourth input terminals of said quadretail cell, respectively; The collectors or drains of the second and third transistors are connected together to form a first output terminal of the quadrature cell, and the collectors or drains of the first and fourth transistors are connected together. To form a second output terminal of the quadrature cell, and (f) a first and a second output from the composite differential amplifier circuit according to the input first and second input voltages. , A third and a fourth output voltage are respectively applied to the first, second, third and fourth input terminals of the quadri-tail cell, and (g) the A multiplying circuit, wherein a differential output including a multiplication result of the first and second input voltages is taken out from first and second output terminals.