JPH11259054A - Drive control circuit in liquid crystal display and method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of picture quality caused by variations in manufacturing components of sample-hold circuits by averaging the levels of output signals of the sample-hold circuits supplied to each pixel of a liquid crystal panel. SOLUTION: This drive control circuit is provided with plural sample-hold circuits 10, a shift register circuit 20 for controlling the sample-hold circuits 10, and plural selector circuits 40 for selectively transmitting the output signals of the sample-hold circuits 10 to the drive circuit of a liquid crystal panel; and controls the sample-hold circuits 10 so that the shift register circuit 20 may sample-hold a video signal at each position in each line by a different sample-hold circuit 10 by the line or field, and each sample-hold circuit 10 branches an output signal to send it to plural selector circuits 30, and each selector circuit 30 outputs a video signal at the position corresponding to the position of each selector circuit 30 in the line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving control circuit and a driving method for an active matrix type liquid crystal display device, and more particularly to a method for controlling image quality degradation caused by a difference in output voltage of a sample and hold circuit for sampling and holding a video signal. The present invention relates to a drive control circuit in a liquid crystal display device and a driving method thereof.

[0002]

2. Description of the Related Art A driving control circuit and a driving method thereof in a conventional liquid crystal display device will be described with reference to FIGS. FIG. 4 is a circuit diagram showing a circuit configuration of a drive control circuit in a conventional liquid crystal display device, and FIG. 5 is a time chart showing a drive method by the drive control circuit of FIG.

Referring to FIG. 4, a driving control circuit of a conventional liquid crystal display device includes a sample and hold circuit 10 for sampling and holding a video signal, a shift register circuit 20 for controlling the sample and hold circuit 10, and a sample and hold circuit 10. A selector circuit 30 for selectively transmitting an output signal to a driver circuit of the liquid crystal panel. Sixteen sample hold circuits 10 are provided corresponding to video signals. The shift register circuit 20 includes 16 flip-flop circuits 21 corresponding to the 16 sample-hold circuits 10 on a one-to-one basis. Eight selector circuits 30 are provided in fixed correspondence with the 16 sample-and-hold circuits 10 on a one-to-two basis.

In the following description, when it is necessary to specify each sample-and-hold circuit 10, flip-flop circuit 21, and selector circuit 30, the flip-flop circuit 21-1, sample-and-hold circuit 10 -1, the selector circuit 30-1. Therefore, referring to FIG. 4, the flip-flop circuits 21-1 to 21-16
Correspond to the sample hold circuits 10-1 to 10-16, respectively. Further, the sample hold circuit 10-1 to the sample hold circuit 10-
8 and sample hold circuits 10-9 to 10-16 correspond to the selector circuits 30-1 to 30-8, respectively.

The shift register circuit 20 has a clock signal CLK and a start pulse signal SP for starting the sample and hold of the video signal by the sample and hold circuit 10.
Is entered. When the flip-flop circuit 21 of the shift register circuit 20 receives the start pulse signal SP, the flip-flop circuit 21-1 sequentially outputs a sample clock signal SC for operating the sample and hold circuit 10 in synchronization with the clock signal CLK. Thus, the sample clock signal SC synchronized with the clock signal CLK is sequentially supplied from the sample hold circuit 10-1 to the sample hold circuit 10-16.

The sample and hold circuit 10 sequentially samples and holds a video signal synchronized with the input sample clock signal SC. Then, the held video signal is output to the corresponding selector 30.

[0007] Upon receiving the selector signal SE, the selector circuit 30 performs serial / parallel conversion on the video signal input from the sample-and-hold circuit 10, and divides the frequency by ８ and outputs the resulting signal. Thereby, a video signal is sent to each pixel of the liquid crystal panel via the driver circuit.

Referring to the time chart of FIG. 5, the output of the video signal DATA starts with the oscillation of the start pulse signal SP, and the selector signal SE is output from the eighth clock from the clock signal at the time of oscillation of the start pulse signal SP. I have. As a result, the selector circuit 30 outputs D1 to D8 of the video signal DATA, and is controlled by the selector signal SE to output D9 of the video signal DATA.
To D16 are output. Here, the selector signal SE
Is supplied to the selector circuit 30 at a timing set according to the start pulse signal SP. In the example of FIG.
After the start pulse signal SP is oscillated, the selector signal SE is supplied to the selector circuit 30 after a lapse of eight clocks of the clock signal CLK, and the output of the video signal from the selector circuit 30-1 to the driver circuit is started in order.

[0009]

As described above, the drive control circuit and the drive method thereof in the conventional liquid crystal display device have a correspondence relationship between the line in the video signal for one line or one field and the sample-and-hold circuit 10. Fixed. For example, in FIG. 4, the first line of the liquid crystal display device is an output signal of the sample and hold circuit 10-1, and the second line is an output signal of the sample and hold circuit 10-2. An image is displayed according to the output signal from.
Therefore, if the elements in each sample-and-hold circuit have manufacturing variations, the output signal level of the sample-and-hold circuit will vary from line to line. For this reason, even if the same video signal is input, the output voltage fluctuates for each line, resulting in a stripe-like shading on the screen, and the image quality is greatly deteriorated.

An object of the present invention is to average the level of the output signal of the sample-and-hold circuit supplied to each pixel of the liquid crystal panel, thereby reducing the deterioration of the image quality due to manufacturing variations of the components of the sample-and-hold circuit. It is an object of the present invention to provide a driving control circuit and a driving method thereof in a liquid crystal display device which can prevent the occurrence of the driving control circuit.

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention controls a driver circuit for driving a drain electrode of an active matrix type liquid crystal display panel having a gate electrode, a drain electrode and a common electrode line by line. A plurality of sample-and-hold circuits that sample and hold a video signal, a shift register circuit that controls the sample-and-hold circuit, and a plurality of circuits that selectively send output signals of the sample-and-hold circuit to a driver circuit of a liquid crystal panel. The shift register circuit controls the sample-and-hold circuit so as to sample and hold the video signal at each position in each line by a different sample-and-hold circuit in line or field units. The hold circuit splits the output signal Serial feed to a plurality of said selector circuit,
Each of the selector circuits to which video signals have been input from the plurality of sample and hold circuits outputs a video signal at a position corresponding to the position of each of the selector circuits on the line.

According to a second aspect of the present invention, in the driving control circuit of the liquid crystal display device, the shift register circuit includes a plurality of flip-flop circuits corresponding to the sample-and-hold circuits on a one-to-one basis. When the shift register circuit inputs a start pulse signal, the shift register circuit sequentially enters the output preparation state for each clock signal, and the sample is sequentially output from the flip-flop circuit which was in the output preparation state at that time. The number of sample clock signals corresponding to the number of the hold circuits is output, and each of the sample and hold circuits is
A video signal synchronized with a sample clock signal input from the corresponding flip-flop circuit is sequentially sampled and held.

According to a third aspect of the present invention, in the drive control circuit of the liquid crystal display device, the shift register circuit includes a plurality of flip-flop circuits corresponding to the sample-and-hold circuits on a one-to-one basis. From the time when the shift register circuit receives the start pulse signal, a sample clock signal is sequentially output for each clock signal, and each of the sample and hold circuits is synchronized with the sample clock signal input from the corresponding flip-flop circuit. The video signal is supplied to the sample and hold circuit while sequentially sampling and holding the video signal and changing the output timing of the video signal relative to the output timing of the start pulse signal.

According to another aspect of the present invention to achieve the above object, the present invention comprises a plurality of sample-and-hold circuits for sampling and holding a video signal, and a plurality of flip-flop circuits corresponding to the sample-and-hold circuits on a one-to-one basis. An active matrix type having a shift register circuit for controlling a sample and hold circuit, and a plurality of selector circuits for selectively transmitting an output signal of the sample and hold circuit to a driver circuit of a liquid crystal panel, and having a gate electrode, a drain electrode, and a common electrode. In the driving method of the drive control circuit for controlling the driver circuit for driving the drain electrode of the liquid crystal display panel line by line,
The sample-and-hold circuit is controlled so that the video signal at each position in each line is sampled and held by a different sample-and-hold circuit, and the output of the sample-and-hold circuit is branched and sent to the plurality of selector circuits. Outputting the video signal at each position of the selector circuit at a position corresponding to the position of the video signal on the line among the selector circuits to which the video signals are input from the plurality of sample and hold circuits. And

According to a fifth aspect of the present invention, in the driving method of the drive control circuit in the liquid crystal display device, each of the flip-flop circuits is set to an output ready state for sequentially outputting a sample clock signal for each clock signal, and at an arbitrary timing. A start pulse signal is oscillated, and a sample clock signal is sequentially output from the flip-flop circuit which was in an output ready state at the time when the start pulse signal was input, and a video signal synchronized with the sample clock signal is output from the sample clock. The sample-and-hold circuit corresponding to the flip-flop circuit that outputs the signal sequentially samples and holds.

According to a sixth aspect of the present invention, in the driving method of the drive control circuit in the liquid crystal display device, each of the flip-flop circuits sequentially outputs a sample clock signal for each clock signal from the time when the start pulse signal is oscillated. The video signal was output at an arbitrary timing while changing the time from the start of the start pulse signal to the output of the video signal, and the video signal synchronized with the sample clock signal was output as the sample clock signal. The sample-and-hold circuit corresponding to the flip-flop circuit sequentially samples and holds.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic diagram showing a concept of a drive control circuit in a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a configuration of a main part of the drive control circuit of FIG.

Referring to FIG. 1, the drive control circuit of the liquid crystal display device of the present embodiment includes a sample and hold circuit 10 for sampling and holding a video signal, a shift register circuit 20 for controlling the sample and hold circuit 10, and a sample and hold circuit. And a selector circuit 30 for selectively transmitting the output signal of C.10 to the driver circuit of the liquid crystal panel. Sixteen sample hold circuits 10 are provided corresponding to video signals. The shift register circuit 20 includes 16 flip-flop circuits 21 corresponding to the 16 sample-hold circuits 10 on a one-to-one basis. The selector circuit 30
One-to-two corresponds to six sample-and-hold circuits 10, and 8
Are provided. The above configuration is the same as the drive control circuit in the conventional liquid crystal display device.

In the following description, when it is necessary to specify each of the sample-and-hold circuits 10, the flip-flop circuits 21 and the selector circuits 30, the numbers shown are used to designate the flip-flop circuits 21-1 and the sample-and-hold circuits 10-1. -1, the selector circuit 30-1. Therefore, referring to FIG. 4, the flip-flop circuits 21-1 to 21-16
Correspond to the sample hold circuits 10-1 to 10-16, respectively. This point is also the same as the drive control circuit in the conventional liquid crystal display device.

In the present embodiment, the eight selector circuits 30 correspond to the sample-and-hold circuit 10 on a one-to-two basis, but the correspondence is not fixed, and one selector circuit 30 includes a plurality of selector circuits 30. It is associated with the sample hold 10 with appropriate flexibility. In the present embodiment, as shown in FIG. 2, the video signals output from the odd-numbered sample hold circuits 10-1, 3,...
-1, 3, 5, and 7 and output from the even-numbered sample hold circuits 10-2, 4,..., 16 are converted to even-numbered selector circuits 30.
-2, 4, 6, 8. The individual correspondence between the sample hold circuit 10 and the selector circuit 30 may be arbitrarily determined based on the relationship between the video signal held by the sample hold circuit 10 and the video signal to be output from the selector circuit 30. Needless to say, it is not limited to the specific correspondence shown in the present embodiment.

Hereinafter, the operation of the present embodiment will be described. In the present embodiment, the 16 flip-flop circuits 21 of the shift register circuit 20 are in a state where the sample clock signal SC can be sequentially output for each clock signal CLK (hereinafter, an output preparation state). The transition to the output preparation state in each flip-flop circuit 21 is performed in the following manner.
It is executed in a cyclic manner from 21-16 to 21-1 to 21-16.

When the shift register circuit 20 receives the start pulse signal SP, 16 sample clock signals SC are sequentially output from the flip-flop circuit 21 which is ready to output the sample clock signal SC at that time. For example, when the flip-flop circuit 21-5 is ready to output the sample clock signal SC, the shift register circuit 20 outputs the start pulse signal SP
Is input, the sample clock signal SC is output from the flip-flop circuit 21-5 to the flip-flop circuit 21-16.
Returning to step 1, the sample clock signal SC is output to the flip-flop circuit 21-4.

Each sample and hold circuit 10 sequentially samples and holds a video signal synchronized with the sample clock signal SC input from the corresponding flip-flop circuit 21 of the shift register circuit 20. That is, in the above example, the sample and hold of the video signal is started from the sample and hold circuit 10-5 corresponding to the flip-flop circuit 21-5, and the sample and hold is sequentially performed up to the sample and hold circuit 10-16. Sample hold is performed from 10-1 to the sample hold circuit 10-4.

Therefore, the first sample clock signal SC can be output from any flip-flop circuit 21 by controlling the timing of the start pulse signal SP. It can be taken into the sample and hold circuit 10.

Next, the video signal held by the sample and hold circuit 10 is sent to the selector circuit 30 and output according to the selector signal SE. The selector signal SE is
The signal is supplied to the selector circuit 30 at a timing set according to the start pulse signal SP. Therefore, by appropriately controlling the timing of supplying the selector signal to the selector circuit 30, the desired video signal can be output from the desired selector circuit 30 corresponding to the position on the line of the video signal. For example, if the head video signal of the line is output from the selector circuit 30-1, the head video signal of the line output from any of the sample-and-hold circuits 10 is output from the selector circuits 30-1, 3, 5, 7, and 7.
Is controlled to output the video signal from the selector circuit 30-1 according to the timing of the supply of the selector signal SE.

Next, another embodiment of the present invention will be described. This embodiment is configured similarly to the above embodiment described with reference to FIG. However, the 16 flip-flop circuits 21 in the shift register circuit 20 sequentially output the sample clock signal SC for each clock signal CLK from the flip-flop circuit 21-1 after receiving the start pulse signal SP. The output of the sample clock signal SC is 21-1 to 21-16 → 21-1.
Repeat twice in the order of ~ 21-16.

In this embodiment, the output timing of the start pulse signal SP and the output timing of the video signal DATA are appropriately changed. FIG. 3 shows a relationship between output timings of the start pulse signal SP and the video signal DATA. Referring to FIG. 3, in the first start pulse signal SP1, the output of the video signal DATA is started together with the oscillation of the start pulse signal SP1, and in the second start pulse signal SP2, after the start pulse signal SP2 oscillates, The output of the video signal DATA is started after the elapse of two clocks of the clock signal CLK. Similarly, the oscillation timing of the start pulse signal SP and the video signal DA
The output timing of the TA shifts by two clocks of the clock signal CLK each time the number of times increases, and in the eighth start pulse signal SP8, after the start pulse signal SP8 oscillates, the video signal 14 clocks after the clock signal CLK. Output of DATA is started.

As described above, the shift register circuit 20
Of the start pulse signal S
After receiving P, the flip-flop circuit 21-1 sequentially outputs the sample clock signal SC for each clock signal CLK. Therefore, when the first start pulse signal SP1 is oscillated, it corresponds to the flip-flop circuit 21-1. D1 of the video signal DATA is sampled and held by the sample and hold circuit 10-1, and similarly, D2 and D2 of the video signal DATA are
D16 is sampled and held. And
When the second start pulse signal SP2 is oscillated,
Sample and hold circuit 10 corresponding to flip-flop circuit 21-3 shifted by two clocks of clock signal CLK
-3 of the video signal DATA is sampled and held, and similarly, the sample and hold circuits 10-4 to 16 sample and hold D2 to D14 of the video signal DATA.
D15 of the ATA is sampled and held, and D16 of the video signal DATA is sampled and held by the sample and hold circuit 10-2.

As described above, by controlling the difference between the oscillation timing of the start pulse signal SP and the output timing of the video signal DATA, the video signal at the head of a predetermined line is taken into an arbitrary sample and hold circuit 10. It is possible to make it.

In the present embodiment, since 16 sample hold circuits 10 are provided, if the oscillation timing of the start pulse signal SP and the output timing of the video signal DATA are shifted by 16 clocks of the clock signal CLK, the line is switched. D1 which is the first video signal DATA is 1
As in the case of the first oscillation of the start pulse signal SP1, the sample and hold is performed by the sample and hold circuit 10-1. Therefore, as shown in FIG. 3, the oscillation timing of the start pulse signal SP and the video signal DA
When the output timing of the TA is controlled so as to be shifted by two clocks of the clock signal CLK, in the ninth start pulse signal SP, the timing between the oscillation timing of the start pulse signal SP and the output timing of the video signal DATA is used. Is returned to '0', and the start pulse signal S
The output of the video signal DATA is started with the oscillation of P.

The selector circuit 30 is similar to the selector circuit 30 in the above embodiment described with reference to FIG.
Controlled by the selector signal SE, the desired video signal is output from the desired selector circuit 30 corresponding to the position on the line of the video signal.

As described above, the video signal at each position on the line is sampled and held using different sample and hold circuits for each line or each field, so that each pixel of the liquid crystal panel can be sampled and held for each line or each field. Video signals that have passed through different sample and hold circuits are supplied for each field. Therefore, the level of the output signal of the sample and hold circuit supplied to each pixel of the liquid crystal panel can be averaged.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments. For example, in the above embodiment,
Although the video signal at each position on the line is controlled to be sampled and held by a different sample and hold circuit for each line, a similar operation may be performed for each field or every several fields.

[0035]

As described above, the drive control circuit and the drive method in the liquid crystal display device according to the present invention provide a different sample hold circuit for each pixel of the liquid crystal panel for one line or one field to several fields. Since it is possible to supply a video signal that has passed through the circuit, the level of the output signal of the sample and hold circuit supplied to each pixel of the liquid crystal panel can be averaged. There is an effect that deterioration of image quality due to manufacturing variation can be prevented.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a concept of a drive control circuit in a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a main part of the drive control circuit of FIG. 1;

FIG. 3 is a time chart illustrating an operation of a drive control circuit in a liquid crystal display device according to another embodiment of the present invention.

FIG. 4 is a schematic diagram illustrating the concept of a drive control circuit in a conventional liquid crystal display device.

FIG. 5 is a time chart illustrating an operation of a conventional drive control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Sample hold circuit 20 Shift register circuit 21 Flip-flop circuit 30 Sample hold circuit

Claims (6)

[Claims] 1. A drive control circuit for controlling a driver circuit for driving a drain electrode of an active matrix type liquid crystal display panel having a gate electrode, a drain electrode and a common electrode line by line. A sample-and-hold circuit; a shift register circuit for controlling the sample-and-hold circuit; and a plurality of selector circuits for selectively sending an output signal of the sample-and-hold circuit to a driver circuit of a liquid crystal panel. Or, on a field-by-field basis, the sample-and-hold circuit is controlled so as to sample and hold a video signal at each position in each line by a different sample-and-hold circuit. Sent to the selector circuit, more than one A drive control circuit in a liquid crystal display device, wherein each of the selector circuits to which a video signal is input from the sample and hold circuit outputs a video signal at a position corresponding to a position of each of the selector circuits on the line. 2. A shift register circuit comprising: a plurality of flip-flop circuits corresponding to the sample-and-hold circuits on a one-to-one basis; each of the flip-flop circuits sequentially outputting a sample clock signal for each clock signal; When the shift register circuit receives a start pulse signal, the shift register circuit outputs a number of sample clock signals corresponding to the number of the sample and hold circuits in order from the flip-flop circuits that are in the output preparation state at that time. 2. The drive control circuit according to claim 1, wherein each of the sample and hold circuits sequentially samples and holds a video signal synchronized with a sample clock signal input from the corresponding flip-flop circuit. 3. The shift register circuit includes a plurality of flip-flop circuits corresponding to the sample-and-hold circuits on a one-to-one basis, and each of the flip-flop circuits includes a plurality of flip-flop circuits from a time point at which the shift register circuit receives a start pulse signal. , A sample clock signal is sequentially output for each clock signal, and each of the sample and hold circuits sequentially samples and holds a video signal synchronized with the sample clock signal input from the corresponding flip-flop circuit, and the start pulse signal 2. The drive control circuit according to claim 1, wherein the video signal is supplied to the sample-and-hold circuit while changing the output timing of the video signal relative to the output timing of the liquid crystal display device. 4. A shift register circuit that includes a plurality of sample and hold circuits that sample and hold a video signal, a plurality of flip-flop circuits corresponding to the sample and hold circuits on a one-to-one basis, and controls the sample and hold circuit; A plurality of selector circuits for selectively transmitting an output signal of the sample hold circuit to a driver circuit of the liquid crystal panel, and a drain electrode of an active matrix type liquid crystal display panel having a gate electrode, a drain electrode, and a common electrode for each line. In a driving method of a drive control circuit for controlling a driver circuit to be driven, the sample-and-hold circuit is controlled so that a video signal at each position in each line is sampled and held by a different sample-and-hold circuit in line or field units. The output of the sample and hold circuit Branching and sending to the plurality of selector circuits, the video signal at each position on the line, the position of the video signal in the line among the selector circuits which input the video signal from the plurality of sample and hold circuits; A driving control circuit in the liquid crystal display device, wherein a signal is output from each of the selector circuits at a position corresponding to (a). 5. Each of the flip-flop circuits is set to an output ready state for sequentially outputting a sample clock signal for each clock signal, oscillating a start pulse signal at an arbitrary timing, and outputting when the start pulse signal is input. A sample clock signal is sequentially output from the flip-flop circuit in the ready state, and a video signal synchronized with the sample clock signal is output by the sample-and-hold circuit corresponding to the flip-flop circuit that output the sample clock signal. 5. The method according to claim 4, wherein the sample and hold are sequentially performed. 6. A flip-flop circuit sequentially outputs a sample clock signal for each clock signal from the time when the start pulse signal is oscillated, and outputs a video signal from the start of the start pulse signal. The video signal synchronized with the sample clock signal is output at an arbitrary timing while changing the time until time, and is sequentially sampled and held by the sample and hold circuit corresponding to the flip-flop circuit that has output the sample clock signal. 5. The driving method of a drive control circuit in a liquid crystal display device according to claim 4, wherein: