JPH11238903A - Semiconductor device, semiconductor wafer, and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device and semiconductor wafer, whereby function tests can be accurately made in a wafer state and provide a semiconductor device which provides an accurate output. SOLUTION: A field oxide film 97 is made so as to cover a scribing region 80 whereby the thick field oxide film 97 prevents a light P from penetrating from the top face of a wafer 72 into the scribing region 80. As a result, if a P-N junction is formed at the scribing region 80, no photocurrent flows in the P-N junction and hence the photocurrent flowing in a phototransistor adjacent to the scribing region 80 can be accurately measured, i.e., the function tests can be accurately conducted in a wafer state. Even in a semiconductor device mounting a phototransistor PT obtd. by cutting the scribing region 80, an accurate output corresponding to the light P can be obtd.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, a semiconductor wafer, and a method for manufacturing a semiconductor device.
The present invention relates to a semiconductor device including a semiconductor chip on which a light receiving element is mounted.

[0002]

2. Description of the Related Art A phototransistor is known as one of light receiving elements. A conventional method for manufacturing a phototransistor will be described with reference to FIGS. 15A to 19A. First,
As shown in FIG. 15A, a wafer 2 made of an N-conductivity type silicon semiconductor is prepared, and a plurality of chip forming regions 6, 8,... And scribe regions 10,.
・ ・ Set

Next, a resist 14 is formed on the wafer 2 and boron (B) is ion-implanted using the resist 14 as a mask. Thereby, the chip formation regions 6, 8,
.. Of the NMOS formation region 12 and the scribe region 1
At 0, boron is implanted. The region into which boron has been implanted is indicated by a cross in the figure.

After the resist 14 is removed, annealing (heating) is performed to form P-well regions 16 and 18 as shown in FIG. 15B. Next, another resist 22 is formed on the wafer 2, and boron is ion-implanted using the resist 22 as a mask. As a result, boron is implanted into the base formation regions 20 of the chip formation regions 6, 8,.

After the resist 22 is removed, annealing is performed to form a P ⁻ type active base 24 as shown in FIG. 16A. Next, LOCOS (Local Oxid
The field oxide film 26 is formed at an appropriate position on the surface of the wafer 2 by using a method such as an oxidation of silicon method.

Next, as shown in FIG. 16B, a gate oxide film 28 is formed, and a gate 30 made of polysilicon is formed on the gate oxide film 28 in the NMOS formation region 12.

[0007] Next, as shown in FIG.
A resist 34 is formed thereon, and boron is ion-implanted using the resist 34 as a mask. As a result, boron is implanted into the external base formation region 32 and the scribe region 10 of the base formation region 20.

Next, after removing the resist 34, FIG.
As shown in FIG. 7B, another resist 42 is formed, and phosphorus (P) is ion-implanted using the resist 42 as a mask.
Thereby, the emitter formation region 3 of the base formation region 20 is formed.
6, collector formation regions 38 and 40, NMOS formation region 1
Phosphorus is implanted in 2 and the scribe region 10. The region into which phosphorus has been implanted is indicated by an O mark in the figure.

After the resist 42 is removed, annealing is performed to obtain a P ⁺ -type external base 44, an N ⁺ -type emitter 46, and a collector 4, as shown in FIG. 18A.
8, 50, and a source S and a drain D are formed.
A P + N ⁺ region 16a is formed above P well region 16. Thereafter, an interlayer film 52 is formed, and a contact hole 54 is provided at a predetermined position in the formed interlayer film 52.

Next, as shown in FIG. 18B, an aluminum wiring 56 is formed and covered with a passivation film 58.

By cutting the wafer 2 thus formed at the scribe area 10 as shown in FIG. 19A, IC chips 62, 64,...

As shown in FIG. 19A, the phototransistor PT includes a collector 48, an external base 44, an active base 24, and an emitter 46, and is used for, for example, a light receiving portion of an image sensor.

The light P incident from above the phototransistor PT reaches the active base 24 via a light-transmitting passivation film 58 and an interlayer film 52, and a current I1 flows between the collector 48 and the emitter 46 of the phototransistor PT. Flows. By knowing the magnitude of the current I1, the intensity of the light P can be detected.

[0014]

However, the above-described method for manufacturing the phototransistor PT has the following problems. In order to perform the function test of the phototransistor PT, it is efficient to perform the function test in a wafer state before cutting into individual chips. However, in a conventional manufacturing method, it is difficult to perform a function test in such a wafer state. This is for the following reason.

As shown in FIG. 18A, the scribe area 1
At 0, a P-well region 16 is formed. The P well region 16 is formed simultaneously when forming a P well region (not shown) for electrically isolating a plurality of elements provided in each chip formation region (for example, chip formation region 6). The scribe area has been conventionally formed in the scribe area 10.

However, when the P well region 16 exists,
When the upper surface of the wafer 2 is irradiated with the light P, the current (I) is applied between the collector 48 and the P well region 16 in addition to the current I1.
2) flows. This is because the P well region 16 is coupled to the ground potential via the stray capacitance, so that when the scribe region 10 is irradiated with light P, the P well region 1
This is because a photocurrent flows through the PN junction between the substrate 6 and the N-type substrate portion 4.

Therefore, the collector current flowing through the phototransistor PT adjacent to the scribe region 10 cannot be measured accurately. For this reason, it was not possible to perform a function test in a wafer state.

Further, the phototransistor P as described above
The manufacturing method of T further has the following problem.
When the formed wafer 2 is cut into chips, FIG.
As shown in (1), there is a case where cutting is performed with a deviation from the original scribe area 10 due to a processing error. In such a case, the P-well region 16 remains in the IC chip 62.

In this case, the light P is applied to the phototransistor PT.
, A current (I3) flows between the collector 48 and the P-well region 16 in addition to the current I1. Therefore, the intensity of the light P impinging on the phototransistor PT cannot be measured accurately.

The present invention solves such a problem,
It is an object of the present invention to provide a method of manufacturing a semiconductor device and a semiconductor wafer capable of accurately performing a function test in a wafer state, and a semiconductor device capable of obtaining an accurate output.

[0021]

Means for Solving the Problems, Functions and Effects of the Invention
In the method of manufacturing a semiconductor device according to the first aspect, the region to be cut is covered with a light shielding layer that does not substantially transmit light. The semiconductor wafer according to claim 6 is characterized in that the area to be cut is covered with a light shielding layer that does not substantially transmit light.

Therefore, the light irradiated from the upper surface of the wafer does not enter the cut region. As a result, even if a PN junction is formed in the region to be cut, no photocurrent flows through the PN junction. Therefore, it is possible to accurately measure a photocurrent flowing through the light receiving element adjacent to the cut region. That is, the function inspection in the wafer state can be accurately performed.

When the wafer is cut into individual semiconductor chips, the upper portion near the end of the semiconductor chip is covered with the light shielding layer. Therefore, the light applied to the upper surface of the semiconductor chip does not enter from near the end of the semiconductor chip. As a result, if the P
Even if an N junction is formed,
Photocurrent does not flow. Therefore, the photocurrent flowing through the light receiving element near the end of the semiconductor chip can be accurately measured. That is, it is possible to realize a semiconductor device capable of obtaining an accurate output with respect to the irradiated light.

In the method of manufacturing a semiconductor device according to a second aspect, when the insulating layer for element isolation is formed, the area to be cut is simultaneously covered with the insulating layer.

Therefore, the thick insulating layer allows
Light from the upper surface of the wafer can be prevented from entering the planned cutting area. Further, a light shielding layer that covers an area to be cut can be formed without providing a dedicated process. Therefore, the light shielding layer can be formed without increasing the manufacturing cost.

Further, since the light shielding layer is formed in the insulating layer forming step for element isolation, which is performed relatively early in the semiconductor device manufacturing process, impurities which may form a PN junction are cut off. The light shielding layer can prevent the light from being introduced into the predetermined area. For this reason, it is possible to more accurately measure the photocurrent flowing through the light receiving element adjacent to the planned cutting region.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, when the metal wiring layer is formed, the area to be cut is simultaneously covered with the metal wiring layer.

Therefore, the light from the upper surface of the wafer can be prevented from penetrating into the area to be cut by the metal wiring layer that reflects light. Further, a light shielding layer that covers an area to be cut can be formed without providing a dedicated process. Therefore, the light shielding layer can be formed without increasing the manufacturing cost.

According to a fourth aspect of the present invention, there is provided the method of manufacturing a semiconductor device, wherein the impurity which may form a PN junction in the region to be cut includes:
It is characterized in that it is substantially prevented from being introduced into the to-be-cut area. The semiconductor wafer according to claim 7 is characterized in that substantially no PN junction is formed in the region to be cut.

Therefore, even if the light irradiated from the upper surface of the wafer enters the planned cutting region, no photocurrent flows through the planned cutting region. Therefore, it is possible to accurately measure a photocurrent flowing through the light receiving element adjacent to the cut region. That is, the function inspection in the wafer state can be accurately performed.

Further, when the wafer is cut into individual semiconductor chips, even if light applied to the upper surface of the semiconductor chip enters from near the end of the semiconductor chip, a photocurrent does not flow to portions other than the light receiving element. Absent. Therefore, the photocurrent flowing through the light receiving element near the end of the semiconductor chip can be accurately measured. That is, it is possible to realize a semiconductor device capable of obtaining an accurate output with respect to the irradiated light.

According to a fifth aspect of the present invention, in the step of introducing an impurity, the region to be cut is masked with an impurity introduction blocking layer in the step of introducing the impurity.

Therefore, by using, for example, a resist or an insulating film formed at the same time as forming an insulating layer for element isolation as an impurity introduction blocking layer, impurities which may form a PN junction are removed by the cutting. It can be easily prevented from being introduced into the region.

The semiconductor device according to the eighth aspect is characterized in that the upper part near the end of the semiconductor chip is covered with a light shielding layer which does not substantially transmit light.

Therefore, the light irradiated on the upper surface of the semiconductor chip does not enter from near the end of the semiconductor chip. As a result, even if a PN junction is formed under the light shielding layer, no photocurrent flows through the PN junction. Therefore, the photocurrent flowing through the light receiving element near the end of the semiconductor chip can be accurately measured. That is, an accurate output can be obtained for the irradiated light.

[0036]

1A to 5B show a method of manufacturing a semiconductor device according to an embodiment of the present invention, in which a semiconductor device having an IC chip (semiconductor chip) mounted with a phototransistor (light receiving element) is manufactured. FIG. 4 shows a cross-sectional view of a main part for describing a method. A method for manufacturing such a semiconductor device will be described below.

First, as shown in FIG. 1A, a wafer 72 (semiconductor wafer) made of an N-conductivity type silicon semiconductor
Are prepared, and a plurality of chip forming regions 76 are provided on the wafer 72.
, And scribe areas 80,... (Scheduled cut areas) are set.

Next, a resist 84 (impurity introduction blocking layer) is formed on the wafer 72, and using the resist 84 as a mask, boron (B) (an impurity which may form a PN junction in a region to be cut) is ionized. inject. As a result, boron is implanted into the NMOS formation regions 82 of the chip formation regions 76, 78,... At this time, since the upper part of the scribe area 80 is covered with the resist 84,
Boron is not implanted into the scribe region 80.
The region into which boron has been implanted is indicated by a cross in the figure.

After the resist 84 has been removed, annealing (heating) is performed to obtain the NMO, as shown in FIG.
P well region 88 is formed in S formation region 82. Next, another resist 92 is formed on the wafer 72, and boron is ion-implanted using the resist 92 as a mask. As a result, boron is implanted into the base formation regions 90 of the chip formation regions 76, 78,... At this time,
The upper portion of the scribe region 80 is covered with the resist 92 as in the conventional manufacturing method (see FIG. 15B).

After the resist 92 is removed, annealing is performed to form the base forming region 90 as shown in FIG. 2A.
Thus, a P ^- type active base 94 is formed. Next, LO
A field oxide film 96 (an insulating layer for element isolation) is formed at an appropriate position on the surface of the wafer 72 by using a COS method or the like. In this step, a field oxide film 97 covering the upper portion of the scribe region 80 and its vicinity is formed at the same time. This field oxide film 97 corresponds to the light shielding layer and the impurity introduction blocking layer.

Next, as shown in FIG. 2B, a gate oxide film 98 is formed, and a gate 100 made of polysilicon is formed on the gate oxide film 98 in the NMOS formation region 82.

Next, as shown in FIG.
A resist 104 is formed thereon, and boron is ion-implanted using the resist 104 as a mask. As a result, boron is implanted into the external base formation region 102 of the base formation region 90. At this time, since the upper portion of scribe region 80 is covered with field oxide film 97 and resist 104, boron is not implanted into scribe region 80.

Next, after removing the resist 104, another resist 112 is formed as shown in FIG. 3B, and phosphorus (P) is ion-implanted using the resist 112 as a mask. Thereby, the emitter formation region 106, the collector formation regions 108 and 110 of the base formation region 90, the NMOS,
Phosphorus is implanted into the formation region 82. The region into which phosphorus has been implanted is indicated by an O mark in the figure. At this time, since the upper portion of the scribe region 80 is covered with the field oxide film 97, phosphorus is not injected into the scribe region 80.

After the resist 112 is removed, annealing is performed to form a P ⁺ -type external base 114, an N ⁺ -type emitter 116, collectors 118 and 120, a source S, and a drain, as shown in FIG. 4A. D is formed. After that, an interlayer film 122 is formed, and a contact hole 124 is provided at a predetermined position of the formed interlayer film 122.

Next, as shown in FIG. 4B, an aluminum wiring 126 is formed and covered with a passivation film 128.

The wafer 72 thus formed is
As shown in FIG. 5A, by cutting at the scribe area 80, IC chips 132, 134,...

As shown in FIG. 4B, in this embodiment, the field oxide film 9
7 to cover.

Therefore, the thick field oxide film 97 can prevent light P from the upper surface of the wafer 72 from entering the scribe region 80. As a result, even if a PN junction is formed in the scribe region 80, no photocurrent flows through the PN junction. Therefore, the photocurrent I1 flowing through the phototransistor PT adjacent to the scribe region 80 can be accurately measured. That is, the function inspection in the wafer state can be accurately performed.

As shown in FIG. 5A, when the wafer 72 is cut into individual IC chips 132, 134,..., For example, the vicinity of the end 132a of the IC chip 132 is covered with a field oxide film 97. Have been done. Therefore, the light P applied to the upper surface of the IC chip 132 does not enter the vicinity of the end 132a of the IC chip 132. As a result, even if a PN junction is formed under the field oxide film 97, no photocurrent flows through the PN junction. For this reason, the end 13 of the IC chip 132
The photocurrent I1 flowing through the phototransistor PT near 2a can be accurately measured. That is, an accurate output can be obtained for the irradiated light P.

Further, as shown in FIG. 5B, when the wafer 72 is cut off from the original scribe area 80 due to a processing error, the scribe remaining on the phototransistor PT side is cut. The upper portion of the region 80 is covered with the field oxide film 97. Therefore, IC
Photocurrent does not flow through the scribe region 80 due to the light P applied to the upper surface of the chip 132. Therefore,
Even in such a case, the intensity of the light P impinging on the phototransistor PT can be accurately measured.

In this embodiment, as shown in FIG. 2A, a field oxide film 96 used for element isolation or the like is used.
Is formed, the scribe region 80 is covered with the field oxide film 97 at the same time.

Therefore, field oxide film 97 covering scribe region 80 can be formed without providing a dedicated process. Therefore, the field oxide film 97 can be formed without increasing the manufacturing cost.

Further, the field oxide film 97 is formed at the same time as the step of forming the field oxide film 96 for element isolation, which is performed relatively early in the semiconductor device manufacturing process. Therefore, in the subsequent steps, it is possible to prevent impurities such as boron which may form a PN junction from being introduced into the scribe region 80 by the field oxide film 97. For this reason,
Phototransistor PT adjacent to scribe region 80
Can be measured more accurately.

In this embodiment, as shown in FIGS. 1A and 3A, by using the resist 84 and the field oxide film 97 as a mask, impurities which may form a PN junction such as boron are removed. It is substantially prevented from being introduced into the scribe area 80. Therefore, no PN junction is formed in the scribe region 80.

Therefore, as shown in FIG. 4B, even if the light P irradiated from the upper surface of the wafer 72 enters the scribe region 80 in some way, no photocurrent flows through the scribe region 80. Therefore, the photocurrent I1 flowing through the phototransistor PT adjacent to the scribe region 80 can be measured more accurately. That is, the function inspection in the wafer state can be performed more accurately.

When the wafer 72 is cut into individual IC chips 132, 134,..., As shown in FIG.
Does not flow from the vicinity of the end 132a of the IC chip 132, no photocurrent flows to portions other than the phototransistor PT. Therefore, the photocurrent I1 flowing through the phototransistor PT near the end 132a of the IC chip 132 can be measured more accurately. That is, a more accurate output can be obtained for the irradiated light P.

As described above (see FIG. 5B), even when the wafer 72 is cut off from the original scribe area 80 due to a processing error when the wafer 72 is cut, the wafer 72 remains on the phototransistor PT side. Scribe area 80
Does not have a PN junction. Therefore, the photocurrent does not flow through the scribe region 80 due to the light P applied to the upper surface of the IC chip 132. Therefore, even in such a case, the intensity of the light P impinging on the phototransistor PT can be accurately measured.

Next, FIGS. 6A to 9B are cross-sectional views of main parts for describing a method of manufacturing a semiconductor device having an IC chip on which a phototransistor is mounted according to another embodiment of the present invention. A method for manufacturing such a semiconductor device will be described below.

The steps in the first stage of this embodiment are the same as the steps shown in FIGS. 1A and 1B in the above embodiment. The steps shown in FIGS. 6A to 9B in this embodiment respectively correspond to the steps shown in FIGS. 2A to 5B in the above-described embodiment.

After performing the steps shown in FIGS. 1A and 1B,
As shown in FIG. 6A, the P ⁻ -type active base 94 is formed in the base forming region 90 by removing the resist 92 and thereafter performing annealing, as in the above-described embodiment. Next, the field oxide film 96 is formed at an appropriate position on the surface of the wafer 142 by using the LOCOS method or the like.

However, unlike this embodiment, in this embodiment, no field oxide film 97 (see FIG. 2A) covering the scribe region 80 is formed. However, as shown in FIG. 7A, since the upper portion of the scribe region 80 is covered with the resist 104 (impurity introduction blocking layer), boron is not implanted into the scribe region 80 in the step shown in FIG. 7A. . Therefore,
No PN junction is formed in the scribe region 80.

As shown in FIG. 7B, since the upper portion of the scribe region 80 is covered with the resist 112, phosphorus is not implanted into the scribe region 80.

In this embodiment, as shown in FIG. 8A, when the contact hole 124 is provided at a predetermined position in the interlayer film 122, the interlayer film 122 above the scribe region 80 is also removed.

Further, as shown in FIG. 8B, after forming the passivation film 128, the passivation film 128 above the scribe region 80 is removed. The step of removing the passivation film 128 is performed simultaneously with the step of opening a pad portion (not shown) for wire bonding.

In this way, as shown in FIG. 8B,
The substrate 74 is exposed in the scribe area 80. Therefore, the IC chips 144, 1
(See FIG. 9A) can be easily cut out.

Also in this embodiment, no PN junction is formed in the scribe region 80. Therefore, as shown in FIG. 9B, even when the wafer 142 is cut off from the original scribe area 80 due to a processing error when the wafer 142 is cut, the scribed light P applied to the upper surface of the IC chip 144 is used. No photocurrent flows through the region 80.

Next, FIGS. 10A to 11B are sectional views of a main part for describing a method of manufacturing a semiconductor device having an IC chip on which a phototransistor is mounted according to still another embodiment of the present invention. A method for manufacturing such a semiconductor device will be described below.

The first step of this embodiment is the same as that of the previous embodiment shown in FIGS. 1A to 1B and FIGS. 6A to 8A.
This is the same as the step shown in FIG. The steps shown in FIGS. 10A to 11B in this embodiment respectively correspond to the steps shown in FIGS. 8A to 9B in the above-described embodiment.

After performing the steps shown in FIGS. 1A to 1B and FIGS. 6A to 7B, as shown in FIG.
22 is formed. When the contact hole 124 is provided at a predetermined position of the interlayer film 122, the scribe region 80 is simultaneously formed.
Is also removed. Up to this point, it is the same as the above-described embodiment.

In this embodiment, as shown in FIG. 10B, in the step of forming the aluminum wiring 126 (metal wiring layer), an aluminum layer 127 covering the upper part of the scribe region 80 is formed at the same time. This aluminum layer 127 corresponds to the light shielding layer.

Therefore, the light reflecting aluminum layer 127
Accordingly, it is possible to prevent the light P from the upper surface of the wafer 152 from entering the scribe region 80. In addition, since the light shielding layer that covers the scribe region 80 can be formed without providing a dedicated process, the manufacturing cost does not increase.

As shown in FIG. 10B, a scribe region 80 is provided on a substrate 74 with a soft aluminum layer 127.
(See FIG. 11A) from the wafer 152, it is easy to cut out the IC chips 154, 156,.

Also, as shown in FIG. 11B, even when the wafer 152 is cut off from the original scribe area 80 due to a processing error when the wafer 152 is cut, the presence of the aluminum layer 127 covering the scribe area 80 does not exist. Accordingly, a photocurrent does not flow through the scribe region 80 due to the light P applied to the upper surface of the IC chip 154.

In the above embodiment, when the aluminum layer 127 is formed in the scribe region 80, the interlayer film 122 above the scribe region 80 is removed (see FIG. 10A), and the aluminum layer 127 is directly formed on the substrate 74. (See FIG. 10B), but it is not always necessary to form the aluminum layer 127 directly on the substrate 74. For example, as shown in FIG. 12B, an aluminum layer 127 may be formed on the interlayer film 122. In this case, as shown in FIG. 12A, when providing the contact hole 124 at a predetermined position of the interlayer film 122, the interlayer film 122 above the scribe region 80 is not removed.

In each of the above embodiments, no PN junction is formed in the scribe region 80.
The scribe area 80 may be configured to form a PN junction. 13A to 13B are cross-sectional views of main parts for describing a method of manufacturing such a semiconductor device.

The first step in this embodiment is the same as that shown in FIGS. 15A to 18 in the above-described conventional method for manufacturing a semiconductor device.
A is the same as the step shown in FIG. After the steps shown in FIGS. 15A to 17B are performed, FIG. 13A (steps similar to FIG. 18A)
As shown in FIG. 7, an interlayer film 52 is formed. When the contact hole 54 is provided at a predetermined position in the interlayer film 52, the interlayer film 52 above the scribe region 10 is removed at the same time. The steps up to here are the same as those of the above-described conventional method for manufacturing a semiconductor device.

In this embodiment, as shown in FIG. 13B, in the step of forming the aluminum wiring 56, an aluminum layer 57 covering the upper part of the scribe region 10 is simultaneously formed. This aluminum layer 57 corresponds to the light shielding layer. The steps shown in FIGS. 13A and 13B are the same as the steps shown in FIGS. 10A and 10B in the above embodiment.

Also in this embodiment, similarly to the above case, an aluminum layer 57 can be formed on the interlayer film 52 as shown in FIG. 14B. In this case, as shown in FIG. 14A, when the contact hole 54 is provided at a predetermined position of the interlayer film 52, the interlayer film 52 above the scribe region 10 is not removed.

As described above, the PN junction is formed in the scribe region 10 and the scribe region 10 is formed.
By forming the aluminum layer 57 covering the upper part of the semiconductor device, it is possible to accurately perform the function test in a wafer state without changing the conventional process much, and to obtain an accurate output with respect to the irradiated light. Can be realized.

In each of the above-described embodiments, the light shielding layer and the impurity introduction preventing layer are configured to be performed at the same time as performing the other steps. A dedicated process may be provided.

In each of the above embodiments, a semiconductor device having a phototransistor has been described as an example.
The present invention is not limited to this. For example,
The present invention can be applied to a semiconductor device having a photodiode, a semiconductor device having a semiconductor chip having a light receiving element, and a general semiconductor wafer having a light receiving element.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views of a main part for describing a method for manufacturing a semiconductor device having an IC chip 132 on which a phototransistor is mounted, which is a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG.

FIGS. 2A and 2B are cross-sectional views of main parts for describing a method of manufacturing a semiconductor device having an IC chip 132. FIGS.

FIGS. 3A and 3B are cross-sectional views of main parts for describing a method of manufacturing a semiconductor device having an IC chip 132. FIGS.

FIGS. 4A and 4B are cross-sectional views of main parts for describing a method of manufacturing a semiconductor device having an IC chip 132. FIGS.

FIGS. 5A and 5B are cross-sectional views of main parts for describing a method of manufacturing a semiconductor device having an IC chip 132. FIGS.

6A and 6B are main parts for describing a method for manufacturing a semiconductor device having an IC chip 144 having a phototransistor mounted thereon, which is a method for manufacturing a semiconductor device according to another embodiment of the present invention; It is sectional drawing.

7A and 7B are cross-sectional views of main parts for describing a method of manufacturing a semiconductor device including an IC chip 144.

8A and 8B are cross-sectional views of main parts for describing a method of manufacturing a semiconductor device having an IC chip 144.

FIGS. 9A and 9B are cross-sectional views of a main part for describing a method of manufacturing a semiconductor device having an IC chip 144. FIGS.

FIGS. 10A and 10B are main parts for describing a method for manufacturing a semiconductor device having an IC chip 154 on which a phototransistor is mounted, which is a method for manufacturing a semiconductor device according to still another embodiment of the present invention; FIG.

FIGS. 11A and 11B show an IC chip 15;
4 is a cross-sectional view of a main portion for describing a method for manufacturing a semiconductor device including No. 4.

FIG. 12A and FIG. 12B are cross-sectional views of main parts for describing a method of manufacturing a wafer 162 according to still another embodiment of the present invention.

FIG. 13A and FIG. 13B are cross-sectional views of main parts for describing a method of manufacturing a wafer 172 according to still another embodiment of the present invention.

FIGS. 14A and 14B are cross-sectional views of main parts for describing a method of manufacturing a wafer 182 according to still another embodiment of the present invention.

FIG. 15A and FIG. 15B are cross-sectional views of main parts for describing a method of manufacturing a semiconductor device having a conventional IC chip on which a phototransistor is mounted.

16A and 16B are cross-sectional views of main parts for describing a method of manufacturing a semiconductor device having a conventional IC chip on which a phototransistor is mounted.

17A and 17B are cross-sectional views of main parts for describing a method for manufacturing a semiconductor device having a conventional IC chip on which a phototransistor is mounted.

FIGS. 18A and 18B are cross-sectional views of main parts for describing a method of manufacturing a semiconductor device provided with a conventional IC chip on which a phototransistor is mounted.

FIG. 19A and FIG. 19B are cross-sectional views of main parts for describing a method of manufacturing a semiconductor device having a conventional IC chip on which a phototransistor is mounted.

[Explanation of symbols]

 72: wafer 80: scribe area 97: field oxide film I1: photocurrent P: light PT: phototransistor

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor device having a semiconductor chip on which a light receiving element is mounted, comprising the steps of: forming a semiconductor wafer having a chip forming region in which the light receiving element is arranged and a region to be cut adjacent to the chip forming region; In the forming step, a method of manufacturing a semiconductor device, comprising covering a region to be cut with a light shielding layer that does not substantially transmit light. 2. The method of manufacturing a semiconductor device according to claim 1, wherein, when forming an insulating layer for element isolation, said insulating layer covers an area to be cut at the same time. 3. The method of manufacturing a semiconductor device according to claim 1, wherein, when forming the metal wiring layer, the area to be cut is simultaneously covered with the metal wiring layer. 4. A method for manufacturing a semiconductor device provided with a semiconductor chip having a light receiving element mounted thereon, comprising: a semiconductor wafer having a chip forming region in which the light receiving element is arranged and a region to be cut adjacent to the chip forming region. In the forming step, a method of manufacturing a semiconductor device, comprising substantially preventing an impurity which may form a PN junction in a region to be cut from being introduced into the region to be cut. 5. The method of manufacturing a semiconductor device according to claim 4, wherein, in the step of introducing the impurity, the region to be cut is masked with an impurity introduction blocking layer. 6. A semiconductor wafer having a chip forming region in which light receiving elements are arranged and a planned cutting region adjacent to the chip forming region, wherein the planned cutting region is covered with a light shielding layer that does not substantially transmit light. A semiconductor wafer, which is characterized in that: 7. A semiconductor wafer having a chip forming region in which light receiving elements are arranged and a planned cutting region adjacent to the chip forming region, wherein substantially no PN junction is formed in the planned cutting region. Semiconductor wafer. 8. A semiconductor device having a semiconductor chip on which a light receiving element is mounted, wherein a portion near an end of the semiconductor chip is covered with a light shielding layer that does not substantially transmit light. Semiconductor device.