JPH11234135A - Digital / analog converter - Google Patents

Abstract

(57) [Summary] [Problem] 1 Vpp even when driving a termination resistor of less than 100Ω
And an output current capable of obtaining a voltage of
A current output DA converter having a small circuit area is obtained. A current output type D / A converter is constituted by a D / A conversion unit having a current cell array composed of unit reference current cells and a multiplication unit composed of a multiplication circuit for multiplying the output of the D / A conversion unit. The output of the DA converter is set to be 1 / n of the required DA converter output current Io, and the multiplication circuit is set to be n times as large. [Effect] The unit reference current cell can be reduced in device size to 1 / n of the conventional one, and the power supply and ground lines to that point need not be thickened, and the occupied area can be reduced. By reducing the device size, it is possible to suppress noise by reducing the parasitic capacitance and improve the operation speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current output type digital / analog converter for supplying an analog output current corresponding to digital input data to a built-in or an external terminating resistor. The present invention relates to a digital / analog converter suitable for a high definition display application such as a work station.

[0002]

2. Description of the Related Art Conventionally, a display system circuit such as a high-definition display of this type is required to operate at a high speed. Therefore, a current output type digital / analog converter (Di / A / D converter) using a current cell has been required.
gitalAnalog Converter, hereinafter referred to as a DA converter). In these applications, a resistor of 50Ω or 75Ω is usually used as a terminating resistor. Therefore, in order to generate an output voltage of about 1 Vpp for this terminating resistor, the output current of the DA converter is 20 mA or 13 mA.
A value of A is required. Since the terminating resistance value and the amplitude value of the output voltage are determined by the request from the system,
The output current value of the converter is also automatically determined. For this reason,
These values are not at the disposal of the designer.

The operation of the conventional current output type 8-bit D / A converter shown in FIG. 2 will be described below. The current value Io of the unit current cell is 20 mA ÷ 256 = 78 μ
A. The 8-bit DA converter includes a current cell array 200 provided with 255 unit current cells 201. Here, a general configuration of the unit current cell is shown in FIG. In FIG. 3, reference numeral 301 denotes a transistor for generating an output current Io by a bias voltage supplied from an external bias circuit, and 302 denotes a current switch for selecting whether or not to output a current (normally, a difference between emitter and source common connection). And 303, a drive circuit for driving the current switch by using each row and column decoder output signal.

Returning to FIG. In FIG. 2, Iout is an output current, 203 is a terminating resistor, 204 is a bias voltage generation circuit that generates a predetermined bias voltage from a reference voltage,
Numerals 05 and 208 denote a row decoder and a column decoder, respectively, for driving the unit current cells 201 by the number corresponding to the input data.
It is common to decode the bits to 16. B0
B7 is the input digital data, 207 is the input data B0
This is a latch that holds B7.

The operation is as follows. The 8-bit input data B0 to B7 are decoded from 0 to 255 by the row decoder 205 and the column decoder 208, respectively.
The current switch 3 of each unit current cell is set such that each unit current cell 201 of this number outputs a current value Io.
02 is switched. Therefore, the current cell array 200
, 25,..., 25
5Io and 256 kinds of current including Io as a unit step are obtained. Thereby, digital / analog conversion is performed.

A conventional example of a current output type D / A converter is disclosed in, for example, IEE19.
95 Custom Integrated Circuits Conference, pp. 211-214 (IEEE 1995 CUSTOM INTEGRATED CIRCUITS CONFERENCE,
Digest Technical Papers, pp. 211-214), an 8-bit CMOS D / A converter, or
E-E Transactions on Circuits
And Systems, Vol. 38, No. 3, March 1991, pp. 322 to 325 (IEEE TRANSACTIONS ON C
IRCUITS AND SYSTEMS, VOL.38, NO.3, MARCH 1991, pp.
322-325), a 10-bit CMOS compatible DA converter, and the like.

[0007]

Generally, in order to achieve the accuracy of a current output type D / A converter, it is necessary to secure a current value of a predetermined unit current cell. At the current technical level, in the case of an 8 to 10-bit DA converter, the current of the unit current cell may be about several hundred nA. Therefore, in the conventional example shown in FIG. 2, a value of 78 μA means that a current of 100 times the required amount flows when only the accuracy is considered. If the gate voltage of the MOS transistor is constant, the current value is proportional to the size of the MOS transistor. Therefore, this DA converter should be able to be reduced to 1/100.

However, as described above, the value of the output current Iout of the DA converter is determined by a request from the system. In other words, it can be said that there is a problem that the current needs to be reduced to 1/100 when the device is operated as a DA converter, but the current must be increased according to a request from the system. It is this point that the present invention seeks to solve.

Further, the disadvantages of a large current value are not limited to an increase in device size, but include the following.

(I) It is necessary to provide a thick power supply and a ground wiring corresponding to a large current, which is also a factor of increasing the area. (ii) In a mixed analog / digital LSI, while the miniaturization of the process advances and the logic circuit area is reduced, the analog cannot be reduced as much as the logic circuit, and the occupied area is relatively increased. (iii) The settling time of the DA converter increases. In other words, there is a problem that the area is large in the above (i) and (ii).

Here, the above item (iii) will be supplemented. Larger devices have higher parasitic capacitance. The charge / discharge current for charging / discharging the parasitic capacitance is superimposed on the output current, resulting in noise. This will be described with reference to FIGS. FIG. 4 shows the current switch shown in FIG. 3. In order to easily explain the charge / discharge current, a parasitic capacitance 405 is shown.
And the charge / discharge current 402 flowing therethrough are added. That is, the parasitic capacitance 405 is a capacitance between the drain of the transistor 401 that generates the current Io and the source of the transistor of the current switch 404. 4A and 4B show the gate input nodes of the current switch, and FIG. 4C shows the source node of the current switch connected in common. FIG. 5 shows voltage waveforms at the nodes (a), (b), and (c). The voltage waveform at the node (b) is inverted by the voltage waveform at the node (a) and delayed by an amount corresponding to the voltage via the inverter.

Now, consider a state in which the voltage of the node (a) changes from a high state to a low state. At this time, the voltage of the node (b) changes from a low state to a high state with a slight delay. Therefore, in the period indicated by reference numeral 505 in FIG. 5, both the current switches including the PMOS transistors are on. Conversely, when the voltage at the node (a) transitions from the low state to the high state, a period 504 occurs in which both current switches are turned off. The state where both current switches are on has no effect, but the problem is when both current switches are off.

In this case, the current Io flowing through the transistor 401 has no place to go, and the potential of the node (c) to which the drain terminal is connected rapidly approaches the power supply voltage. At this time, the parasitic capacitance 405 is charged. After a short time, one of the current switches is turned on, so that the potential of the node (c) returns to the original state. At this time, the charge held in the parasitic capacitance 405 becomes a discharge current 402 and flows from the turned-on transistor to the output. This current becomes noise.
Accurately, the waveform overshoots, but the conversion time of the DA converter increases because it is necessary to wait for this settling. Another cause of the discharge current is that the transition from off to on takes longer than the transition from on to off as a characteristic of the transistor, and as a result, a period in which both are off occurs.

Further, the shift of the decode signal arrival time at each unit current cell due to the parasitic capacitance increases, so-called skew occurs. This is also a factor that limits the operation speed. This can be solved by providing a latch in each unit current cell, but this increases the circuit area.

As described above, the DA converter currently used for a high-definition display or the like has a problem that the area is large and the settling time due to noise increases. It is considered that these problems will become more remarkable in the future when the required accuracy of the DA converter is increased from the current 8 bits to 9, 10 bits in such applications. To solve this, the current value may be reduced, but the output current value is determined by a request from the system.

Accordingly, an object of the present invention is to provide a high-definition display or the like in which the terminating resistance is 50Ω or 75Ω.
A digital / digital converter capable of generating an output voltage of 1 Vpp even with a low resistance value of less than 00 Ω and suppressing an increase in circuit area.
An object of the present invention is to provide an analog converter. That is, while satisfying the output current value required by a system such as a high-definition display, the current consumption of the conversion part can be reduced, and the noise generated on the power supply line and the ground line is reduced, so that the settling time is short and the power supply It is an object of the present invention to provide a D / A converter in which the area is reduced by eliminating the need for a wire and a ground wire.

[0017]

In order to solve the above-mentioned problems, a digital / analog converter according to the present invention provides an analog output corresponding to m-bit digital input data to a built-in or external terminating resistor. In a current output type digital / analog converter for supplying a current, a digital / analog which outputs an analog current of 1 / n of a desired output current value of the digital / analog converter based on a result of decoding the digital input data. A conversion section and a multiplication section for multiplying the output current of the digital / analog conversion section by n times are provided, and the output current of the multiplication section is supplied to the terminating resistor.

In this case, the digital / analog conversion unit includes, as shown in FIG. 1, for example, a latch 108 for holding the m-bit (m = 8 bits in FIG. 1) digital input data, and Decoders 106 and 109 for decoding the held digital input data B0 to B7
When, it is preferable if it is constituted by a current cell array 100 consisting of 2 ^m -1 pieces of unit current cells for outputting a current of 2 ^m as based on the decoding result by said decoder.

Alternatively, the digital / analog conversion unit may include a latch for holding the m-bit digital input data, a decoder for decoding the digital input data held in the latch, and 2 ^m patterns based on the decoding result by the decoder. A plurality of sets of reference current cell arrays each including a current cell array composed of 2 ^m -1 unit current cells for outputting currents, for example, three sets of reference current cell arrays 1002 as shown in FIG. Input data selection means 1001 for selecting which set of latches among a plurality of sets of reference current cell arrays to input to, and output selection means for selecting which set of output currents of the plurality of sets of reference current cell arrays to output 1003, and a control signal 1006 for controlling the input selection means and the output selection means. Can be connected constituting more said input selection means and an output current of the selective operation is allowed by the selected said reference current array output selection means to enter into said multiplier circuit.

In addition, the digital / analog conversion unit includes:
As shown in FIG. 8, the m bits (m = 8 in FIG. 8)
And a current cell 801 having a weight corresponding to each bit position of the digital input data held in the latch.
The output current obtained by adding the weighted outputs of the current cells may be connected to the multiplying circuit.

Further, the digital / analog conversion unit is
A latch for holding the m-bit digital input data;
Decoder and a current cell array composed of a 2 ^u -1 pieces of unit current cells for outputting a current of 2 ^u street based on the decoding result by said decoder for decoding the higher u bits of the digital input data held in the latch For example, FIG.
The current cell array 901 for the upper 5 bits as shown in FIG.
And a current cell 90 having a weight corresponding to each of the remaining low-order bits mu bits (8-5 = 3 bits in FIG. 9) of the digital input data held in the latch.
6, the output current of the current cell array and the weighted output of each current cell may be added to the multiplying circuit so as to input the output current.

In the digital / analog converter, the current multiplying circuit is, for example, a current mirror circuit in which the size ratio of input / output transistors is 1: n as shown in FIG. 6, or as shown in FIG. It is preferable that the current mirror circuit be cascaded and configured so that the input / output current ratio becomes 1: n as a whole.

Further, in the above-mentioned digital / analog converter, a dummy current source for supplying the same current as the output current of the digital / analog converter, for example, a dummy reference for supplying the same current as the reference current cell array 1201 as shown in FIG. A current cell array 1202, a first bias voltage Vgs1 of a dummy transistor 1206 connected to the dummy current source, and a second bias voltage of an input section of the multiplying circuit to which an output current of the digital / analog conversion section is connected. Vgs2, and an additional current source 12 that is larger than the output current at the beginning of the transition of the output current of the digital / analog conversion unit by the output of the comparator.
14 or 1211 and the second bias voltage V
Switch circuits 1212 and 1213 that operate to disconnect the additional current source when gs2 exceeds a predetermined reference value.
And a control circuit 1210 for controlling the switch circuit.

In this case, it is preferable that a means for holding the comparison result is further provided at the output of the comparator.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiment of the digital-to-analog converter according to the present invention is a digital-to-analog converter.
It has a circuit configuration including a DA converter that performs A-conversion and a multiplier that multiplies the output of the DA converter to a required size. The output of the unit current cell is regarded as a current having only a magnitude corresponding to the input digital data, and this current is amplified to a required magnitude. That is, the D / A converter is connected to a reference D for generating a minute output current.
It comprises an A converter and a multiplying circuit for amplifying the output current of the reference DA converter.

In a reference DA converter composed of a current cell array composed of unit current cells having a reduced current value, a power supply,
The ground wiring can be made thinner, and the device size can be made smaller accordingly. Therefore, the parasitic capacitance is also reduced, and skew and noise are suppressed. In the DA converter of the present invention, a current multiplication circuit is newly required. However, since this circuit can be constituted by a simple current mirror circuit as described later, the area increase due to the circuit is smaller than the reduced area. Things.

This will be briefly described using the 8-bit DA converter shown in FIG. In FIG. 1, reference numeral 100 denotes a current cell array.
It consists of five unit current cells 101. Unit current cell 10
The current value of 1 is Io / n. Reference numeral 103 denotes an n-times current multiplier, 104 denotes a terminating resistor, 105 denotes a bias voltage generation circuit, 106 denotes a row decoder, B0 to B7 denote input data, 108 denotes a latch, and 109 denotes a column decoder. The reference DA converter includes a current cell array 100, a row decoder 106, a column decoder 109, and a bias voltage generation circuit 105.

The DA converter of the present embodiment thus configured is different from the conventional DA converter in that the unit current cell 1
This is the point that the current value of 01 is as small as 1 / n. Therefore, when the 8-bit data composed of the input data B0 to B7 changes to 0, 1, 2,..., 255, the output current of the current cell array becomes 0, Io / n, 2Io / n,.
It changes to 55 Io / n. The output current of the current cell array 100 is finally multiplied by n using the current multiplying circuit 103, so that the originally required output current value of 0, Io, 2Io,. Current multiplication circuit 103
In the vicinity of, a power line and a ground line having sufficient thickness must be drawn, but unlike a case where a thick wiring is drawn in each of the 255 unit current cells 101, a place where a large current flows is limited. Therefore, only that portion needs to be made thicker, so that the area efficiency is good.

Since each unit current cell 101 has a small current, it does not require a high bias voltage. For this reason,
There is an advantage that suitability for a low power supply voltage, which has been increasing in recent years, is high.

[0030]

Next, a more specific embodiment of the digital / analog converter according to the present invention will be described in detail with reference to the accompanying drawings.

<Embodiment 1> FIG. 1 is a block diagram showing an embodiment of a DA converter according to the present invention, which is a current output type 8-bit DA converter with an external terminating resistor. FIG.
In the configuration of the conventional example shown in FIG. 1, the current value Io of the unit current cell 201 is 20 mA ÷ 256 = 78 μA. Therefore, the current per column of the current cell array 200 is 1.25 mA in total, and 20 mA in 16 columns. Assuming that the output current of the unit current cell is 1/100, that is, n = 100, the unit current cell 101 has only 780 nA, 12.5 μA per column, and 200 μA even in a total of 16 columns. Output current Iout / from current cell array 100
n is input to a current multiplication circuit 103 having a gain of 100. The current multiplying circuit 103 is easily realized by the current mirror circuit 600 shown in FIG. In this cantilever mirror circuit 600, the size ratio between the input transistor 601 and the output transistor 602 may be 1: 100.

The current mirror circuit 600 for obtaining a large current ratio such as 1: 100 has a configuration in which 100 transistors of the same size as the input transistor 601 of the current mirror are provided on the output side. In this configuration, as the magnification increases, the entire area increases, and the original effect of reducing the circuit area decreases. In such a case, the subordinate connection of the current mirror is effective as shown in FIG. Here, a current mirror circuit 701 constituted by an NMOS transistor having an h-times gain and a current mirror circuit 702 constituted by a PMOS transistor having a k-times gain are cascaded to obtain a current gain of h × k times. h = k =
If it is set to 10, the total becomes 100 times, and the circuit area in this case is almost 1/5 of the current multiplication circuit having the configuration shown in FIG. The current mirror circuit 600 shown in FIG.
Since a case is shown in which transistors are used, in this case, the terminating resistor 104 shown in FIG. 1 needs to be connected to a power supply instead of being grounded at one end. When the one end is connected to the grounded terminating resistor 104 as shown in FIG. 1, the current mirror circuit may be configured as a current mirror circuit 702 composed of PMOS transistors in FIG. In this embodiment, the terminating resistor is provided externally, but it is needless to say that the terminating resistor may be built in the chip.

<Embodiment 2> The present invention is not limited to the D / A converter shown in FIG. 1 having a current cell array composed of unit current cells having the same current value. For example, 128I
o: 64Io: 32Io: 16Io: 8Io: 4Io: 2I
o: A D / A converter provided with a current cell having a weight of 2 to the power of 2 (for example, Signor et al., "A Low Power High-
Speed 10-BitCMOS-Compatible D / A Converter ": IEEE
Transactions on circuits and systems, VOL.38, NO.
3, March 1991, the upper 8 bits are configured in this way).

The configuration shown in FIG. 8 is an embodiment applied to a current output type 8-bit D / A converter composed of weighted current cells. Although FIG. 8 shows that the terminating resistor 804 is externally connected to the output terminal 803 of the current multiplying circuit 802, it may be built in. In FIG.
Reference numeral 1 denotes a current cell having a power of 2 weighting, and the magnitude of the current is all 1 / n. The output current from the current cell 801 is converted into a current multiplication circuit 802
To obtain the output current Iout of the DA converter. As a result, the same effect as in the first embodiment can be obtained, and the circuit area and the settling time can be reduced.

In FIG. 8, reference numeral 805 denotes a bias voltage generation circuit that generates a bias voltage to be applied to each weighted current cell from a reference voltage.
B7 indicates 8-bit input data. This input data B
0 to B7 are temporarily held in the latches and connected to the corresponding weighted current cells 801 respectively.

<Embodiment 3> The present invention divides 8 bits of input data into, for example, upper 5 bits and lower 3 bits, and divides the upper 5 bits into a current cell array composed of 31 unit current cells which output 31 equal currents Io. And the lower 3 bits to 4Io:
2Io: DA converter composed of Io weighted current cells (Kohno et al. "A 350-MS / s 3.3V 8-bit CMOS D / A Converter
Using a Delayed Driving Scheme: IEEE 1995 Custom
Integrated Circuits Conference).

FIG. 9 is a block diagram showing one embodiment of such a configuration. In FIG. 9, reference numeral 901 denotes a current cell array including 35 unit current cells for the upper 5 bits, and 906 denotes a weighted current cell for the lower 3 bits. is there. The required output current Iout is obtained by adding the output of the current cell array 901 and the output of the weighted current cell 906 and multiplying the output by n by the current multiplier 902. Also in this embodiment, the same effects as those of the first embodiment can be obtained, and the circuit area and the settling time can be reduced.

In FIG. 9, reference numeral 903 denotes a row decoder, 904 denotes an external terminating resistor, 905 denotes a current cell array 901 and a weighted current cell 9 from a reference voltage.
A bias voltage generation circuit for generating a bias voltage to be applied to 06, 909 is a column decoder, B0 to B7 are 8-bit input data, and the input data B0 to B7 are temporarily held in a latch.

<Embodiment 4> FIG. 10 is a block diagram showing a configuration of another embodiment of a DA converter according to the present invention capable of higher-speed conversion operation. A plurality of sets of current cell arrays are provided and operated sequentially. This is a case where the present invention is applied to a DA converter having a configuration. The present embodiment is characterized in that a plurality of sets of reference current cell arrays and a means for selecting an output current from the reference current cell array are provided.

In FIG. 10, reference numeral 1001 designates a selection means for selecting which reference current cell array to input m-bit input data, and 1002 designates a plurality of reference current cell arrays, the current values of which are terminating resistors. 100
8 is 1 / of the current value necessary to obtain a predetermined voltage by driving
n. Further, each reference current cell array 100
2 includes a current cell array composed of 2 ^m -1 unit current cells as in FIG. 1, a latch, a row decoder and a column decoder. Reference numeral 1003 denotes a selecting means for selecting, from among the outputs of the respective reference current cell arrays 1002, an output which is actually output to the terminating resistor 1008 via the n-times current multiplying circuit 1004. The selecting means 1003 is shown in FIG. It is also possible to use a current switch in the current cell instead. Reference numeral 1005 denotes a bias circuit for generating a bias voltage to be applied to the current cell array in the reference current cell array from the reference voltage. Reference numeral 1006 denotes a control signal for controlling the input / output selecting means 1001 and 1003;
07 is m-bit input data.

The DA converter 1000 configured as described above
Realizes a high-speed operation by operating each reference current cell array 1002 with a slightly shifted phase, and selecting and outputting the output of each reference current cell array by a selection means 1003 at an appropriate timing. For example, the reference current cell array 1002 has three sets of reference current cell arrays a to c as shown in FIG.
Assuming that the frequency is 00 MHz, 300 MHz operation is possible as a whole, ignoring other elements.

This will be described with reference to the timing chart shown in FIG. This figure shows the input digital data 1007 shown in FIG. 10, the input data to each of the reference current cell arrays a to c, their analog outputs, and the DA converter (DA).
C) shows an output waveform. 11, reference numeral 1101 denotes an input data signal, 1102 denotes an input data signal of the reference current cell array a, 1103 denotes an analog output waveform of the reference current cell array a, 1104 denotes an input data signal of the reference current cell array b, and 1105 denotes a reference current cell array. The analog output waveform b, 1106 is the input data signal of the reference current cell array c, 1107 is the output waveform of the reference current cell array c, and 1108 is the output waveform of the DA converter.

The input data signal 1102 of the reference current cell array 1002 is set to 100n as shown in FIG.
It takes seconds. For this reason, 100 MHz is the upper limit of the conversion frequency in the reference current cell array alone. But,
The reference current cell array 1002 is provided with three sets of a, b, and c, and input data D1 at a certain moment is stored in the reference current cell array a.
And input the next input data D2 to the reference current cell array b.
And input data D3 is similarly input to the reference current cell array c. Since the output of the reference current cell array a has been settled so far, the output is selected by the selection means 1003 as the DA converter output. In the next cycle, the output of the reference current cell array b is selected by the selection means 1003 as the DA converter output while the input data D4 is taken into the reference current cell array a again. In this way, each of the reference current cell arrays a, b, and c has a frequency of 100 MHz (1
Although the operation is performed at a period of 00 nsec), a conversion operation of 300 MHz (33 nsec) can be obtained as a whole of the DA converter.

In this embodiment, as in the embodiment of FIG.
An output voltage of 1 Vpp required for display display can be obtained by connecting to a terminating resistor of less than 00Ω, and the output current of the reference current cell array 1002 is reduced to 1 / n, so that the current consumption of the DA converter is reduced. The power supply line and the ground line in the DA converter can be significantly reduced as compared with the conventional example. Therefore, the area occupied by the DA converter on the integrated circuit chip can be reduced. Further, the DA converter according to the present embodiment can realize a higher-speed conversion operation.

<Embodiment 5> FIG.
It is a block diagram showing a schematic structure of another example of a converter. In FIG. 12, reference numeral 1201 denotes digital /
The reference current cell array constituting the analog conversion unit is shown,
The reference current cell array 1201 allows a current 1 / n of a desired output current Iout of the DA converter to flow. Reference numeral 1202 denotes a current source that supplies the same current value Iout / n as that of the reference current cell array 1201, and is hereinafter referred to as a dummy reference current cell array. Reference numeral 1203 denotes an n-times current multiplication circuit that constitutes a multiplication unit. The voltage Vgs between the gate and the source of the MOS transistor 1204 of the current multiplication circuit 1203 is set to Vgs2. In the figure, W is the gate width of the MOS transistor, L
Indicates a gate length. 1206 is a dummy reference current Iout /
The transistor is a transistor that generates a reference gate-source voltage Vgs1 by flowing n, and is hereinafter referred to as a dummy transistor. 1207 is a gate of the current multiplication circuit.
A voltage comparator 1208 for comparing the source-to-source voltage Vgs2 with the reference voltage Vgs1 is means for holding the comparison result of the comparator.
The reason why this is necessary will be described later. 1209 is a circuit for determining the timing of the control circuit, 1210 is a control circuit for selecting pull-up or pull-down from the comparison result,
11 is a pull-down current source, 1212 and 1213 are pull-up / pull-down selection means, and 1214 is a pull-up current source. Although the terminating resistor is not shown in the present embodiment, the terminating resistor may be connected to the output current terminal OUT of the current multiplier 1203 either internally or externally.

The operation of this circuit will be described with reference to FIG. This is a waveform diagram showing voltage and current waveforms of each part of the circuit shown in FIG. In FIG. 13, reference numeral 1301 denotes an output current waveform of the reference current cell array 1201; 1302, a voltage waveform of a gate-source voltage Vgs2 of a MOS transistor constituting the current multiplying circuit 1203 in the case where the speed-up of this embodiment is not performed; Reference numeral 1303 denotes a voltage waveform of the gate-source voltage Vgs1 of the dummy transistor 1206, reference numeral 1304 denotes a voltage waveform of the gate-source voltage Vgs2 of the MOS transistor constituting the current multiplying circuit 1203 in the case where the speed is increased according to the present embodiment, and 1305.
Indicates an output waveform of the voltage comparator 1207, and 1306 indicates a point at which the result of the voltage comparator 1207 is to be held to stop the comparison operation. Reference numeral 1307 denotes an input data waveform of the DA converter.

The output current of the reference current cell array 1201 changes like a waveform 1301 according to the input data 1307. This current Iout / n is used as a current multiplication circuit 1203
Flows through the current mirror MOS transistor 1204, and the change in the current results in a change in the gate-source voltage Vgs2 of the MOS transistor 1204. However, this change is limited by the time constant of the current mirror constituting the current multiplying circuit 1203, and if this time constant is longer than the operation cycle, the change cannot follow as shown by the waveform 1302. On the other hand, a dummy reference current cell array 1202 in which a current value Iout / n equal to that of the reference current cell array flows.
Since the load capacity of the dummy transistor 1206 connected to the dummy transistor 1206 is smaller, it changes at a higher speed as shown by a waveform 1303.

Therefore, in order to change the gate-source voltage Vgs2 of the MOS transistor 1204 in the current multiplying circuit 1203 at high speed in accordance with the change of the gate-source voltage Vgs1 of the transistor 1206, the current is reduced in this embodiment. It is configured to be poured from outside. To be exact,
Gate-source voltage V of MOS transistor 1204
When increasing gs2, the current I_pullup is supplied, and when decreasing gs2, the operation of extracting the current I_pulldown is performed. However, if the charge or discharge is continued as it is, an appropriate voltage will be excessively passed. Therefore, this voltage Vgs2 is compared with the gate-source voltage Vgs1 of the dummy MOS transistor 1206, and the flow of current or the extraction is stopped when they match. This is based on the result of the voltage comparator 1207, the flow selection unit 1213 and the extraction selection unit 121.
2 can be realized. As a result, control is performed such that the gate-source voltage Vgs2 of the current multiplier circuit 1203 always matches the gate-source voltage Vgs1 of the dummy transistor 1206 connected to the dummy reference current cell 1202. The factor that limits the operating speed of the DA converter in this case is the settling time of this control loop if the settling time of the current cell is ignored.

With this circuit, the MOS transistor 120
4 when the gate-source voltage Vgs2 of the dummy transistor 1206 approaches the gate-source voltage Vgs1 of the dummy transistor 1206.
The inversion is repeated when the output of the comparator 1207 is 1 and 0. This change affects the gate-source voltage Vgs2 of the MOS transistor 1204 and causes noise in the output voltage.
08. The most appropriate timing is shown in FIG.
It is considered that this is indicated by reference numeral 306.

The dummy reference current cell array 1202
Need not be exactly the same as the reference current cell array 1201. For example, the dummy reference current cell array 1
Instead of providing 202, reference current cell array 1201
Is temporarily received by a current mirror circuit, the current mirror circuit is configured to have two outputs, one of which is supplied to a current multiplier circuit 1203, and the other is supplied to a dummy transistor 1203.
6 may be configured to be output.

In the configuration shown in FIG. 1 of the first embodiment, the mutual conductance gm of the input current Iin side MOS transistor of the current mirror of FIG. 6 or FIG. MOS
The overall operation speed is limited by a time constant determined by the gate capacitance of the transistor. Since the current of the reference current cell array, which is the charging current, is smaller than the gate capacitance of the current multiplying circuit 103 serving as the load of the reference current cell array, the time constant is large and the operation speed is slow. On the other hand, if the DA converter is configured as shown in the present embodiment, it is possible to improve the operation speed by solving the delay caused by the time constant. In the configuration of the present embodiment, since a circuit for detecting the operation state and quickly pulling up or pulling down the gate potential of the current multiplying circuit 1203 is added, in addition to the current from the current multiplying circuit at the time of transition, charging is performed. Alternatively, a change in the gate-source voltage Vgs2 can be hastened by flowing or extracting a current for discharging.

<Embodiment 6> FIG. 14 has the same configuration as that of the DA converter of Embodiment 5 described with reference to FIG. 12, but a pull-down / pull-up selecting means for selecting pull-up and pull-down from the comparison result. Is an embodiment comprising an inverter and a MOS transistor pair. 14, reference numeral 1401 denotes a reference current cell array, 1402 denotes a dummy reference current cell array, 1403 denotes a current multiplier, 140
4 is a dummy transistor, 1405 is a current source for pull-out (pull-down), 1406 is flow-in / pull-out selection means composed of a current switch of an inverter and a MOS transistor pair, 1407 is a voltage comparator, and 1408 is a current source for flow-in (pull-up). , And 1409 are latches for holding comparison results.

The operation of this circuit will be described with reference to FIG. The reference current cell array 1401 has a waveform 1301
Let's say that it has changed. At this time, the current multiplication circuit 14
The voltage Vgs2 between the gate and the source of the MOS transistor composing 03 does not rise as rapidly as the waveform 1302 as it is. On the other hand, the dummy transistor 140
4, the gate-source voltage Vgs1 changes at a high speed as shown by a waveform 1303. Therefore, the reference current cell array 140
When the current of 1 increases, Vgs1> Vgs2, and the result of the comparator 1407 becomes 1. As a result, in the flow-in / pull-out selection means 1406, not only the current Iout / n of the reference current cell array 1401 but also the current I_pullup of the pull-up current source 1408 is used as the current multiplication circuit 1403.
Is poured into.

The current I_pul of the pull-down current source 1405
ldown is N in the flow / pull-out selection means 1406
With a switch composed of a pair of MOS transistors,
It starts flowing from the power supply. In this state, the current multiplication circuit 1
When the voltage Vgs2 between the gate and the source of the MOS transistor constituting 403 rises and Vgs1 <Vgs2, the output of the comparator 1407 becomes 0. At this time, the selection means 140
Reference numeral 6 controls the flow of the current of the reference current cell array 1401 and the reduction of the gate-source voltage Vgs2 of the MOS transistor constituting the current multiplying circuit 1403, which is excessively increased by the pull-down current source 1405. Then, when the voltage Vgs2 is directly lowered, the output of the comparator 1407 is inverted again. Here, the pull-up current source 1408 and the pull-down current source 1405 are used.
Are all separated and only the reference current cell array 1401 is operated.

At this point, the operation of the circuit for speeding up is completed, and the operation returns to the original DA conversion operation. To disconnect the current source, the pull-up current source 1408 and the pull-down current source 1405 may be stopped collectively, or a current switch for this purpose may be provided. This speeding-up means can be applied to other embodiments.

The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and various design changes can be made without departing from the spirit of the present invention. It is.

[0057]

As is apparent from the above-described embodiments, according to the present invention, in a current output type DA converter, a DA converter composed of a current cell array composed of current cells and the like, And a multiplier that multiplies the output current of the D / A converter to obtain a predetermined output of the D / A converter, so that the current of the D / A converter composed of current cells can be reduced while maintaining the characteristics of the D / A converter. It can be reduced to about 1/100. Accordingly, the device size of the current cell can be reduced, and it is not necessary to make the power supply wiring and the ground wiring of the DA converter thick, and the circuit area can be reduced. In addition, since the device size is reduced, the parasitic capacitance is reduced, thereby suppressing noise and improving the operation speed. Furthermore, the overall chip area can be reduced by reducing the area of the DA converter occupying on the integrated circuit chip, and the manufacturing cost can be reduced.

Therefore, such as a high-definition display, a terminal resistor suitable for applications requiring a low resistance value of less than 100Ω, an analog amplitude voltage of 1 Vpp and high-speed operation is required.
A converter, that is, a D / A converter that can obtain 1 Vpp output even when connected to a display terminating resistor, is high-speed, reduces noise on power supply lines and ground lines, and reduces chip area. Can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a DA converter according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a conventional current cell type DA converter.

FIG. 3 is a circuit diagram illustrating a configuration example of a unit current cell.

FIG. 4 is a circuit diagram in which a parasitic capacitance and its charge / discharge current are added to the unit current cell of FIG. 3;

FIG. 5 is a timing chart of a voltage waveform at each node of the circuit shown in FIG. 4;

FIG. 6 is a circuit diagram showing a configuration example of a current multiplier circuit used in a DA converter according to the present invention.

FIG. 7 is a circuit diagram showing another configuration example of the current multiplier circuit used in the DA converter according to the present invention.

FIG. 8 is a block diagram showing another embodiment of the DA converter according to the present invention.

FIG. 9 is a block diagram showing another embodiment of the DA converter according to the present invention.

FIG. 10 is a block diagram showing still another embodiment of the DA converter according to the present invention.

11 is a timing chart illustrating the operation of the DA converter shown in FIG.

FIG. 12 is a block diagram showing still another embodiment of the DA converter according to the present invention.

13 is a timing chart illustrating the operation of the DA converter shown in FIG.

FIG. 14 is a block diagram showing still another embodiment of the DA converter according to the present invention.

[Explanation of symbols]

100, 200: current cell array, 101, 201: unit current cell, 103, 802: current multiplication circuit, 104,
203, 804 ... terminating resistor, 105, 204, 805 ...
Bias voltage generating circuits, 106, 205... Row decoders,
108, 207 ... data holding latch, 109, 208 ...
Column decoders, 301 and 401 output current Io generating transistors, 302 and 404 current switches, 303 current switch driving circuits, 402 discharge currents from parasitic capacitances,
405: parasitic capacitance; 504: a period when both nodes (a) and (b) are at a high level; 505: a period when both nodes (a) and (b) are at a low level; 601: a multiplying circuit input transistor; Multiplying circuit output transistor, 701... H-times gain current mirror, 702... K-times gain current mirror, 801... Circuit, 904
1008: Terminating resistor, 905, 1005: Bias voltage generation circuit, 906: Weighting current cell for lower bit, 9
08: Upper bit row decoder, 909: Upper bit column decoder, 1000: DA converter, 1001: Input data selection means, 1002: Reference current cell array provided with a plurality of sets, 1003: Output selection means, 1005: Reference current Cell array bias circuit 1006 Control signal for controlling input / output selection means 1007 Input data 110
1: input data waveform, 1102: reference current cell array a
, The input waveform of the reference current cell array b, the input waveform of the reference current cell array b,
1105... Output waveform of reference current cell array b, 1106
... input data of the reference current cell array c, 1107 ... output waveform of the reference current cell array c, 1108 ... output waveform of the DA converter, 1201 ... reference current cell array, 1202 ... a dummy reference current cell array in which the same current value as the reference current cell array flows. 1203: current multiplying circuit, 1204: multiplying circuit MOS transistor, 1206: Transistor (dummy transistor) for generating reference gate-source voltage, 1207, 1407: voltage comparator, 1208 ...
Means for holding a comparator comparison result, 1209 a control circuit timing decision circuit, 1210 a pull-up / down selection control circuit, 1211 a current source for pull-down, 1212,
1213: pull-up / down selection means, 1214: pull-up current source, 1301: output current waveform of the reference current cell array, 1302 ... gate-source voltage waveform of the current multiplying circuit MOS when speeding up is not performed, 1303 ...
Gate-source voltage waveform of dummy transistor, 13
04: voltage waveform between the current multiplication circuit MOS gate and source when the speed is increased, 1305: output waveform of the voltage comparator, 13
06: time when the operation of the comparator should be stopped or the result should be held in the latch; 1307: input data waveform, 1
Reference numeral 401: reference current cell array; 1402: dummy reference current cell array; 1403: current multiplication circuit; 1404: reference gate-source voltage generation transistor;
Current source for extraction, 1406 inflow / extraction selection means constituted by current switches, 1407 voltage comparator,
1408: current source for pouring, 1409: latch for holding comparison result, B0 to B7: input data, Iout / n: current cell array output current, OUT: output current terminal.

Claims (9)

[Claims] 1. An internal or external terminating resistor, m
In a current output type digital / analog converter which supplies an analog output current corresponding to a bit of digital input data, a desired output current value of the digital / analog converter is calculated based on a result of decoding the digital input data. a digital-to-analog converter that outputs n analog currents, and the output current of the digital-to-analog converter is n
A digital-to-analog converter, comprising: a multiplying unit for multiplying the output; and supplying an output current of the multiplying unit to the terminating resistor. 2. The digital / analog converter according to claim 1, wherein
A latch for holding digital input data of bits, a decoder for decoding the digital input data held in the latch, and a decoder for decoding the digital input data based on the decoding result by the decoder.
2. The digital / analog converter according to claim 1, comprising a current cell array composed of 2 ^m -1 unit current cells outputting ^m kinds of currents. 3. The digital / analog conversion unit according to claim 1, wherein
Latch for holding the bits of the digital input data, a decoder for decoding a digital input data held in the latch, with 2 ^m -1 pieces of unit current cells for outputting a current of as 2 ^m based on the decoding result by said decoder A plurality of sets of reference current cell arrays comprising the configured current cell arrays; input data selecting means for selecting which set of latches among the plurality of sets of reference current cell arrays to input digital input data; and Output selecting means for selecting which set of output currents of the reference current cell array to output, and a control signal for controlling the input selecting means and the output selecting means, wherein the input selecting means and the output selecting means are controlled by the control signals. Are selectively operated to input an output current of the selected reference current cell array to the multiplier circuit. According to claim 1 comprising Te digital /
Analog converter. 4. The digital / analog conversion unit according to claim 1, wherein
A latch for holding digital input data of bits, and a current cell having a weight corresponding to each bit position of the digital input data held in the latch, and an output current obtained by adding outputs of the weighted current cells. 2. The input circuit is configured to be input to the multiplying circuit.
2. A digital / analog converter according to claim 1. 5. The digital / analog conversion unit according to claim 1, wherein
A decoder for decoding the latch, the upper u bits of the digital input data held in the latch that holds the bit of the digital input data, 2 ^u -1 pieces for outputting a current of 2 ^u street based on the decoding result by said decoder And a remaining lower bit mu of the digital input data held in the latch.
A current cell having a weight corresponding to each position of a bit, and configured so as to input an output current obtained by adding an output of the current cell array and an output of each of the weighted current cells to the multiplying circuit. The digital-to-analog converter according to claim 1, comprising: 6. The digital / analog converter according to claim 1, wherein said current multiplication circuit comprises a current mirror circuit in which a size ratio of input / output transistors is 1: n. 7. The current multiplying circuit according to claim 1, wherein a current mirror circuit is connected in cascade to form an input / output current ratio of 1: n as a whole.
A digital / analog converter according to the item. 8. A dummy current source for supplying the same current as an output current of the digital / analog conversion unit, and a first one of a dummy transistor connected to the dummy current source.
A comparator for comparing the bias voltage of the digital / analog conversion unit with a second bias voltage of the input unit of the multiplication circuit to which the output current of the digital / analog conversion unit is connected; A switch circuit operable to connect an additional current source larger than the output current at the initial stage of the transition of the output current of the unit and to disconnect the additional current source when the second bias voltage exceeds a predetermined reference value. The digital / analog converter according to any one of claims 1 to 7, further comprising a control circuit for controlling the switch circuit. 9. The digital / analog converter according to claim 8, further comprising means for holding a comparison result at an output of said comparator.