JPH11223569A - Method for manufacturing semiconductor pressure sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the manufacturing of a semiconductor pressure sensor which is capable of implementing reduction in manufacturing cost and is superior in reliability to life and the degree of freedom in element arrangement. SOLUTION: At a region corresponding to a region on an N bulk wafer 12 where a diaphragm 4 is formed, a heavily doped layer 14 is formed in an impurity introducing process, and further an N epitaxial layer 3 is formed in an epitaxial growth process. An impurity is introduced to the N epitaxial layer 3 to form a gauge resistance 6 in a gauge resistance forming process. Wiring films 6a and 11a connected to contacts 6b and 11b are formed in a wiring forming process. A hole part 10 reaching the layer 14 is formed in the N epitaxial layer 3 in a hole part forming process. The layer 14 is selectively removed by etching through the hole part 10 to form a cavity part for a pressure reference chamber 5 and a diaphragm 4 in a sacrifice layer etching process. A pressure reference chamber 5 is formed by sealing the hole part 10 with a sealing film 9 in a sealing process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor pressure sensor in which a diaphragm which is displaced in response to application of pressure is formed by a semiconductor epitaxial layer.

[0002]

2. Description of the Related Art (First Conventional Example)
No. 4350 discloses a method in which a diaphragm formed by epitaxial growth is formed on a single crystal silicon substrate, a gap chamber serving as a pressure reference chamber is formed between the diaphragm and the single crystal silicon substrate, and a gauge resistor is formed in the diaphragm. A described semiconductor pressure sensor is described.
In the semiconductor pressure sensor configured as described above, since the basic structure can be manufactured using only single crystal silicon, better accuracy and sensitivity characteristics can be obtained as compared with the case where the diaphragm is formed of polysilicon. There are advantages.

The above-mentioned publication discloses a technique of manufacturing such a semiconductor pressure sensor by using a SOI wafer and etching a silicon oxide film (insulating isolation film) of the sacrificial layer. Specifically, this manufacturing method
After removing the SOI silicon and the silicon oxide film in the SOI wafer in a state where a required portion is left in an island shape, a portion serving as a diaphragm (a region corresponding to the silicon oxide film left in the island shape) is formed on the SOI wafer. ) Is grown. Furthermore, while forming the gauge resistance in the part that will eventually become the diaphragm,
Forming a communication hole from the surface of the SOI wafer to the silicon oxide film, selectively etching the silicon oxide film from the communication hole to form a void space, and thereafter forming a polysilicon film by a low pressure CVD method; Thus, the respective steps of closing the communication hole are sequentially executed.

(Second conventional example) Further, for example,
JP-A-63209 discloses a sensor substrate in which a P-type epitaxial layer finally serving as a cavity region and an N-type epitaxial layer corresponding to a diaphragm thickness are prepared on an N-type silicon substrate. A method of manufacturing a semiconductor sensor is described in which a layer is removed by electrochemical stop etching to form a diaphragm and a cavity, and then the cavity is sealed.

[0005]

In the structure of the first prior art, a semiconductor pressure sensor is manufactured by using an SOI wafer whose substrate cost is relatively high, so that the manufacturing cost increases. is there. In addition, since the epitaxial layer is formed in a state of covering the SOI silicon left in an island shape on the SOI wafer, the thickness of the SOI silicon film is formed between the diaphragm region and the other region because the epitaxial layer is formed. Will occur. For this reason, the withstand voltage in the peripheral portion (step portion) of the diaphragm is reduced, which may cause a reduction in reliability with respect to the life.

Further, the configuration of the second conventional example has the advantage that no step is formed in the peripheral portion of the diaphragm, but requires an epitaxial wafer having a three-layer structure of N / P / N, which further increases the manufacturing cost. There is a problem of soaring. In addition, due to the need to perform electrochemical stop etching, wiring for applying a voltage to the wafer is required, and therefore, the degree of freedom in element arrangement is reduced due to the presence of the wiring. In addition to the above, there has been a problem that the manufacturing cost is increased due to an increase in chip size, a decrease in the number of chips to be removed from a wafer, a decrease in the yield of etching, and the like.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the manufacturing cost and to manufacture a semiconductor pressure sensor excellent in reliability with respect to life and flexibility in element arrangement. It is to provide a way to become.

[0008]

In order to achieve the above object, a method for manufacturing a semiconductor pressure sensor as described in claim 1 can be adopted. According to this method, the high impurity concentration layer is formed in the region corresponding to the diaphragm formation region on the semiconductor wafer in the impurity introduction step, and the high impurity concentration layer is formed in the epitaxial growth step as described above. An epitaxial layer is formed thereon, and in a gauge resistance forming step, an impurity for a gauge resistance is introduced into a position corresponding to the impurity high concentration layer in the epitaxial layer. Further, in the hole forming step, a hole reaching the high impurity concentration layer is formed in the epitaxial layer, and in the sacrificial layer etching step, the impurity high concentration layer is selectively removed by etching through the hole. Accordingly, a cavity and a diaphragm for the pressure reference chamber are formed. Thereafter, in a sealing step, the hole is sealed and the cavity is sealed to form a pressure reference chamber corresponding to the diaphragm.

In manufacturing a semiconductor pressure sensor as described above, it is possible to use an inexpensive substrate material in which an epitaxial layer is grown on a semiconductor wafer.
The manufacturing cost can be reduced as compared with the case of using an SOI substrate or an N / P / N three-layer epitaxial wafer as in the conventional configuration. Further, since the epitaxial layer for the diaphragm can be grown in a flat state, and no step is generated in the peripheral portion of the diaphragm, the breakdown voltage in the peripheral portion does not decrease, and the life is reduced. A semiconductor pressure sensor having excellent reliability can be manufactured. Furthermore, the selective etching of the high impurity concentration layer does not require the use of the conventional electrochemical stop etching, so that a wiring for applying a voltage is not required, and the element arrangement caused by the wiring is not required. This eliminates the possibility of lowering the degree of freedom, and also prevents the chip size from increasing, the number of chips to be obtained from being reduced, the etching yield from lowering, and the like, and the manufacturing cost can be reduced from this aspect as well.

According to the second aspect of the present invention, since the oxide film and the nitride film are formed in this order on the epitaxial layer forming the diaphragm, the oxide film covering the diaphragm absorbs moisture. It becomes suppressed by the film. Therefore, the deformation of the diaphragm in accordance with the moisture absorption of the oxide film is prevented beforehand, and as a result, the operation reliability of the semiconductor pressure sensor is improved.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows a schematic sectional structure of a semiconductor pressure sensor manufactured by the method according to the present embodiment. In FIG. 3, a semiconductor pressure sensor 1 includes a diaphragm 4 formed by an N epitaxial layer 3 on an N-type silicon substrate 2 (corresponding to a support substrate in the present invention), and a hermetic seal between the diaphragm 4 and the silicon substrate 2. It has a basic structure including a pressure reference chamber 5 formed in a state and a gauge resistor 6 formed on the diaphragm 4 by impurity diffusion.

More specifically, on the N epitaxial layer 3 including the diaphragm 4, a silicon oxide film 7 as an insulating protective film and a silicon nitride film 8 which functions to prevent moisture absorption are formed in this order. Further, a sealing film 9 also serving as a surface passivation film is deposited thereon so as to cover portions other than the diaphragm 4 and a bonding pad portion (not shown). 5 has a structure in which the hole 10 used for forming the airtight seal 5 is hermetically sealed.

On the silicon nitride film 8, a wiring film 6a for the gauge resistor 6 is formed.
a is connected to the gauge resistor 6 via a contact 6b provided to penetrate the silicon oxide film 7 and the silicon nitride film 8. The N epitaxial layer 3, which is N ⁺ region 11 for fixing to a high potential state is formed, for this N ⁺ region 11 also, the wiring layer 11a on the silicon nitride film 8, a silicon The connection is made via a contact 11b provided to penetrate the oxide film 7 and the silicon nitride film 8.

Now, FIGS. 1 and 2 schematically show the manufacturing process of the semiconductor pressure sensor 1 configured as described above, which will be described below. First, FIG.
An impurity introduction step as shown in FIG. In this impurity introducing step, first, the impurity concentration is 10 ¹⁴ to 10 ¹⁷
An N bulk wafer 12 (corresponding to a semiconductor wafer in the present invention) having a plane orientation (100) set to about cm ⁻³ is prepared, and a film thickness of 100 to
A thermal oxide film 13 of about 1000 nm is formed. Then N
After removing the thermal oxide film 13 in a region corresponding to the region where the diaphragm 4 is formed on the bulk wafer 12 by etching or the like, boron is diffused to form a high impurity concentration layer 14.

More specifically, after boron ions are implanted, heat treatment is performed in a nitrogen atmosphere at about 800 to 1200 ° C. to form the high impurity concentration layer 14. Since the formation region finally becomes the pressure reference chamber 5, the heat treatment conditions are set so that the diffusion depth of boron is in a predetermined state (for example, 0.5 to 5 μm). Further, the high impurity concentration layer 14
It becomes a P ⁺ buried layer in accordance with the execution of an epitaxial growth step described later.
It is set to be ¹⁸ to 10 ²⁰ cm ^-3 or so.

Next, after the thermal oxide film 13 is entirely removed by etching or polishing means, FIG.
An epitaxial growth step as shown in FIG. In this epitaxial growth step, the N epitaxial layer 3 is grown over the entire area on the N bulk wafer 12. However, since the thickness of the N epitaxial layer 3 becomes the thickness of the diaphragm 4, for example, the N epitaxial layer 3 has a thickness of about 1 to 20 μm. Is controlled so that the film thickness becomes as follows. In this case, since the impurity concentration of the N epitaxial layer 3 depends on the concentration of the N bulk wafer 12, it is about 10 ¹⁴ to 10 ¹⁷ cm ⁻³ .

Next, a gauge resistance forming step as shown in FIG. 1C is performed. In this gauge resistance forming step, first, the silicon oxide film 7 is formed by thermal oxidation over the entire area on the N epitaxial layer 3, and its thickness is set to about 100 to 1000 nm. Thereafter, a resist pattern 15 is formed on the silicon oxide film 7 in a state where the formation region of the gauge resistor 6 is opened, and boron ions are implanted. Next, after the resist pattern 15 is removed, the gauge resistance 6 is formed by performing a heat treatment in a nitrogen atmosphere at about 800 to 1200 ° C. The heat treatment condition at this time is that the diffusion depth is 0.5. ~ 2
It is set to be about μm. The impurity concentration of the gauge resistor 6 is set to, for example, about 10 ¹⁸ to 10 ²⁰ cm ⁻³ .

Next, an N ⁺ region forming step as shown in FIG. 1D is performed. In this N ⁺ region forming step, although not specifically shown, N-type impurities such as phosphorus are spotted at predetermined positions (positions other than the region where the diaphragm 4 is formed) in the N epitaxial layer 3 using a resist pattern. The N ⁺ region 11 is formed by performing ion implantation and performing heat treatment as necessary. In addition, this N ⁺
The impurity concentration of the region 11 is, for example, 10 ¹⁸ to 10 ²⁰ cm.
^-3 is set.

Next, a contact hole forming step as shown in FIG. In this contact hole forming step, first, the silicon nitride film 8 is formed over the entire region on the silicon oxide film 7 by a CVD method or the like, and then the formation of the contacts 6b and 11b in the silicon oxide film 7 and the silicon nitride film 8 is performed. In the region, a group of through holes 16 having a shape corresponding to each of the contacts 6b and 11b is formed.

Next, a wiring forming step as shown in FIG. In this wiring forming step, a conductive material film such as Al, Al—Cu, W or the like is formed on the silicon nitride film 8 in a state where the through holes 16 are buried, and then patterned to form the wiring film 6a, 11a and contacts 6b and 11b are formed.

Next, a hole forming step as shown in FIG. In the hole forming step, for example, dry etching is performed on the stacked body of the silicon nitride film 8, the silicon oxide film 7, and the N epitaxial layer 3 to extend from the surface side of the silicon nitride film 8 to the impurity-rich layer 14. The hole 10 which reaches is formed. The hole 10 has a diameter of about 1 to 10 μm.

Next, a sacrifice layer etching step as shown in FIG. In this sacrificial layer etching step, a hydrofluoric acid-nitric acid based etching solution using acetic acid as a diluting solution, for example, HF: HNO3: CH3 COOH = 1: 3:
By using an etching solution of 8 (volume ratio), the high impurity concentration layer 14 is selectively etched and removed. As a result, a region corresponding to the high impurity concentration layer 14 is hollowed to form the diaphragm 4, and this hollow portion is finally used as the pressure reference chamber 5. The etching rate at this time is about 0.7 to 3 μm / sec.

In this case, in general, in a silicon substrate in which impurities are diffused at a high concentration, a larger number of mobile carriers participate in the oxidation step than in a silicon substrate having a lower impurity concentration. On the contrary, it is known that the etching rate of a silicon substrate having an impurity concentration is reduced. The dependence of the etching rate on the impurity concentration is very large, and HF: HN
In the case of an etching solution of O3: CH3 COOH = 1: 3: 8 (volume ratio), the state is as follows.

That is, this etchant allows the high impurity concentration layer 14 (impurity concentration: 10
The etching rate when etching a high-concentration silicon substrate such as about ¹⁸ to 10 ²⁰ cm ⁻³ ) is about 0.7 to 3 μm / sec as described above.
The etching rate of a silicon substrate having a low impurity concentration of ¹⁷ cm ⁻³ or less (corresponding to the N bulk wafer 12 and the N epitaxial layer 3 in this embodiment) is reduced to 1/150 or less (such an etching rate of The impurity concentration dependency occurs similarly whether the impurity type is N-type or P-type). Therefore, when the high impurity concentration layer 14 is etched in the sacrificial layer etching step,
The N bulk wafer 12 and the N epitaxial layer 3 are hardly etched.

Next, a sealing step as shown in FIG. In this sealing step, a predetermined pressure (for example, 10
The sealing film 9 is formed by depositing a silicon oxide film, a silicon nitride film, a TEOS film, or a composite film thereof in an atmosphere of 0 Pa or less). A pressure reference chamber 5 corresponding to the diaphragm 4 is formed by hermetically sealing. Incidentally, the sealing film 9 finally covers the diaphragm 4 and a portion excluding a region corresponding to a bonding pad portion (not shown).

As described above, the basic structure of the semiconductor pressure sensor 1 is formed. From this state, the semiconductor pressure sensor 1 as shown in FIG. 3 is completed through a dicing process and the like. .

According to the manufacturing method of the present embodiment, N
It is only necessary to use an inexpensive substrate material in which the N epitaxial layer 3 is grown on the bulk wafer 12, so that it is not necessary to use a conventional SOI substrate or an N / P / N three-layer epitaxial wafer. Cost 1
About ２〜 to １ ／. In addition, the N epitaxial layer 3 for the diaphragm 4 can be grown in a flat state, so that there is no step in the peripheral portion of the diaphragm 4 unlike the conventional configuration (Japanese Patent Laid-Open No. 8-274350). Therefore, it is possible to manufacture the semiconductor pressure sensor 1 having excellent reliability with respect to the life without causing a decrease in the withstand voltage in the peripheral portion.

Further, the selective etching of the high impurity concentration layer 14 only requires the use of a hydrofluoric acid-nitric acid etching solution using acetic acid as a diluting solution.
63209), there is no need to use an electrochemical stop etching, so wiring for applying a voltage is not required, and there is no danger that the degree of freedom in element arrangement due to the wiring is reduced. At the same time, an increase in chip size, a decrease in the number of chips to be obtained, a decrease in the yield of etching, and the like do not occur, and the manufacturing cost can be reduced from this aspect as well.

Since the silicon nitride film 8 having a moisture absorption preventing function is formed on the silicon oxide film 7 formed so as to cover the diaphragm 4, the diaphragm is formed by the moisture absorption of the silicon oxide film 7. 4 is no longer deformed. As a result, it is possible to prevent the mechanical characteristics of the diaphragm 4 from changing over time, and to prevent the semiconductor pressure sensor 1 from changing.
Is also improved in operation reliability.

(Other Embodiments) As described above,
The dependence of the etching rate on the impurity concentration in the silicon substrate occurs similarly whether the impurity type is N-type or P-type. Thus, for example, an impurity concentration of bulk wafer (semiconductor wafer) and the epitaxial layer ^{10 1 4}
To 10 ¹⁷ cm ^-3 or so, if the impurity concentration of the high impurity concentration layer and the gauge resistor is set to about ^{10 1} 8 ~10 ²⁰ cm ^-3, bulk wafer, an epitaxial layer, the high impurity concentration layer and gauge resistance It is not necessary that the conductivity type be a combination as in the above-described embodiment. Specifically, the combinations of the conductivity types of the bulk wafer, the epitaxial layer, the high impurity concentration layer, and the gauge resistance can be set as shown in Table 1 below.

[0031]

[Table 1]

In the above embodiment, HF: HNO3: CH3 COOH = 1: 3: 8 for sacrificial layer etching.
Although an etching solution having a (volume ratio) is used, an etching solution having a significantly different etching rate depending on the impurity concentration of the substrate to be etched may have another composition. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing a first half of a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a sectional view schematically showing the latter half of the manufacturing process.

FIG. 3 is a schematic sectional view of a semiconductor pressure sensor.

[Explanation of symbols]

1 is a semiconductor pressure sensor, 2 is an N-type silicon substrate (support substrate), 3 is an N epitaxial layer, 4 is a diaphragm, 5
Is a pressure reference chamber, 6 is a gauge resistance, 7 is a silicon oxide film,
Reference numeral 8 denotes a silicon nitride film, 9 denotes a sealing film, 10 denotes a hole, 12 denotes an N bulk wafer (semiconductor wafer), and 14 denotes a high impurity concentration layer.

Claims (3)

[Claims] 1. A support substrate made of a semiconductor, a diaphragm formed by an epitaxial layer on the support substrate, a pressure reference chamber formed in a sealed state between the diaphragm and the support substrate, and a pressure reference chamber formed on the diaphragm. A method of manufacturing a semiconductor pressure sensor having a gauge resistor, comprising: an impurity introduction step of forming a high impurity concentration layer in a region corresponding to a region where the diaphragm is formed on a semiconductor wafer for the support substrate; An epitaxial growth step of forming the epitaxial layer on a wafer; a gauge resistance forming step of introducing an impurity for the gauge resistance into a position of the epitaxial layer corresponding to the impurity-rich layer; A hole forming step of forming a hole reaching the concentration layer, A sacrificial layer etching step of selectively removing the high-impurity concentration layer by etching through the hole to form a cavity for the pressure reference chamber and the diaphragm, and sealing the hole to form the sacrificial layer. And a sealing step of forming a pressure reference chamber by closing a cavity. 2. The method according to claim 1, wherein a step of forming an oxide film and a nitride film on the epitaxial layer in this order is performed. 3. The semiconductor wafer having an impurity concentration of 1
0 ¹⁷ cm ⁻³ or less, the impurity concentration of the high impurity concentration layer is set to about 10 ¹⁸ cm ⁻³ or more, and acetic acid is used as a diluting solution as an etching solution in the sacrificial layer etching step. 3. A method for manufacturing a semiconductor pressure sensor according to claim 1, wherein a hydrofluoric acid-nitric acid based etching solution is used.