JPH11224896A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the flatness of an insulating film of a semiconductor device embedded in isolation channels differing in depth. SOLUTION: A silicon oxide film 101 and a silicon nitride film 102 are deposited on a silicon substrate 100, and the silicon nitride film 102 is then etched using a photoresist 103 as a mask, an n-type semiconductor region 104 is formed thereafter. A p-type semiconductor region 106 is formed using a photoresist 105 as a mask. A temporary channel 107 is formed by dry etching. After a silicon nitride film has been deposited on the overall surface, the silicon nitride film 108, the silicon oxide film 101, and the silicon substrate 100 are dry-etched using a photoresist 109 as a mask to form a second shallow isolation channel 110 and a first deep isolation channel 111. An insulating film 112 is embedded in the second isolation channel 110 and the first isolation channel 111, and after planarizing it, the silicon nitride film 108 and the silicon oxide film 101 are removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art A conventional technique for forming isolation grooves having two different depths in a semiconductor device will be described below with reference to FIG. FIG. 6 is a process sectional view showing a conventional method for manufacturing a semiconductor device. First, as shown in FIG.
After the silicon oxide film 201 and the silicon nitride film 202 are formed on the substrate 0, patterning is performed using a photoresist 203 except for a region where a shallow isolation groove is to be formed (FIG. 6B). After the film 202 and the silicon oxide film 201, the silicon substrate 200 is etched to a predetermined depth to form the shallow isolation trench 20.
4 is formed (FIG. 6C).

Next, after removing the photoresist 203, the photoresist 2 is removed except for a region where a deep isolation groove is to be formed.
Then, the silicon substrate 200 is etched to a predetermined depth following the silicon nitride film 202 and the silicon oxide film 201 using the photoresist 205 as a mask to form a deep isolation groove 206 (FIG. 6D). (FIG. 6 (e)).

After removing the photoresist 205, the shallow separation groove 204 and the deep separation groove 206 are
07, and planarization is performed by CMP (chemical mechanical polishing) using the silicon nitride film 202 as a stopper film (FIG. 6F).
02 and the silicon oxide film 201 are removed (FIG. 6).
(G)).

Next, an n-type semiconductor region 209 is formed by ion implantation using the photoresist 208 having a pattern in which the n-type semiconductor formation region is opened as a mask.
(H)). After removing the photoresist 208, the photoresist 21 having a pattern in which the p-type semiconductor formation region is opened
P-type semiconductor region 21 by ion implantation using 0 as a mask
1 (FIG. 6 (i)). Then, when the photoresist 210 is removed, an n-type semiconductor region 209 and a p-type semiconductor region 211 separated by a deep isolation groove 206 filled with an insulating film 207 are formed on the surface of the silicon substrate 200, and the p-type semiconductor region The structure is such that a shallow isolation groove 204 filled with an insulating film 207 is formed in 211.
(J)).

In this semiconductor device, two isolation trenches 204 and 206 filled with an insulating film 207 are element isolation regions, and include an n-type semiconductor region 209 and a p-type semiconductor region 211 on both sides of the shallow isolation trench 204. Are active regions, that is, regions for forming elements such as MOS transistors.

[0007]

In recent years, with the miniaturization of semiconductor devices, flattening the surface of the silicon substrate 200 in the manufacturing process has become important in order to reduce the exposure margin required in the photo process. In the step of forming the gate electrode of a MOS transistor, particularly strict control of the processing size is required. Therefore, the step of embedding and flattening the separation grooves 204 and 206 (FIG. 6)
In (f)), improvement in flatness is particularly required. However, as in the above-described conventional case, the insulating films 207 are simultaneously buried in the separation grooves 204 and 206 having a rectangular cross section and different depths.
In the method of flattening, it is difficult to improve flatness, which hinders miniaturization of a semiconductor element.

The present invention has been made in consideration of the above-described conventional problems, and has as its object to provide a semiconductor device capable of improving the flatness of insulating films embedded in isolation trenches having different depths, and a method of manufacturing the same.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a first isolation insulating film for isolating a first conductivity type semiconductor region and a second conductivity type semiconductor region formed on a semiconductor substrate; A second conductive layer formed in at least one of the first conductive type semiconductor region and the second conductive type semiconductor region;
A first isolation insulating film embedded in a first isolation groove having shallow grooves on both sides of a deep groove having a predetermined width; The isolation insulating film has a second depth equal to the depth of the shallow groove of the first isolation groove.
Embedded in the separation groove.

According to this structure, the first isolation insulating film is embedded in the first isolation groove having shallow grooves on both sides of the deep groove having a predetermined width, and the second isolation insulating film is
Since it is buried in the second separation groove having the same depth as the shallow groove portion of the first separation groove, it is difficult to embed and planarize the first and second separation insulating films having different depths. Dependence is small and flatness can be improved.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, the first isolation insulating film is formed of a first insulating film.
Characterized by having a void portion in the deep groove portion of the separation groove. Thereby, the capacitance between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type can be reduced.
In addition, there is no limit on the depth of the deep groove portion of the first isolation groove due to the limit of the embedding of the first isolation insulating film, and the isolation width can be reduced by setting the depth to be deep.

According to a third aspect of the present invention, in the semiconductor device of the second aspect, a ratio of a depth of the first isolation groove to a width of a deep groove portion of the first isolation groove is 3 or more. And With such a setting, a void can be easily provided in the deep groove of the first separation groove.

According to a fourth aspect of the present invention, in the semiconductor device according to the second or third aspect, the width of the deep groove of the first isolation groove is 0.15 μm or less.
With such a setting, a void can be easily provided in the deep groove of the first separation groove. A method of manufacturing a semiconductor device according to claim 5, wherein the first method comprises:
Forming a semiconductor region of a conductivity type and a semiconductor region of a second conductivity type; and forming a temporary groove by etching a semiconductor substrate at a boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type. Forming a photoresist in a predetermined region on the semiconductor substrate, and etching the semiconductor substrate using the photoresist as a mask to form a deep groove formed by drilling a temporary groove and shallow grooves on both sides of the deep groove. Forming a first separation groove having the first separation groove and a second separation groove having the same depth as the shallow groove portion of the first separation groove; and removing the photoresist and forming the first and second separation grooves. Embedding the isolation insulating film and flattening the isolation insulating film.

According to this manufacturing method, after the provisional groove is formed at the boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type, the semiconductor substrate is etched using the photoresist as a mask, and the provisional groove is formed. By forming a first separation groove having a deep groove formed by digging a groove and shallow grooves on both sides of the deep groove, and a second separation groove having the same depth as the shallow groove of the first separation groove. First and second with different depths
In the step of burying the isolation insulating film in the isolation groove and flattening, the pattern dependency is small and the flatness can be improved.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Forming a first conductivity type semiconductor region and a second conductivity type semiconductor region adjacent to each other on a semiconductor substrate; and forming a semiconductor substrate at a boundary between the first conductivity type semiconductor region and the second conductivity type semiconductor region. Forming a high-concentration n-type impurity region by performing ion implantation; forming a photoresist in a predetermined region on the semiconductor substrate; and etching the semiconductor substrate using the photoresist as a mask, thereby forming a high-concentration n-type impurity region. Forming a first separation groove having a deep groove formed by digging a portion, a shallow groove on both sides of the deep groove, and a second separation groove having the same depth as the shallow groove of the first separation groove; And after removing the photoresist, the first and second
Burying the isolation insulating film in the isolation groove, and planarizing the isolation insulating film.

According to this manufacturing method, the high concentration n is formed at the boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type.
After the formation of the impurity region, the semiconductor substrate is etched using the photoresist as a mask, and a first isolation groove having a deep groove formed by digging down the high-concentration n-type impurity region and shallow grooves on both sides of the deep groove. And a second isolation groove having the same depth as the shallow groove portion of the first isolation groove, thereby embedding an isolation insulating film in the first and second isolation grooves having different depths, thereby achieving planarization. In the step to be performed, pattern dependency is small and flatness can be improved.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Forming a first insulating film on a semiconductor substrate, forming a second insulating film thereon; forming a first photoresist in a predetermined region on the second insulating film; Forming a first conductivity type semiconductor region on a semiconductor substrate by introducing impurities using the first photoresist as a mask, and removing a second insulating film on the first conductivity type semiconductor region using the first photoresist as a mask And removing the first photoresist, forming a second photoresist in a predetermined region on the first insulating film, and introducing impurities into the semiconductor substrate using the second photoresist as a mask. Forming a semiconductor region of the second conductivity type; and forming a first region of the boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type using the second photoresist and the second insulating film as a mask. Of insulating film and semiconductor substrate Forming a temporary groove by etching, removing the second photoresist and the second insulating film, and then forming a stopper insulating film on the entire surface, and forming a predetermined region on the stopper insulating film. A third photoresist is formed, and the stopper insulating film, the first insulating film, and the semiconductor substrate are etched using the third photoresist as a mask. Forming a first isolation groove having shallow groove portions on both sides and a second isolation groove having the same depth as the shallow groove portion of the first isolation groove; and, after removing the third photoresist, Embedding an isolation insulating film in the first and second isolation trenches and flattening the isolation insulating film with reference to the stopper insulating film.

According to this manufacturing method, after forming a temporary groove at the boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type, the deep groove formed by digging the temporary groove and the deep groove are formed. By forming a first separation groove having shallow groove portions on both sides and a second separation groove having the same depth as the shallow groove portion of the first separation groove, first and second separation portions having different depths are formed. In the step of burying the insulating film for isolation in the groove and performing planarization, pattern dependency is small and planarity can be improved. Further, the temporary groove which is a deep groove of the first separation groove can be formed by the first groove without adding a new photolithography step.
This can be performed together with the formation of the semiconductor regions of the conductivity type and the second conductivity type, and separation grooves having different depths can be formed at low cost.

In the semiconductor device according to the present invention, a step of forming a first insulating film on a semiconductor substrate and forming a second insulating film thereon, and a step of forming a first insulating film on a predetermined region on the second insulating film. Forming a first photoresist, introducing impurities using the first photoresist as a mask to form a semiconductor region of the first conductivity type on the semiconductor substrate, and using the first photoresist as a mask; Etching the second insulating film on the semiconductor region of about half of its thickness and removing the first photoresist, and then depositing the second photoresist on a predetermined area on the second insulating film. Forming a second conductive type semiconductor region on a semiconductor substrate by introducing impurities using the second photoresist as a mask; and forming a second conductive type semiconductor region on the second conductive type semiconductor region using the second photoresist as a mask. Second insulating film A step of etching and removing the second insulating film at the boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type, and removing the second photoresist; Forming a temporary groove by etching the first insulating film and the semiconductor substrate at the boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type using the second insulating film as a mask; A third photoresist is formed in a predetermined region on the second insulating film, and the second insulating film, the first insulating film, and the semiconductor substrate are temporarily etched by using the third photoresist as a mask. Forming a first separation groove having a deep groove formed by digging a groove, shallow grooves on both sides of the deep groove, and a second separation groove having the same depth as the shallow groove of the first separation groove; And the third photo register After removal of the door, and a step of the first and second isolation trench burying isolation insulating film is planarized isolation insulating film a second insulating film as a reference.

According to this manufacturing method, the same effect as that of claim 7 can be obtained, and the second insulating film is used as the stopper insulating film when the isolation insulating film is planarized. Since there is no need to add a film deposition step of the insulating film for use, cost reduction can be achieved. Also, the first
The temporary groove formed at the boundary between the semiconductor region of the conductivity type and the semiconductor region of the second conductivity type becomes a deep groove portion of the first separation groove and is filled with another insulating film until the separation insulating film is filled. Therefore, even when the width of the deep groove is narrow, the depth of the deep groove can be increased, and the separation withstand voltage between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type can be improved. it can.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
A first insulating film on a semiconductor substrate, a second insulating film on the first insulating film,
Forming a third insulating film thereon; forming a first photoresist in a predetermined region on the third insulating film; introducing the impurity using the first photoresist as a mask; A step of forming a semiconductor region of the first conductivity type, a step of removing the third insulating film over the semiconductor region of the first conductivity type using the first photoresist as a mask, and a step of removing the first photoresist. Forming a second photoresist in a predetermined region on the second insulating film, introducing impurities using the second photoresist as a mask, and forming a second conductivity type semiconductor region in the semiconductor substrate; Etching the second insulating film at the boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type by using the second photoresist and the third insulating film as a mask; Photoresist mask Removing the third insulating film and the first insulating film by etching, and after removing the second photoresist, using the second insulating film as a mask, forming a semiconductor region of the first conductivity type and a second conductivity type. Forming a temporary groove by etching the semiconductor substrate at the boundary with the semiconductor region,
A third photoresist is formed in a predetermined region on the second insulating film, and a second photoresist is formed using the third photoresist as a mask.
Etching the first insulating film, the first insulating film, and the semiconductor substrate to form a first isolation groove having a deep groove formed by drilling a temporary groove and shallow grooves on both sides of the deep groove; Forming a second isolation groove having the same depth as the shallow groove portion, and removing the third photoresist, filling the first and second isolation grooves with an isolation insulating film, and forming a second isolation groove. Flattening the isolation insulating film on the basis of the insulating film.

According to this manufacturing method, the same effect as the seventh aspect is obtained, and the temporary groove formed at the boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type is formed by 1
It becomes a deep groove of the isolation groove and is not buried by another insulating film until the isolation insulating film is buried, so that even if the width of the deep groove is narrow, the depth of the deep groove can be increased, The separation withstand voltage between the semiconductor region of one conductivity type and the semiconductor region of the second conductivity type can be improved. Note that since the second insulating film is used as a stopper insulating film when planarizing the isolation insulating film, it is not necessary to add a new step of depositing a stopper insulating film. Film deposition of the film is required. In addition, since the temporary groove serving as a deep groove of the first isolation groove is formed in a self-aligned manner at the boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type, the temporary groove is formed in the first isolation groove. Deep groove and first
Since there is no need for a mask misalignment margin for forming the semiconductor regions of the conductivity type and the second conductivity type, the separation region can be reduced.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the ninth aspect, when the isolation insulating film is embedded in the first and second isolation trenches, the first isolation is performed. A void is formed in the deep groove. Thereby, the capacitance between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type can be reduced. In addition, there is no longer any limitation on the depth of the deep groove portion of the first isolation groove due to the limit of the embedding of the isolation insulating film, and the isolation width can be reduced by setting it deep.

According to an eleventh aspect of the present invention, in the method of the eighth, ninth or tenth aspect, the second insulating film is a silicon nitride film. As described above, when the isolation insulating film is planarized by using the silicon nitride film as the second insulating film, the second insulating film can be used as the stopper insulating film.

According to a twelfth aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating film on a semiconductor substrate and forming a second insulating film thereon; Forming a first photoresist in a region of the semiconductor substrate and introducing impurities by using the first photoresist as a mask to form a semiconductor region of a first conductivity type on a semiconductor substrate; Removing the second insulating film on the one-conductivity-type semiconductor region; removing the first photoresist; forming a second photoresist on a predetermined region on the first insulating film; Forming a second conductivity type semiconductor region in the semiconductor substrate by introducing impurities using the second photoresist as a mask, and performing ion implantation using the second photoresist and the second insulating film as a mask; Conductive semiconductor region Forming a high-concentration n-type impurity region in the semiconductor substrate at the boundary between the semiconductor region and the second conductivity type semiconductor region, removing the second photoresist and the second insulating film, and then forming a stopper insulating film on the entire surface. Forming a film, forming a third photoresist in a predetermined region on the stopper insulating film, etching the stopper insulating film, the first insulating film, and the semiconductor substrate using the third photoresist as a mask; By doing so, a first isolation groove having a deep groove formed by digging down the high-concentration n-type impurity region and shallow grooves on both sides of the deep groove, and a first isolation groove having the same depth as the shallow groove of the first isolation groove are formed. A step of forming a second isolation groove and, after removing the third photoresist, burying an isolation insulating film in the first and second isolation grooves, and forming the isolation insulating film on the basis of the stopper insulating film; The step of performing planarization And Nde.

According to this manufacturing method, the high concentration n is formed at the boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type.
After the formation of the impurity region, a first isolation groove having a deep groove formed by digging the high-concentration n-type impurity region and shallow grooves on both sides of the deep groove, and the same as the shallow groove of the first isolation groove By forming a second separation groove of a depth,
In the step of burying isolation insulating films in the first and second isolation trenches having different depths and performing flattening, pattern dependency is small and flatness can be improved. In addition, the difference between the etching rate of the high-concentration n-type impurity region and that of the other region is determined between the deep groove portion of the first isolation groove, the shallow groove portion of the first isolation groove, and the second isolation groove. Therefore, the separation grooves having different depths can be formed at low cost.

According to a thirteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the seventh, eighth, ninth, tenth, eleventh, or twelfth aspect, wherein the first photoresist is formed at a predetermined distance from the region where the first photoresist is formed. And forming a second photoresist. As described above, the width of the deep groove portion of the first separation groove can be determined by the predetermined interval between the formation region of the first photoresist and the formation region of the second photoresist.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment; Related to Claims 1, 5, 7, and 13]
FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a silicon oxide film 101 of about 10 nm is formed on a silicon substrate 100.
And a silicon nitride film 102 of about 50 nm are deposited. Next, the p-type semiconductor formation region and the n-type semiconductor
In the case where a first isolation groove 111 (FIG. 1 (j)) filled with an insulating film 112 is provided on the boundary with the type semiconductor formation region, FIG.
As shown in (b), after patterning the photoresist 103 so as to cover the area other than the area where the n-type semiconductor formation region is expanded by a predetermined value (for example, 0.20 μm), the photoresist 103 is used as a mask. Then, the silicon nitride film 102 is etched, and then P (phosphorus) is ion-implanted to form an n-type semiconductor region 104.

Next, as shown in FIG. 1 (c), the photoresist 103 is removed, and the photoresist is formed so as to cover the region where the n-type semiconductor formation region has been reduced by a predetermined value (for example, 0.20 μm). After patterning at 105, B (boron) using photoresist 105 as a mask
Is ion-implanted to form a p-type semiconductor region 106.

Next, as shown in FIG. 1D, using the photoresist 105 and the silicon nitride film 102 as a mask,
The silicon oxide film 101 and the silicon substrate 100 are removed by dry etching to a predetermined depth (for example, 100 nm), and a temporary groove 107 is formed. Next, after removing the photoresist 105 and the silicon nitride film 102 (FIG. 1E), as shown in FIG. 1F, a silicon nitride film 108 of, for example, 100
Deposit about nm. Next, as shown in FIG. 1G, the silicon nitride film 108 is removed by anisotropic dry etching using the photoresist 109 patterned to cover the active region as a mask. Here, for example, 100% over-etching is performed so that the silicon nitride film does not remain on the side wall of the temporary groove 107.

Next, using the photoresist 109 as a mask, the silicon oxide film 101 and the silicon substrate 10
0 is dry-etched to a predetermined depth (for example, 200 nm) to form a shallow second separation groove 110 and a deep first separation groove 111 (FIG. 1H). next,
After the photoresist 109 is removed, the second separation groove 110 and the first separation groove 111 are buried with an insulating film 112 by a well-known method, and planarization is performed by, for example, a chemical mechanical polishing (CMP) method ( After that, the silicon nitride film 108 and the silicon oxide film 101 are removed (FIG. 1 (j)).

By the above-described manufacturing method, a deep groove having a predetermined width (0.40 μm) and a depth of 300 nm and a shallow groove having a depth of 200 nm on both sides thereof are formed at the boundary between the n-type semiconductor region 104 and the p-type semiconductor region 106. And a second isolation groove 110 having a depth of 200 nm in the n-type semiconductor region 104.
A semiconductor device in which the insulating film 112 is buried and flattened in 111 can be manufactured.

Here, the silicon substrate 100 is a semiconductor substrate, the silicon oxide film 101 is a first insulating film, the silicon nitride film 102 is a second insulating film, and the photoresist 10
3, a first photoresist, an n-type semiconductor region 104 is a semiconductor region of the first conductivity type, a photoresist 105 is a second photoresist, a p-type semiconductor region 106 is a semiconductor region of the second conductivity type, and a silicon nitride film 108 Is a stopper insulating film, the photoresist 109 is a third photoresist, and the insulating film 112 is a separating insulating film.

According to the present embodiment, n-type semiconductor region 1
After a temporary groove 107 having a predetermined width is formed at the boundary between the semiconductor substrate 04 and the p-type semiconductor region 106, a first isolation groove having a deep groove formed by digging the temporary groove 107 and shallow grooves on both sides of the deep groove is formed. By forming the second separation groove 110 having the same depth as the shallow groove portion of the first separation groove 111, the insulating film 112 is formed in the separation grooves 110 and 111 having different depths.
In the process of embedding and flattening, pattern dependency is small and flatness can be improved. Also,
The temporary groove 107, which is a deep groove of the first separation groove 111,
It can be formed using a photolithography process for ion implantation of the n-type semiconductor region 104 and the p-type semiconductor region 106 without adding a new photolithography process. Grooves 110 and 111 can be formed.

In this embodiment, when patterning the photoresists 103 and 105, the value for expanding or reducing the n-type semiconductor formation region is set to 0.2.
Although 0 μm is used, this value can be set in a range equal to or more than half the alignment margin value in the photolithography process. [Second Embodiment: Related to Claims 1, 5, 8, 11, and 13] FIG. 2 is a process sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

First, as shown in FIG. 2A, a silicon oxide film 101 of about 10 nm is formed on a silicon substrate 100.
And a silicon nitride film 102 of about 300 nm is deposited. Next, the p-type semiconductor formation region and the n-type semiconductor
In the case where a first isolation groove 111 (FIG. 2 (i)) filled with an insulating film 112 is provided on the boundary with the type semiconductor formation region, FIG.
As shown in (b), after patterning the photoresist 103 so as to cover the area other than the area where the n-type semiconductor formation region is expanded by a predetermined value (for example, 0.10 μm), the photoresist 103 is used as a mask. Then, the silicon nitride film 102 is etched by 150 nm, and then P ions are implanted to form an n-type semiconductor region 104.

Next, as shown in FIG. 2C, the photoresist 103 is removed, and the n-type semiconductor formation region is reduced by a predetermined value (for example, 0.10 μm) so as to cover a region where the n-type semiconductor formation region is reduced. After patterning at 105, B is ion-implanted using the photoresist 105 as a mask to form a p-type semiconductor region 106. Thereafter, the silicon nitride film 102 is removed by 150 nm etching using the photoresist 105 as a mask. I do.

Next, as shown in FIG. 2D, after the photoresist 105 is removed, the silicon substrate 100 is etched to a predetermined depth (for example, 100 nm) using the silicon nitride film 102 as a mask to form a temporary groove. 107 is formed. Next, as shown in FIG. 2E, using the photoresist 109 patterned so as to cover the active region as a mask, the silicon nitride film 102 is removed by dry etching. As shown in FIG. 2F, the silicon substrate 100 is dry-etched to a predetermined depth (for example, 300 nm) to form a shallow second isolation groove 110 and a deep first isolation groove 111.

Next, the photoresist 109 is removed (FIG. 2).
(G)) After that, the second separation groove 1 is formed by a known method.
10 and the first isolation groove 111 are buried with an insulating film 112, and the silicon nitride film 102 is
The planarization is performed by the MP method (FIG. 2 (h)).
The silicon nitride film 102 and the silicon oxide film 101 are removed (FIG. 2 (i)).

According to the above-described manufacturing method, a deep groove having a predetermined width (0.20 μm) and a depth of 400 nm and a shallow groove having a depth of 300 nm on both sides thereof are formed at the boundary between the n-type semiconductor region 104 and the p-type semiconductor region 106. And a second isolation groove 110 having a depth of 300 nm in the n-type semiconductor region 104.
A semiconductor device in which the insulating film 112 is buried and flattened in 111 can be manufactured.

According to the present embodiment, as in the first embodiment, after a temporary groove 107 having a predetermined width is formed at the boundary between the n-type semiconductor region 104 and the p-type semiconductor region 106, the temporary groove 107 is formed. A first separation groove 111 having a deep groove formed by digging a groove and shallow grooves on both sides of the deep groove, and a second separation groove 11 having the same depth as the shallow groove of the first separation groove 111.
0, the separation grooves 11 having different depths are formed.
In the step of burying the insulating film 112 in 0 and 111 and performing planarization, pattern dependency is small and planarity can be improved. Further, the provisional groove 107 which is a deep groove of the first isolation groove 111 can be formed by photolithography for ion implantation of the n-type semiconductor region 104 and the p-type semiconductor region 106 without adding a new photolithography process. The separation grooves 110 and 111 having different depths can be formed at low cost at a low cost. Furthermore, according to the present embodiment, the silicon nitride film 102 is used as a stopper insulating film when the insulating film 112 is planarized by the CMP method, so that a new step of depositing a stopper insulating film must be added. Therefore, the cost can be further reduced. In addition, the temporary groove 107 formed at the boundary between the n-type semiconductor region 104 and the p-type semiconductor region 106 becomes a deep groove of the first isolation groove 111 and the insulating film 11 for isolation.
2 is not buried by another insulating film until it is buried, so that even if the width of the deep groove is as narrow as 0.20 μm or less, the depth of the deep groove can be increased.
The separation withstand voltage between the n-type semiconductor region 104 and the p-type semiconductor region 106 can be improved.

In this embodiment, when patterning the photoresists 103 and 105, the value for expanding and reducing the n-type semiconductor formation region is set to 0.1.
Although 0 μm is used, this value can be set in a range equal to or more than half the alignment margin value in the photolithography process. [Third Embodiment: Related to Claims 1, 5, 9, 11, and 13] FIG. 3 is a process sectional view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

First, as shown in FIG. 3A, a silicon oxide film 101 of about 10 nm is formed on a silicon substrate 100.
A silicon nitride film 102 of about 150 nm;
A silicon oxide film 113 (third insulating film) of about nm is deposited. Next, when a first isolation groove 111 (FIG. 3 (i)) filled with an insulating film 112 is provided on a boundary between a p-type semiconductor formation region and an n-type semiconductor formation region arranged adjacent to each other, FIG. As shown in (b), after patterning the photoresist 103 so as to cover the area other than the area where the n-type semiconductor formation region is expanded by a predetermined value (for example, 0.10 μm), the photoresist 103 is used as a mask. Then, the silicon oxide film 113 is etched, and then P ions are implanted to form the n-type semiconductor region 104.

Next, as shown in FIG. 3C, the photoresist 103 is removed, and the photoresist is formed so as to cover the region where the n-type semiconductor formation region has been reduced by a predetermined value (for example, 0.10 μm). After patterning at 105, B ions are implanted using the photoresist 105 as a mask to form a p-type semiconductor region 106, and then the silicon nitride film 102 is formed using the photoresist 105 and the silicon oxide film 113 as a mask. Etch.
Subsequently, as shown in FIG.
Using silicon mask 5 as a mask, silicon oxide film 113 and silicon oxide film 101 are etched.

Next, as shown in FIG. 3E, after the photoresist 105 is removed, the silicon substrate 100 is etched to a predetermined depth (for example, 200 nm) using the silicon nitride film 102 as a mask to form a temporary groove. 107 is formed. Next, as shown in FIG. 3F, using the photoresist 109 patterned so as to cover the active region as a mask, the silicon nitride film 102 is removed by dry etching. As shown in FIG. 3G, a shallow second isolation groove 110 and a deep first isolation groove 111 are formed by dry-etching the silicon substrate 100 to a predetermined depth (for example, 200 nm).

Next, after the photoresist 109 is removed, the second isolation groove 110 and the first isolation groove 111 are buried with an insulating film 112 by a known method, and the CMP is performed using the silicon nitride film 102 as a stopper film. Then, the silicon nitride film 102 and the silicon oxide film 101 are removed (FIG. 3H).
(I)).

According to the above-described manufacturing method, a deep groove having a predetermined width (0.20 μm) and a depth of 400 nm and a shallow groove having a depth of 200 nm on both sides thereof are formed at the boundary between the n-type semiconductor region 104 and the p-type semiconductor region 106. And a second isolation groove 110 having a depth of 200 nm in the n-type semiconductor region 104.
A semiconductor device in which the insulating film 112 is buried and flattened in 111 can be manufactured.

According to the present embodiment, as in the first embodiment, a temporary groove 107 having a predetermined width is formed at the boundary between the n-type semiconductor region 104 and the p-type semiconductor region 106, and then the temporary groove 107 is formed. A first separation groove 111 having a deep groove formed by digging a groove and shallow grooves on both sides of the deep groove, and a second separation groove 11 having the same depth as the shallow groove of the first separation groove 111.
0, the separation grooves 11 having different depths are formed.
In the step of burying the insulating film 112 in 0 and 111 and performing planarization, pattern dependency is small and planarity can be improved. Further, the provisional groove 107 which is a deep groove of the first isolation groove 111 can be formed by photolithography for ion implantation of the n-type semiconductor region 104 and the p-type semiconductor region 106 without adding a new photolithography process. The separation grooves 110 and 111 having different depths can be formed at low cost at a low cost.

According to the present embodiment, similarly to the second embodiment, the n-type semiconductor region 104 and the p-type semiconductor region 1
Since the provisional groove 107 formed at the boundary with the second groove 06 becomes a deep groove of the first separation groove 111 and is not buried by another insulating film until the insulating film 112 for separation is buried, the deep groove 107 Even when the width is as narrow as 0.20 μm or less, the depth of the deep groove can be increased, and the breakdown voltage between the n-type semiconductor region 104 and the p-type semiconductor region 106 can be improved. The CMP of the insulating film 112
Since the silicon nitride film 102 is used as the stopper insulating film when performing the planarization by the method, it is not necessary to add a new film deposition step of the stopper insulating film, but the silicon oxide film 113 must first be deposited. .

Further, according to the present embodiment, temporary groove 107 which is a deep groove of first isolation groove 111 is formed in a self-aligned manner at the boundary between n-type semiconductor region 104 and p-type semiconductor region 106. Therefore, the deep trench portion of the first isolation trench 111, the n-type semiconductor region 104, and the p-type semiconductor region 106
Since a mask misalignment margin for the formation of a mask is not required, the separation region can be reduced.

According to the present embodiment, the width of the deep groove portion of the first isolation groove 111 is determined by the etching of the silicon nitride film 102 in the step of FIG.
In the step of etching the silicon oxide films 101 and 113 in the step (d), since the silicon oxide film 102 has a sufficient selectivity to the silicon nitride film 102, the dimensional shift is small, and the width of the deep groove of the first isolation groove 111 is controlled. Can be determined sexually.

In this embodiment, when patterning the photoresists 103 and 105, the value for expanding and reducing the n-type semiconductor formation region is set to 0.1.
Although 0 μm is used, this value can be set in a range equal to or more than half the alignment margin value in the photolithography process. [Fourth Embodiment; Related to Claims 1, 6, 12, and 13] FIG. 4 is a process sectional view showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

First, as shown in FIG. 4A, a silicon oxide film 101 of about 10 nm is formed on a silicon substrate 100.
And a silicon nitride film 102 of about 200 nm is deposited. Next, the p-type semiconductor formation region and the n-type semiconductor
In the case where a first isolation groove 111 (FIG. 4 (i)) filled with an insulating film 112 is provided on the boundary with the type semiconductor formation region, FIG.
As shown in (b), after patterning the photoresist 103 so as to cover the area other than the area where the n-type semiconductor formation region is expanded by a predetermined value (for example, 0.10 μm), the photoresist 103 is used as a mask. Then, the silicon nitride film 102 is etched, and then P ions are implanted to form an n-type semiconductor region 104.

Next, as shown in FIG. 4C, the photoresist 103 is removed, and the photoresist is covered so as to cover the region where the n-type semiconductor formation region has been reduced by a predetermined value (for example, 0.10 μm). After patterning at 105, B is ion-implanted using the photoresist 105 as a mask to form a p-type semiconductor region 106.
Subsequently, the photoresist 105 and the silicon nitride film 102
Is used as a mask, As is injected into the silicon substrate 100 by 5 × 1
By ion implantation of about 0 ¹⁵ cm ^-2 , a depth of 10
An n ⁺ -type impurity region 114 of about 0 nm is formed.

Next, as shown in FIG. 4D, after removing the photoresist 105 and the silicon nitride film 102, a silicon nitride film 108 is formed on the entire surface of the silicon substrate 100 as shown in FIG. For example, about 200 nm is deposited.
Next, as shown in FIG. 4F, using the photoresist 109 patterned so as to cover the active region as a mask, the silicon nitride film 108 and the silicon oxide film 101 are used.
And are removed by etching.

Next, as shown in FIG. 4G, the silicon substrate 100 is dry-etched using the silicon nitride film 108 as a mask to form a shallow second isolation groove 110 and a deep first isolation groove 111. . At this time, the second separation groove 1
When 10 is etched so as for example a depth of 300 nm, the etching rate of the n ⁺ -type impurity regions 114 for faster more than twice the etching rate of the silicon substrate 100 other than the portion, the n ⁺ -type impurity regions 114 were present A first isolation groove 111 having a depth of about 350 nm is formed at a lower portion.
Is formed.

Next, the second separation groove 110 and the first separation groove 111 are buried with an insulating film 112 by a well-known method, and planarized by, for example, a chemical mechanical polishing (CMP) method (FIG. 4). (H)) Then, the silicon nitride film 108 and the silicon oxide film 101 are removed (FIG. 4).
(I)). By the above manufacturing method, the n-type semiconductor region 1
04 and a predetermined width (0.
20 μm) and a first isolation groove 111 having a deep groove having a depth of 350 nm and shallow grooves having a depth of 300 nm on both sides thereof.
And a second isolation groove 110 having a depth of 300 nm in the n-type semiconductor region 104, and these isolation grooves 110 and 111 are provided.
A semiconductor device in which the insulating film 112 is embedded and flattened can be manufactured.

According to the present embodiment, n-type semiconductor region 1
After an n ⁺ -type impurity region 114 is formed at the boundary between the semiconductor substrate 104 and the p-type semiconductor region 106, a deep groove having a predetermined width formed by digging the n ⁺ -type impurity region 114 and shallow grooves on both sides of the deep groove are formed. A first separation groove 111 having
Of the second separation groove 1 having the same depth as the shallow groove portion of the separation groove 111 of FIG.
10 to form separation grooves 11 having different depths.
In the step of burying the insulating film 112 in 0 and 111 and performing planarization, pattern dependency is small and planarity can be improved. Further, the difference between the etching rate of the n ⁺ -type impurity region 114 and that of the other region is different between the deep groove portion of the first isolation groove 111, the shallow groove portion of the first isolation groove 111, and the second isolation groove 110. The separation grooves 11 having different depths at low cost because they are formed simultaneously by using
0,111 can be formed.

In this embodiment, when patterning the photoresists 103 and 105, the value for expanding and reducing the n-type semiconductor formation region is set to 0.1.
Although 0 μm is used, this value can be set in a range equal to or more than half the alignment margin value in the photolithography process. [Fifth Embodiment; Claims 1 to 5, 9, 10, 11,
13 is a process sectional view showing a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention.

First, as shown in FIG. 5A, a silicon oxide film 101 of about 10 nm is formed on a silicon substrate 100.
A silicon nitride film 102 of about 150 nm;
A silicon oxide film 113 of about nm is deposited. next,
FIG. 5B shows a case where a first isolation groove 111 (FIG. 5J) filled with an insulating film 112 is provided on a boundary between an adjacent p-type semiconductor formation region and an n-type semiconductor formation region. As shown in the figure, the n-type semiconductor formation region is set to a predetermined value (for example, 0.
After performing patterning with the photoresist 103 so as to cover the area other than the area subjected to the extension processing by only 0.05 μm), the silicon oxide film 113 is
Is etched, and then P ions are implanted to form an n-type semiconductor region 104.

Next, as shown in FIG. 5C, the photoresist 103 is removed, and the n-type semiconductor formation region is reduced by a predetermined value (for example, 0.05 μm) so as to cover the reduced region. After patterning at 105, B ions are implanted using the photoresist 105 as a mask to form a p-type semiconductor region 106, and then the silicon nitride film 102 is formed using the photoresist 105 and the silicon oxide film 113 as a mask. Etch.
Subsequently, as shown in FIG.
Using silicon mask 5 as a mask, silicon oxide film 113 and silicon oxide film 101 are etched.

Next, as shown in FIG. 5E, after the photoresist 105 is removed, the silicon substrate 100 is etched to a predetermined depth (for example, 200 nm) using the silicon nitride film 102 as a mask to form a temporary groove. 107 is formed. Next, as shown in FIG. 5F, using the photoresist 109 patterned so as to cover the active region as a mask, the silicon nitride film 102 is removed by dry etching. 5 (g), the n-type semiconductor region 104 and the p-type semiconductor region 10 are dry-etched to a predetermined depth (for example, 200 nm) of the silicon substrate 100.
6 and a predetermined width (0.10 μm) and a depth of 400 n
a first isolation groove 111 having a deep groove having a depth of 200 m and shallow grooves having a depth of 200 nm on both sides thereof, and an n-type semiconductor region 104.
A second isolation groove 110 having a depth of 200 nm is formed therein.

Next, as shown in FIG.
The TEOS (S
An insulating film 112 composed of an i (OC ₂ H ₅ ) ₄ ) film is deposited. At this time, in the first isolation groove 111, the growth of the TEOS film from the shallow groove on both sides is faster than the growth rate of the TEOS film in the deep groove, so that a void 115 is formed in the deep groove. After that, the silicon nitride film 102
Is used as a stopper film, and planarization is performed by a CMP method (FIG. 5I), and then the silicon nitride film 102 and the silicon oxide film 101 are removed (FIG. 5J).

By the manufacturing method described above, a deep groove having a predetermined width (0.10 μm) and a depth of 400 nm and a shallow groove having a depth of 200 nm on both sides thereof are formed at the boundary between the n-type semiconductor region 104 and the p-type semiconductor region 106. And a second isolation groove 110 having a depth of 200 nm in the n-type semiconductor region 104.
A semiconductor device can be manufactured in which an insulating film 112 is buried and flattened in 111 and a void 115 is formed in a deep groove of the first isolation groove 111.

According to this embodiment, the same effects as in the third embodiment can be obtained. Further, the first separation groove 111
Since the void 115 is formed in the deep groove, the capacitance between the n-type semiconductor region 104 and the p-type semiconductor region 106 can be reduced. Further, the insulating film 112 for isolation is used.
There is no limit on the depth of the deep groove portion of the first separation groove 111 due to the limit of embedding, and the separation width can be reduced by setting it deep.

By setting the ratio (aspect ratio) of the depth of the first separation groove 111 to the width of the deep groove of the first separation groove 111 to be 3 or more, the depth of the first separation groove 111 can be reduced. The gap 115 can be easily formed at the same time.
The width of the deep groove of the first separation groove 111 is set to 0.15 μm.
m, the gap 115 can be easily formed in the deep groove of the first separation groove 111. Further, when the aspect ratio is set to 3 or more, the gap 115 is more easily formed. 115 can be formed.

In this embodiment, when patterning the photoresists 103 and 105, the value for expanding and reducing the n-type semiconductor formation region is set to 0.0.
Although 5 μm is used, this value can be set in a range equal to or more than half the alignment margin value in the photolithography process. In the first to fifth embodiments,
Photoresist 103 formation region and photoresist 10
5, the first separation groove 111 is formed.
It is needless to say that the width of the deep groove can be determined.

In the first to fifth embodiments,
After forming the n-type semiconductor region 104, the p-type semiconductor region 1
06 is formed, but the p-type semiconductor region 106 may be formed first, and then the n-type semiconductor region 104 may be formed. Further, the second separation groove 110 is formed as n
Although it is formed in the type semiconductor region 104, it may be formed in the p-type semiconductor region 106 or may be formed in both the semiconductor regions 104 and 106.

[0070]

As described above, according to the present invention, the shallow groove having a shallow groove on both sides of the deep groove having a predetermined width at the boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type. And forming a second isolation groove having the same depth as the shallow groove of the first isolation groove in at least one of the first conductivity type semiconductor region and the second conductivity type semiconductor region. By forming, when embedding and flattening the isolation insulating film in the first and second isolation trenches having different depths, pattern dependency is small and flatness can be improved.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device of the fourth embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the method for manufacturing the semiconductor device of the fifth embodiment of the present invention.

FIG. 6 is a process sectional view illustrating a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 silicon substrate 101 silicon oxide film 102 silicon nitride film 103 photoresist 104 n-type semiconductor region 105 photoresist 106 p-type semiconductor region 107 temporary groove 108 silicon nitride film 109 photoresist 110 second separation groove 111 first separation groove 112 Insulating film 113 Silicon oxide film 114 N ⁺ type impurity region 115 Void

Claims (13)

[Claims] A first isolation insulating film for separating a first conductivity type semiconductor region and a second conductivity type semiconductor region formed on a semiconductor substrate; a first isolation type insulating film; A second isolation insulating film formed in at least one of the two conductivity type semiconductor regions, wherein the first isolation insulating film has a deep groove having a predetermined width. Embedded in a first isolation groove having shallow grooves on both sides of
The semiconductor device, wherein the second isolation insulating film is embedded in a second isolation groove having the same depth as a shallow groove portion of the first isolation groove. 2. The method according to claim 1, wherein the first isolation insulating film has a gap in a deep groove of the first isolation groove.
13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein a ratio of a depth of said first separation groove to a width of a deep groove portion of said first separation groove is 3 or more. 4. The width of a deep groove of the first separation groove is 0.15.
The semiconductor device according to claim 2, wherein the thickness is not more than μm. 5. A step of forming a first conductivity type semiconductor region and a second conductivity type semiconductor region adjacent to each other on a semiconductor substrate; and forming the first conductivity type semiconductor region and the second conductivity type semiconductor region. Forming a temporary groove by etching the semiconductor substrate at the boundary of; and forming a photoresist in a predetermined region on the semiconductor substrate, and etching the semiconductor substrate using the photoresist as a mask, A first separation groove having a deep groove formed by drilling down the temporary groove, shallow grooves on both sides of the deep groove, and a second separation groove having the same depth as the shallow groove of the first separation groove are formed. And after removing the photoresist, the first and second
Embedding an isolation insulating film in the isolation groove and flattening the isolation insulating film. 6. forming a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type adjacent to each other on a semiconductor substrate; and forming the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type. Forming a high-concentration n-type impurity region by ion-implanting the semiconductor substrate at the boundary of; and forming a photoresist in a predetermined region on the semiconductor substrate, and etching the semiconductor substrate using the photoresist as a mask. By doing so, a first isolation groove having a deep groove formed by digging down the high-concentration n-type impurity region and shallow grooves on both sides of the deep groove, and the same depth as the shallow groove of the first isolation groove Forming a second isolation groove, and after removing the photoresist, the first and second isolation grooves are formed.
Embedding an isolation insulating film in the isolation groove and flattening the isolation insulating film. 7. A first insulating film is formed on a semiconductor substrate,
Forming a second insulating film thereon; forming a first photoresist in a predetermined region on the second insulating film; introducing the impurity using the first photoresist as a mask; Forming a first conductivity type semiconductor region on the substrate; removing the second insulating film on the first conductivity type semiconductor region using the first photoresist as a mask; After removing the photoresist, a second photoresist is formed in a predetermined region on the first insulating film,
Using the second photoresist as a mask to introduce impurities to form a second conductivity type semiconductor region in the semiconductor substrate; and forming the first photoresist using the second photoresist and the second insulating film as a mask. Etching the first insulating film and the semiconductor substrate at the boundary between the semiconductor region of the conductivity type and the semiconductor region of the second conductivity type to form a temporary groove; Forming a stopper insulating film on the entire surface after removing the second insulating film, forming a third photoresist in a predetermined region on the stopper insulating film, and masking the third photoresist. By etching the stopper insulating film, the first insulating film and the semiconductor substrate, a deep groove formed by digging down the temporary groove and shallow grooves on both sides of the deep groove are formed. Forming a first separation groove having a first separation groove and a second separation groove having the same depth as the shallow groove portion of the first separation groove; and, after removing the third photoresist, forming the first and second separation grooves. Embedding an isolation insulating film in the isolation groove and flattening the isolation insulating film with reference to the stopper insulating film. 8. A first insulating film is formed on a semiconductor substrate,
Forming a second insulating film thereon; forming a first photoresist in a predetermined region on the second insulating film; introducing the impurity using the first photoresist as a mask; Forming a semiconductor region of the first conductivity type on the substrate; etching and removing the second insulating film on the semiconductor region of the first conductivity type by about half the thickness thereof using the first photoresist as a mask; Forming a second photoresist in a predetermined region on the second insulating film after removing the first photoresist,
Forming a second conductive type semiconductor region on the semiconductor substrate by introducing impurities using the second photoresist as a mask; and forming a second conductive type semiconductor region on the second conductive type semiconductor region using the second photoresist as a mask. Etching the second insulating film by about half its thickness and etching away the second insulating film at the boundary between the first conductive type semiconductor region and the second conductive type semiconductor region; And after removing the second photoresist, the first insulating film at a boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type using the second insulating film as a mask Forming a temporary groove by etching the semiconductor substrate; forming a third photoresist in a predetermined region on the second insulating film; and using the third photoresist as a mask, Etching the insulating film, the first insulating film, and the semiconductor substrate to form a first isolation groove having a deep groove formed by drilling down the temporary groove and shallow grooves on both sides of the deep groove; Forming a shallow groove portion of the first separation groove and a second separation groove having the same depth; and, after removing the third photoresist, separating insulating films in the first and second separation grooves. And flattening the isolation insulating film with reference to the second insulating film. 9. A step of forming a first insulating film on a semiconductor substrate, a second insulating film thereon, and a third insulating film thereon, and forming a first insulating film on a predetermined region on the third insulating film. Forming a first photoresist, introducing impurities using the first photoresist as a mask to form a semiconductor region of the first conductivity type on the semiconductor substrate, and forming the first photoresist using the first photoresist as a mask; Removing the third insulating film on the one conductivity type semiconductor region; and forming a second photoresist on a predetermined region on the second insulating film after removing the first photoresist. And
Forming a second conductivity type semiconductor region in the semiconductor substrate by introducing impurities using the second photoresist as a mask; and forming the first conductivity type semiconductor region on the semiconductor substrate using the second photoresist and the third insulating film as a mask. Etching the second insulating film at the boundary between the semiconductor region of the conductivity type and the semiconductor region of the second conductivity type; and etching the third insulating film and the second insulating film using the second photoresist as a mask. 1) removing the insulating film by etching, and removing the second photoresist, and forming the first conductive type semiconductor region and the second conductive type semiconductor region using the second insulating film as a mask. Forming a temporary groove by etching the semiconductor substrate at a boundary; forming a third photoresist in a predetermined region on the second insulating film; using the third photoresist as a mask Etching the second insulating film, the first insulating film, and the semiconductor substrate to form a first isolation groove having a deep groove formed by digging down the temporary groove and shallow grooves on both sides of the deep groove. Forming a shallow groove portion of the first separation groove and a second separation groove having the same depth as the first separation groove; and, after removing the third photoresist, separating into the first and second separation grooves. Embedding an insulating film for isolation, and flattening the insulating film for isolation with reference to the second insulating film. 10. The semiconductor according to claim 9, wherein when the isolation insulating film is buried in the first and second isolation trenches, a void is formed in a deep trench of the first isolation trench. Device manufacturing method. 11. The method according to claim 8, wherein the second insulating film is a silicon nitride film. 12. A step of forming a first insulating film on a semiconductor substrate and forming a second insulating film thereon, and forming a first photoresist on a predetermined region on the second insulating film. Forming a first conductive type semiconductor region on the semiconductor substrate by introducing impurities using the first photoresist as a mask; and forming the first conductive type semiconductor region on the first photoresist as a mask. Removing the second insulating film above, and after removing the first photoresist, forming a second photoresist in a predetermined region on the first insulating film;
Forming a second conductivity type semiconductor region in the semiconductor substrate by introducing impurities using the second photoresist as a mask; and performing ion implantation using the second photoresist and the second insulating film as a mask. Forming a high-concentration n-type impurity region in the semiconductor substrate at a boundary between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type; Forming an insulating film for a stopper over the entire surface after removing the insulating film, and forming a third photoresist in a predetermined region on the insulating film for the stopper, and using the third photoresist as a mask. By etching the stopper insulating film, the first insulating film, and the semiconductor substrate, both the deep groove formed by digging down the high-concentration n-type impurity region and the deep groove are formed. Forming a first isolation groove having a shallow groove portion, and a second isolation groove having the same depth as the shallow groove portion of the first isolation groove. After removing the third photoresist, Embedding an isolation insulating film in the first and second isolation trenches and flattening the isolation insulating film based on the stopper insulating film. 13. The semiconductor according to claim 7, wherein the second photoresist is formed at a predetermined distance from a region where the first photoresist is formed. Device manufacturing method.