JPH11212904A - Data transfer system - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce CPU overhead due to a large number of interrupts. A status register (206c) in which whether or not the data transfer has been completed is written when data to be transferred is transferred to an external device that receives stored data at predetermined time intervals. A controller 205 that performs a timer interrupt to the CPU every predetermined time
When the CPU receives an interrupt from the controller 205, the CPU refers to the status register 206c to check the state of the data transfer, thereby notifying the CPU of the elapse of a predetermined time due to the interrupt, and Enables notification of status.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system suitable for transferring data to an external device such as a display device or a network which receives data at predetermined time intervals by a DMA (Direct Memory Access). is there.

[0002]

2. Description of the Related Art Conventionally, when data is transferred to an external device such as a display device or a network which receives data at predetermined time intervals, the data is transferred to a memory such as an HDD (hard disk drive) or a RAM. Data to be prepared is prepared and transferred directly by the CPU, or data is transferred by a DMAC (DMA controller) in order to reduce the processing of the CPU.

In the above-mentioned DMA method, first, a CPU is used.
Specifies the area for performing DMA on the DMAC and sets a flag indicating the start. On the other hand, DMA
C detects that the start flag has been set, and
Initiate MA transfer. When the DMA transfer of the designated data is completed, the DMAC interrupts the CPU and notifies the CPU of the completion. The CPU receives the DMAC interrupt, performs interrupt processing, and knows that the DMA has been completed.

There is also a method in which the CPU refers to its own timer in order for the CPU to detect the timing at which the external device receives data at predetermined time intervals. However, in view of an increase in the load on the CPU, an interrupt from another device is performed. A method of notifying the CPU of the break of the time slot is adopted.

[0005]

However, if a break in the time slot is notified by an interrupt from another device, an interrupt is issued to the CPU in addition to the DMA completion interrupt, and processing corresponding to the interrupt is performed. There has been a problem that it becomes complicated and overhead increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional data transfer system, and has as its object to provide an external device such as a display device or a network which receives data at predetermined time intervals. When performing data transfer, prepare data to be transferred during the above-mentioned predetermined time, that is, in a time slot of the predetermined time, perform data transfer in the next time slot, and notify it with less CPU overhead. It is to provide a data transfer system capable of performing the following.

[0007]

According to a first aspect of the present invention, there is provided a data transfer system comprising: a data storage unit for storing data to be transferred; an external device for receiving the data at predetermined time intervals; A data transfer unit for transferring data between a storage unit and the external device; a CPU for controlling the data transfer; a register in which whether or not the data transfer is completed by the data transfer unit is written; Timer interrupt means for performing a timer interrupt to the CPU every time, and when the CPU receives an interrupt from the timer interrupt means, the CPU refers to the register to check a data transfer state. I do. As a result, an interrupt is made to the CPU every predetermined time at which the external device receives data.
U can confirm the state of data transfer, and can reduce the number of interrupts and the overhead for the CPU.

The data transfer system according to a second aspect of the present invention has a control register for a flag for instructing the start of data transfer, and the CPU sets the flag of the control register as needed. And Thus, the start of data transfer can be controlled by an instruction from the CPU.

According to a third aspect of the present invention, there is provided a data transfer system, comprising: a data storage unit for storing data to be transferred; an external device for receiving the data at predetermined time intervals; A data transfer unit for transferring data between the CPU, a CPU for controlling the data transfer, a register in which whether or not the data transfer is completed by the data transfer unit is written; In addition to performing a timer interrupt,
Timer interrupt means for instructing the data transfer means to start data transfer is provided, and when the CPU receives an interrupt from the timer interrupt means, the CPU refers to the register to check the state of data transfer. And As a result, an interrupt is issued to the CPU every predetermined time at which the external device receives data. At this time, the CPU can check the state of the data transfer, reducing the number of interrupts and reducing overhead for the CPU. ,
There is no need for the CPU to give a data transfer start instruction, and the overhead can be reduced in this respect as well.

According to a fourth aspect of the present invention, there is provided a data transfer system, comprising: a data storage means for storing data to be transferred; an external device receiving the data at predetermined time intervals; A data transfer means for transferring data between the CPU, a CPU for controlling the data transfer, and a start value for writing whether or not the data transfer has been completed by the data transfer means and for giving a data transfer start timing And a timer interrupt means for performing a timer interrupt to the CPU at each predetermined time and instructing the data transfer means to start data transfer based on a start value set in the register. When the CPU receives an interrupt from the timer interrupt means, the CPU refers to the register to change the state of data transfer. Characterized in that it sure. Thus, the data transfer is started based on the start value set in the register, and it is possible to prevent the timing at which the CPU refers to the register from overlapping with the timing of the data transfer.

The data transfer system according to claim 5 of the present invention is provided with an interrupt factor register for setting information indicating that the timer interrupt has been performed from the timer interrupt means.
The PU refers to the interrupt factor register when receiving a timer interrupt from the timer interrupt means. Thus, the CPU that has received the interrupt can know the cause of the interrupt.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data transfer system according to the present invention will be described below with reference to the accompanying drawings. In each drawing, the same components are denoted by the same reference numerals, and redundant description will be omitted. FIG. 1 shows a configuration diagram of the entire system. A storage unit 101, an external I / F (interface) device 102, and other devices 104 are connected via an internal bus 103 to a CPU 100 that integrally controls the system.

The storage unit 101 is a memory such as an HDD or a RAM.
00 and becomes a data transfer source. External I / F
The device 102 is an external device 1 such as a display device or a network that receives data of the storage unit 101 at predetermined time intervals.
05, and constitutes a data transfer destination.

Assuming that the external device 105 needs to receive data every predetermined time (predetermined time slot) T, for example, data a, b, c, d,.
Is performed as shown in FIG. That is,
For each data a, b, c, d,..., In the time slot of each phase (Phase) n-2, the CPU 1
00, the data is stored in the storage unit 101, and data is transferred from the storage unit 101 to the external I / F device 102 in the time slot of each phase (Phase) n-1. (P
hase) n, the external I / F device 10
2 to the external device 105.

FIG. 3 shows the configuration of the external I / F device 102 according to the first embodiment. The internal bus 103 is connected by a bus I / F (interface) unit 201. The bus I / F unit 201 includes a data buffer unit 2
02, a DMA controller 207 and a register 206 are connected. The external I / F device 102 is controlled by the controller 205. Controller 205
Is operating in response to the output of the counter 204 that counts the clock of a clock source having a predetermined frequency, and generates an interrupt to the CPU 100 at the timing of a time slot break.

The DMA controller 207 transmits data stored in the storage unit 101 to the data buffer unit 2.
02 DMA transfer. The data buffer unit 202 has a double buffer configuration, in which data transferred by the DMA controller 207 is written into one buffer, and data is transmitted from the other buffer to the external I / F unit 203. The switching of the data buffer unit 202 is performed by a control signal output from the controller 205 and indicating a time slot break. Also, the timing of reading data from the data buffer unit 202,
Timing of writing data to the external I / F unit 203,
Further, the timing of data transfer from the external I / F unit 203 to the external device 205 is all performed by a command output from the controller 205.

The register 206 includes an interrupt factor register 206a, a control register 206b, and a status register 206c. Interrupt factor register 20
A flag is set in 6a to indicate that the controller 205 has generated an interrupt due to a time slot break. The control register 206b has a CP
The U100 sets the target device identification information of the DMA, the start address and length of the data area, and the flag of the start of the DMA, and is referred to by the DMA controller 207. The status register 206 is managed by the DMA controller 207, and a flag indicating completion of DMA is set.

The operation of the first embodiment configured as described above will be described. Phase for data a (Phas
e) At the end of the n-1 time slot, the controller 205 generates an interrupt to the CPU 100. Then, in response to this, the CPU 100 refers to the interrupt factor register 206a of the register 206 and detects that the interrupt is for notifying a time slot break. Prior to this, the DMA controller 207
The completion of the DMA transfer for the data a is set in the status register 206c. Therefore, the CPU 10
0 refers to the status register 206c following the reference to the interrupt factor register 206a to detect that the DMA transfer for the data a has been completed.

Since the CPU 100 has finished storing the data b in the storage unit 101 in the time slot of the phase (Phase) n-2, following the above operation, the control register 206b of the register 206
The target device identification information (that is, the identification information of the storage unit 101), the start address and length of the area related to the data b, and the DMA start flag are set.

The DMA controller 207 refers to the control register 206b. When the DMA start flag is set as described above, the target device identification information of the DMA set in the control register 206b (that is, the storage unit) DMA transfer is started based on the identification information 101), the start address and the length of the area related to the data b. That is, the time slot of the phase (Phase) n-1 for the data b is entered, and the DMA transfer of the data b is performed by the DMA.
This is performed by the controller 207. At the same time, CPU
100 is the data processing and storage unit 101 in the time slot of phase n-2 for data c.
To the controller 205 for the data a.
External device 1 from external I / F device 102 under the control of
05 is performed. Hereinafter, similarly, the data is sequentially transferred to the external device 105.

FIG. 4 shows the configuration of an external I / F device 102 according to a second embodiment. In this embodiment, the CPU 305 does not give an instruction to start DMA, but the controller 305 gives it directly to the DMA controller 307. That is, the DMA controller 307 is provided with a flag for setting the start of DMA, and the controller 305 is configured to set the start of DMA at a break between time slots. Therefore, the control register 306 of the register 306 is not provided with a flag for setting the start of DMA. Others are the same as the first embodiment.

The operation of the second embodiment configured as described above will be described. Phase for data a (Phas
e) At the end of the n-1 time slot, the controller 305 generates an interrupt to the CPU 100. Then, in response to this, the CPU 100 refers to the interrupt factor register 206a of the register 306, and detects that the interrupt is for notifying a time slot break. Prior to this, the DMA controller 307
The completion of the DMA transfer for the data a is set in the status register 206c. Therefore, the CPU 10
0 refers to the status register 206c following the reference to the interrupt factor register 206a to detect that the DMA transfer for the data a has been completed.

The CPU 100 finishes storing the data b in the storage unit 101 in the time slot of the phase (Phase) n-2, so that the CPU 100 sends the DMA to the control register 306b of the register 306 following the above operation.
The target device identification information (that is, the identification information of the storage unit 101), the start address of the area related to the data b, and the length are set.

When the DMA start flag in the DMA controller 307 is set by the controller 305, the DMA controller 307 identifies the target device identification information of the DMA set in the control register 306b (that is, the DMA controller 307).
The DMA transfer is started based on the identification information of the storage unit 101), the head address of the area related to the data b, and the length. That is, the phase (Phase) n for the data b
-1 time slot, and DMA transfer of data b is D
This is performed by the MA controller 307. At the same time, C
In the time slot of the phase (Phase) n-2 for the data c, the PU 100 performs the data processing and storage 1
01 is stored in the controller 3 for the data a.
Data transfer from the external I / F device 102 to the external device 105 is performed under the control of 05. Hereinafter, similarly, the data is sequentially transferred to the external device 105.

According to the second embodiment, the controller 305 sets the DMA start flag and controls the DMA start timing.
There is no need to control the start timing, and the CPU 100
Can be reduced.

FIG. 5 shows a configuration of an external I / F device 102 according to a third embodiment. In this embodiment, the register 406 is provided with a DMA start value register 406d.
The time until the start (DMA start value) is set.
The DMA start value is initially set by the CPU 100 based on a program in advance, or is initially set by an operator giving a command to the CPU 100 using a keyboard or the like. The controller 405 detects a time slot break based on the output of the counter 204,
It is configured to set DMA start in a flag in the controller 305 based on the output of the counter 204 and the DMA start value. Others are the same as the second embodiment.

The operation of the third embodiment configured as described above will be described. Phase for data a (Phas
e) At the end of the n-1 time slot, the controller 405 generates an interrupt to the CPU 100. Then, in response to this, the CPU 100 refers to the interrupt factor register 206a of the register 406, and detects that the interrupt is for notifying a time slot break. Prior to this, the DMA controller 307
The completion of the DMA transfer for the data a is set in the status register 206c. Therefore, the CPU 10
0 refers to the status register 206c following the reference to the interrupt factor register 206a to detect that the DMA transfer for the data a has been completed.

The CPU 100 finishes storing the data b in the storage unit 101 in the time slot of the phase (Phase) n-2.
The target device identification information (that is, the identification information of the storage unit 101), the start address of the area related to the data b, and the length are set.

The controller 405 detects, based on the DMA start value of the register 406, whether or not a predetermined time (DMA start value) has elapsed from the time slot break.
DMA start flag is set. When the DMA start flag in the DMA controller 307 is set by the controller 405, the DMA controller 307 sets the DMA set in the control register 306b.
DMA transfer is started based on the target device identification information (that is, the identification information of the storage unit 101), the head address of the area related to the data b, and the length. That is, the time slot of the phase (Phase) n-1 for the data b is entered, and the DMA transfer of the data b is performed by the DMA controller 307.
Done by At the same time, in the time slot of phase (Phase) n-2 for the data c,
Data processing and storage in the storage unit 101 are performed, and the data a is transferred from the external I / F device 102 to the external device 105 under the control of the controller 405. Similarly, the data is sequentially transferred to the external device 10.
5 will be transferred.

According to the third embodiment, when a predetermined time (DMA start value) has elapsed from the time slot break based on the DMA start value of the register 406, the DM
Since the DMA start flag in the A controller 307 is set, the start of the DMA can be sent as compared with the second embodiment. Therefore, the CPU 100 sets the register 40 in the time from the reception of the interrupt to the start of the DMA.
6 and the operation can be performed with a margin.

In the first to third embodiments described above, the CPU 100 sets the interrupt factor register 206a
Has been described with reference to the status register 206c with reference to the above, the completion of the DMA transfer has been detected for the data a. However, the fact that the DMA has not been completed has been detected by referring to the interrupt factor register 206a. In this case, the external device 105 cannot receive data in time slot units, and the system is broken. In such a case, the CPU 100 takes predetermined measures such as retrying (transferring again) for an abnormality or sending a command indicating occurrence of a fraud to the external device 105.

[0032]

As described above, according to the data transfer system of the first aspect, the CPU is interrupted every predetermined time when the external device receives data, and at this time, the CPU changes the state of the data transfer. Can be confirmed,
For a CPU, the number of interrupts can be reduced and the overhead can be reduced.

As described above, according to the data transfer system of the second aspect, the flag of the control register for the flag for instructing the start of data transfer can be set by the CPU as needed, so that the Has an effect that the start of data transfer can be controlled by the instruction of (1).

As described above, according to the data transfer system of the third aspect, the CPU is interrupted every predetermined time during which the external device receives data. At this time, the CPU confirms the state of the data transfer. Can, C
For the PU, the number of interrupts can be reduced and the overhead can be reduced. In addition, there is no need for the CPU to give an instruction to start data transfer, and this also has the effect of reducing the overhead.

As described above, according to the data transfer system of the fourth aspect, the data transfer is started based on the start value set in the register, and the timing at which the CPU refers to the register and the timing of the data transfer are determined. Overlap can be prevented, and the CPU can operate with a margin.

As described above, according to the data transfer system of the fifth aspect, since the interrupt factor register for setting the information indicating that the timer interrupt has been performed is provided, the CPU receiving the interrupt is provided. Can know the cause of the interrupt.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a data transfer system.

FIG. 2 is a diagram showing timing of data transfer by the system of the present invention.

FIG. 3 shows an external I constituting the data transfer system of the present invention.
FIG. 1 is a configuration diagram of a first embodiment of a / F device.

FIG. 4 shows an external I constituting the data transfer system of the present invention.
FIG. 2 is a configuration diagram of a second embodiment of the / F device.

FIG. 5 shows an external I constituting the data transfer system of the present invention.
FIG. 7 is a configuration diagram of a third embodiment of the / F device.

[Explanation of symbols]

100 CPU 101 Storage unit 102 External I / F device 103 Internal bus 105 External device 201 Bus I / F
F section 202 Data buffer section 203 External I /
F section 204 counters 205, 305,
405 controller 206, 306, 406 register 206a interrupt cause register 206b, 306b control register 206c status register 207, 307 DMA controller 406d DMA start value register

Claims (5)

[Claims] 1. Data storage means for storing data to be transferred, an external device receiving the data at predetermined time intervals, and a data transfer means for transferring data between the data storage means and the external device. A CPU for controlling the data transfer, a register in which whether or not the data transfer has been completed by the data transfer means, and a timer interrupt means for performing a timer interrupt to the CPU every predetermined time. The data transfer system according to claim 1, wherein when the CPU receives an interrupt from the timer interrupt unit, the CPU refers to the register to check a data transfer state. 2. The data transfer system according to claim 1, further comprising a control register for a flag for instructing start of data transfer, wherein the CPU sets the flag of the control register as needed. 3. Data storage means for storing data to be transferred, an external device for receiving the data at predetermined time intervals, and data transfer means for transferring data between the data storage means and the external device. A CPU for controlling the data transfer; a register in which whether or not the data transfer is completed by the data transfer means; and a timer interrupt for the CPU every predetermined time period; A data transfer system comprising: a timer interrupt unit for instructing a start of data transfer; wherein the CPU, upon receiving an interrupt from the timer interrupt unit, refers to the register to check a data transfer state. . 4. A data storage means for storing data to be transferred, an external device receiving the data at predetermined time intervals, and a data transfer means for transferring data between the data storage means and the external device. A CPU for controlling the data transfer; a register in which whether or not the data transfer has been completed by the data transfer means is written, and a start value for giving a data transfer start timing is set; Timer interrupt means for performing a timer interrupt to the CPU and instructing the data transfer means to start data transfer based on a start value set in the register, wherein the CPU interrupts the timer interrupt means Receiving the data, the data transfer state is checked by referring to the register. . 5. An interrupt factor register for setting information indicating that a timer interrupt has been performed from the timer interrupt means, wherein the CPU, upon receiving a timer interrupt from the timer interrupt means, 5. The data transfer system according to claim 1, wherein the data transfer system refers to an interrupt factor register.