JPH11212870A - Electronic control unit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] In the case of a CPU with a built-in flash memory, the write enable / prohibit control of the flash memory is performed by an external control signal.
Prevent shortage for the original control and delete /
Prevents the writing mode and enhances reliability. SOLUTION: Erasing of a flash memory 4 of a CPU 3 /
A control signal is output from the output port 6 of the CPU 3 to the input port 5 for permitting / prohibiting the writing, and the CPU 3 controls itself. Further, even when the CPU 3 controls a port for permitting / prohibiting erasing / writing of the flash memory by itself, if the CPU 3 falls into an abnormal state such as a runaway, the erasing / writing signal of the input port is set to the prohibited side. An electric circuit may be provided instead of the resistor 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an erasing / writing control of a flash memory in an electronic control unit using a CPU with a built-in flash memory, for example, an electronic control unit for an automobile.

[0002]

2. Description of the Related Art CPUs with built-in flash memory
The contents of the program can be easily electrically and externally erased / written from outside, and the turnaround time from completion of the program to mass production of a control device equipped with the CPU can be shortened. Further, since the ROM is incorporated in the CPU, the circuit scale is reduced, which is suitable for reducing the size of the control device. The CPU with the built-in flash memory is mounted on an electronic control unit for an automobile, and the contents of the flash memory are rewritten on the production line of the control unit or on-board after the vehicle is mounted on an actual vehicle, thereby correcting defects and improving maintainability.

[0003]

However, in order to erase / write the flash memory, an external C
An input signal for switching the electrical signal input to the PU from the prohibition side to the permission side is required.
A trigger signal for transition to the write operation is required. When these signals are input from the connector attached to the control device, several of the connector pins are occupied by the control signals for the erase / write operation, and the number of pins used for the original control function is reduced. However, when most of the connector pins are already occupied only by the control signal, the number of pins is insufficient. Further, since the input of the electric signal for erasing / writing the flash memory is opened to the outside by the connector, there is a possibility that the erasing / writing mode is erroneously set.

The present invention solves such a conventional problem, and provides a highly reliable electronic control device that can effectively use the pins of a connector and prevent an erroneous erase / write mode. The purpose is to do.

[0005]

According to the present invention, in order to achieve the above object, an input port for permitting / prohibiting erasing / writing of a flash memory of a CPU is controlled by outputting a control signal from an output port of the CPU. The configuration is such that the CPU controls itself, and an electronic control device capable of on-board writing can be realized without adding an external control signal.

According to the present invention, an input port for permitting an erasing / writing operation of a flash memory of a CPU is provided with a CP.
When the U performs an abnormal operation, an electric circuit is configured to be forcibly set to the prohibition side by a watchdog timer, and the CPU controls a port for permitting / prohibiting erasing / writing of the flash memory by itself. Even so,
When the CPU falls into an abnormal state such as runaway, the erase / write signal of the input port can be set to the inhibit side.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention according to claim 1 of the present invention has a built-in electrically erasable / writable flash memory, and the erasing / erasing of the flash memory is performed by an electric signal input to an input port from the outside. A CPU having a function of permitting / prohibiting writing; connecting the input port to an output port of the CPU by an electric circuit;
An electronic control unit that, when triggered by a specific signal input to another input port, transitions to an erase / write mode, and uses a control signal output from the output port to permit erasing / writing of the input port. And
This has the effect that an electronic control device capable of on-board writing can be realized without adding an external control signal.

According to a second aspect of the present invention, a CPU
A watchdog timer is connected to the CPU to clear the input port at regular intervals, and when the watchdog timer overflows due to an abnormal operation of the CPU, the signal and the control signal output from the output port erase / clear the input port. 2. The electronic control device according to claim 1, wherein the writing is prohibited, and when the CPU falls into an abnormal state such as runaway, the erasing / writing of the input port can be prohibited.

According to a third aspect of the present invention, a control signal output from an output port and an overflow signal from a watchdog timer are input to an AND circuit, and the output thereof inhibits erasing / writing of the input port. 3. The electronic control device according to claim 2, wherein an erasing / writing operation of the input port can be prohibited when the CPU falls into an abnormal state such as runaway.

According to a fourth aspect of the present invention, a CPU
When a watchdog timer is connected to the CPU and the timer is cleared at regular intervals, and when the watchdog timer overflows due to abnormal operation of the CPU, the signal is used to hold the CPU in a reset state. 2. The electronic control device according to claim 1, wherein erasing / writing is prohibited, and when the CPU falls into an abnormal state such as runaway, erasing / writing of the input port can be prohibited.

According to a fifth aspect of the present invention, in the electronic control device according to any one of the first to fourth aspects, the specific signal input to the other input port is a check signal for a dealer service. This has the effect that a general signal can be used as the specific signal.

According to a sixth aspect of the present invention, in the electronic device according to any one of the first to fourth aspects, the specific signal input to another input port is a command input from a serial communication circuit. This is a control device and has an effect that a general signal can be used as a specific signal. Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 shows an electronic control unit (hereinafter referred to as an ECU) for a vehicle according to a first embodiment of the present invention.
Abbreviated. 3) shows a schematic configuration. In FIG. 1, 1
Denotes an entire ECU, and 2 denotes a connector for connecting the ECU 1 to an external device. Reference numeral 3 denotes a CPU, which has a built-in flash memory 4. Reference numeral 5 denotes an erase / write permission signal input port of the flash memory 4, reference numeral 6 denotes an output port, reference numeral 7 denotes a check signal input port for dealer service, and reference numeral 8 denotes a serial communication input port. The erase / write enable signal input port 5 and output port 6 are connected by a resistor 9 as an electric circuit. The dealer service check signal input port 7 is connected to a dealer service check signal input pin of the connector 2 via the interface circuit 10. The serial communication input port 8 is connected to a serial communication signal pin of the connector 2 via the interface circuit 11.

Next, the operation of the ECU 1 configured as described above will be described. When the check signal input port 7 for the dealer service of the CPU 3 is set to a prescribed logic by a signal from the interface circuit 10, the control transits to the erase / write mode using this as a trigger signal, and the program shown in the flowchart of FIG. . In FIG. 2, the CPU 3 outputs a control signal from the output port 6 in step S1, thereby setting the erase / write permission signal input port 5 for the flash memory 4 to the erase / write permission side, and in step S2, the serial communication input port 8 Then, in step S3, the flash memory 4 is erased and the received data is rewritten. Then, in step S4, this process is repeated until the data rewriting of all areas is completed.

As described above, in the first embodiment, the erase /
Since the check signal output from the interface circuit 10 is used as a dedicated trigger signal for transitioning to the write mode, the trigger signal does not occupy a part of the pins of the connector 2 and the connector 2 is effectively used. Can be. Further, since the electrical signal input for permitting / prohibiting erasing / writing of the flash memory 4 is not opened to the outside by the connector 2, there is no possibility that the erasing / writing mode is erroneously set, and the highly reliable ECU 1 is realized. can do.

(Embodiment 2) FIG. 3 shows a configuration of an ECU according to a second embodiment of the present invention. In FIG. 3, reference numeral 21 denotes the entire ECU, and reference numeral 22 denotes the ECU 2
1 and a connector for connecting the external device. 23 is C
It is a PU and has a built-in flash memory 24. 2
Reference numeral 5 denotes an erase / write permission signal input port of the flash memory 24, 26 denotes an output port, 27 denotes a check signal input port for a dealer service, and 28 denotes a serial communication input port. The check signal input port 27 for dealer service is connected to a check signal input pin for dealer service of the connector 22 via the interface circuit 29. Also, serial communication input port 2
8 is a connector 2 via the interface circuit 30.
2 serial communication signal pins. And C
A watchdog timer 32 is connected to the watchdog timer reset pulse output port 31 provided in the PU 23, and the watchdog timer 32 and the output port 26 are connected.
Are connected to the input side of the AND gate 33, and the output side of the AND gate 33 is connected to the erase / write permission signal input port 25.

Next, the operation of the ECU 21 configured as described above will be described. When the check signal input port 27 for the dealer service of the CPU 23 has a prescribed logic, the transition is made to the erase / write mode using this as a trigger signal, and the program shown in the flowchart of FIG. I do. In FIG. 2, by controlling the output port 26 in step S1, the erasing / writing permission signal input port 25 for the flash memory 24 is set to the erasing / writing permission side.
In step 2, write data is received from the outside via the serial communication input port 28. In step S3, the flash memory 24 is erased and the received data is rewritten. Then, in step S4, this process is repeated until the data rewriting of all areas is completed.

The CPU 21 periodically outputs a watchdog clear pulse from the watchdog timer reset pulse output port 31 in accordance with the flowchart of FIG. That is, a predetermined time is monitored in step S11, and after the predetermined time has elapsed, the watchdog timer 32 is reset in step S12. When the CPU 23 goes into a runaway state, this program does not operate, so that the watchdog timer 32 overflows, and the signal and the control signal from the output port 26 control the AND gate 33 to erase / write the flash memory. The permission signal input port 25 is set to the erase / write inhibit side to prevent the flash memory 24 from being erased by mistake.

As described above, according to the second embodiment, the flash memory erase / write permission signal input port 25
When the CPU 23 runs away, the watch dog timer 33
, The flash memory 24 can be prevented from being erased / written by mistake, and the highly reliable ECU 21 can be realized.

In the second embodiment, when the watchdog timer 33 overflows, the erasing / writing of the input port 25 is set to the prohibition side.
Although the gate 33 is controlled, when the watchdog timer 33 overflows, the CPU 23 is held in a reset state by the signal, and as a result, the input port 25 is set to the erase / write-protection side. You may.

In each of the above embodiments, a trigger signal for transitioning to the erase / write mode is:
Although the check signal for the dealer service is used, a dedicated command input from the serial communication circuit may be used instead.

[0022]

According to the present invention, as is apparent from the first embodiment, an input port for permitting / prohibiting erasing / writing of a flash memory of a CPU is controlled by outputting a control signal from an output port of the CPU. Because it was configured to control itself, without adding an external control signal,
An electronic control device capable of on-board writing can be realized.

According to the present invention, the input port for permitting the erasing / writing operation of the flash memory of the CPU is connected to the CP.
When the U performs an abnormal operation, the electric circuit is configured so as to be forcibly set to the prohibition side by the watchdog timer. Also CP
When U enters an abnormal state such as runaway, the erase / write signal of the input port can be set to the inhibit side.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an automotive electronic control device according to a first embodiment of the present invention;

FIG. 2 is a flowchart showing an operation in the first and second embodiments of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of an electronic control unit for a vehicle according to a second embodiment of the present invention;

FIG. 4 is a flowchart showing an operation according to the second embodiment of the present invention;

[Explanation of symbols]

 1, 21 Automotive electronic control unit (ECU) 2, 22 Connector 3, 23 CPU 4, 24 Flash memory 5, 25 Erase / write enable signal input port 6, 26 Output port 7, 27 Check signal input port 8, 28 Serial Communication input port 9 Resistance (electric circuit) 10, 11, 29, 30 Interface circuit 31 Watchdog timer reset pulse output port 32 Watchdog timer 33 AND circuit

Claims (6)

[Claims] A CPU having a built-in electrically erasable / writable flash memory and having a function of permitting / prohibiting erasing / writing of said flash memory by an electric signal input from an external to an input port; Connecting the input port and the output port of the CPU by an electric circuit,
The CPU transits to the erase / write mode triggered by a specific signal input to another input port, and uses the control signal output from the output port to set the erase / write of the input port to the permission side. Control device. 2. A watchdog timer is connected to a CPU to clear the watchdog timer at regular intervals, and when the watchdog timer overflows due to an abnormal operation of the CPU, a signal from the watchdog timer and a control signal output from the output port are used. 2. The electronic control device according to claim 1, wherein erasing / writing of the input port is set to a prohibition side. 3. A control signal output from an output port and an overflow signal from a watchdog timer are ANDed.
3. The electronic control unit according to claim 2, wherein the input is input to a circuit, and the output of the electronic control unit is set to inhibit erasing / writing of the input port. 4. A watchdog timer is connected to the CPU to clear the CPU at regular intervals, and when the watchdog timer overflows due to an abnormal operation of the CPU, the CPU holds the CPU in a reset state by a signal thereof. 2. The electronic control device according to claim 1, wherein the erasing / writing of the input port is consequently set to the prohibition side. 5. The electronic control device according to claim 1, wherein the specific signal input to another input port is a check signal for a dealer service. 6. The electronic control device according to claim 1, wherein the specific signal input to another input port is a command input from a serial communication circuit.