JPH11212877A - Storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To access only a RAM being the object of partial writing at the time of a partial writing operation and to suppress access to a RAM which is not the object. SOLUTION: A storage device 10 is provided with a RAM control circuit 11 for controlling data writing/reading, a RAM access identification circuit 17 for permitting access to a RAM required at the time of writing data, a RAM 15 constituted of a plurality of storage elements, a check bit generation circuit 14 for generating/adding a check bit guaranteeing data at the time of writing data, a data correction circuit 16 for correcting data which is read or detecting the impossibility of correction, a partial write circuit 12 for generating partially written data for rewriting a part of data in RAM 15 and a selector 13 for selecting partially written data normally rewritten data. Thus, only a RAM being the object of partial writing is accessed and power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device having a plurality of storage elements for storing data accessed from a higher-order processor device, and more particularly to a storage device for performing a partial write operation on a storage element. The present invention relates to a storage device which performs writing of data, suppresses a writing operation to another storage element, and reduces power consumption.

[0002]

2. Description of the Related Art A conventional storage device 20 having a partial write circuit, for example, a "semiconductor storage device" disclosed in JP-A-4-74387, has a RAM control circuit 21 for controlling writing or reading of data as shown in FIG. RAM 25,
A check bit generation circuit 24 that generates a check bit for write data at the time of writing data, a data correction circuit 26 that performs correction or non-correction detection of read data, and data for rewriting a part of data in the RAM 25. A partial write circuit 22 to be generated, and a selector 2 for selecting either partial write data issued from the partial write circuit 22 or normal write data
And 3.

In response to a partial write command from a processor device, first, a RAM control circuit 21 receives a partial write command to a RAM 25 and an address, and sends a chip select signal (hereinafter, a CS signal) and an address to n RAMs. The read operation is performed first, and then the read data is passed through the data correction circuit 26 to the partial write circuit 2.
2, data to be rewritten is generated from the write data and the n-block rewrite information, and is written to the n RAMs 25 via the check bit generation circuit 24. At this time, in the RAM control circuit 21, n RAMs 25
In accordance with the timing at which the data to be rewritten is input, the same address as when the CS signal was read out is output to n RAMs.

[0004]

In the above-described conventional partial write operation, the operation of writing the original data to the RAM other than the RAM to be rewritten is performed in the RAM. Has the disadvantage of increasing.

It is an object of the present invention to provide a RAM composed of n RAMs whose data width can be divided into n equal parts.
It is an object of the present invention to provide a storage device for reducing power consumption by suppressing access to a storage device.

[0006]

A storage device according to a first aspect of the present invention receives a RAM composed of n storage elements, a normal write instruction or a partial write instruction, and an address to be written, and writes the data to the RAM. RA to control
An M control circuit; a data correction circuit that corrects data read from the RAM or detects whether data cannot be corrected;
A partial write circuit for generating partial write data for rewriting a part of data read from the AM, a selector for selecting any of the generated partial write data and normal rewrite data, and a selected write data A check bit generation circuit for generating and adding a check bit for guaranteeing write data at the time of writing, and requesting output to the RAM; and at the time of writing data, permitting access to only the storage element to be written by n-block rewrite information. And a RAM access identification circuit.

In the storage device according to a second aspect of the present invention, in the first aspect, the RAM includes n storage elements capable of dividing a data width of data transmitted and received at a time with a host processor device by n. It is configured.

Further, in a storage device according to a third aspect of the present invention, in the second aspect, the RAM includes a data portion including n storage elements for storing data and a check bit portion including storage elements for storing check bits. It is provided with.

Further, a storage device according to a fourth aspect of the present invention comprises:
In the invention according to the second or third aspect, the RAM control circuit includes a select signal for selecting the normal rewrite data or the partial write data for the selector, and a first signal for accessing the storage element of the data unit to the RAM access identification circuit. , A second chip select signal for accessing the storage element of the check bit section, and an address for accessing the storage element of the data section and the check bit section.

Further, a storage device according to a fifth aspect of the present invention comprises:
In the invention according to the second or third aspect, when the RAM control circuit receives the partial write command, the RAM control circuit issues a select signal for selecting partial write data and a first chip select signal for instructing a read operation of all storage elements in the data section. And issuance.

Further, in the storage device according to a sixth aspect, in the first or third aspect, the n-block rewrite information is:
It is constituted by indicating the storage element of the data section accessed by the normal write command or the partial write command.

Further, according to a seventh aspect of the present invention, in the storage device according to the first or fourth aspect, the RAM access identification circuit comprises:
The notified first chip select signal is used to create a third chip select signal for accessing only the storage element indicated by the n-block rewrite information, and when a write operation output request is notified, the third chip select signal is output. Is issued to the storage element of the data section.

Further, in the storage device according to an eighth aspect of the present invention, in the first aspect, the data correction circuit reads the data read from the RAM when an error can be corrected by a check bit of a check bit portion. When the data is corrected and cannot be corrected, an error notification is performed, and when the data is the partial write command, the read data is notified to the partial write circuit.

Further, in the storage device according to a ninth aspect of the present invention, in the first or seventh aspect, the partial write circuit is configured to read the data, the partial rewrite data, and the n-block rewrite information notified from the data correction circuit. It is configured by generating partial write data.

Further, a storage device according to a tenth aspect of the present invention is the storage device according to the first aspect.
Alternatively, in the invention according to the eighth aspect, the selector is configured to select the partial write data or the normal rewrite data based on the notified select signal, and notify the check bit generation circuit.

Further, the storage device according to the eleventh aspect of the present invention,
In the invention, the check bit generation circuit generates a check bit that guarantees data to be written selected by the selector, issues write data with the check bit added to the RAM, and sends an output request to the RAM access identification circuit. It is configured by notifying.

[0017]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

Referring to FIG. 1, a storage device 10 according to the present embodiment has a RAM for controlling writing and reading of data.
A control circuit 11 and a RAM access identification circuit 1 for permitting access only to a RAM required for writing data
7 and a RAM composed of a plurality of storage elements (RAM)
A check bit generation circuit 14 for generating and adding a check bit for guaranteeing data to the write data at the time of data writing; a data correction circuit 16 for correcting the read data to determine whether or not the data can be corrected;
A partial write circuit 12 for generating data for rewriting a part of the data in the memory, and a selector 13 for selecting either the partial write data issued from the partial write circuit 12 or the normal rewrite data.

The storage device 10 receives a normal write command or a partial write command, an address, normal rewrite data or partial rewrite data, and n-block rewrite information indicating the RAM to be accessed from a higher-level processor device (not shown). Is done.

The RAM 15 has n pieces of R for storing data.
Check bit unit 1 including a data unit 151 having an AM and a RAM storing a check bit for guaranteeing data.
52. The number of RAMs in the data section 151 is n which can divide the data width into n equal parts.

In this embodiment, the data width is 32 bits,
The case where the number of RAMs to be used is 12 when the check bits are 12 bits and the RAM bit width is 4 bits, and the number of RAMs to be used is 8 for the data portion and 3 for the check bit portion will be described in total 11 RAMs.

The n-block rewrite information is information indicating which RAM of the data section 151 is to be rewritten when a normal write instruction or a partial write instruction is issued from the processor device. When "1", it indicates that access is to be performed, and when "0", access is to be suppressed.

The RAM control circuit 11 supplies the selector 13 with a select signal for selecting normal write data or partial write data, and a chip select signal (8) required for the RAM access identification circuit 17 to access the RAM of the data section 151. Bit) and the RAM of the check bit part
Chip select signal (3 bits) required for access
Then, an address is issued to 11 RAMs.

The RAM access identification circuit 17 is a chip that permits access only to the RAM requested to access the RAM of the data section 151 based on the signal received from the RAM control circuit 11 and the 8 bits of the n-block rewrite information. Issues a select signal.

The data correction circuit 16 corrects the data read from the RAM 15 when the error can be corrected by the check bit of the check bit section 152, and notifies the error when the error cannot be corrected. In the case of a partial write command, the read data is transferred to the partial write circuit 1.
Notify 2.

The partial write circuit 12 generates partial write data from the partial rewrite data and n-block rewrite information received from the processor device.

The generated partial write data is selected by the selector 13 by a select signal issued from the RAM control circuit 11, and is notified to the check bit generation circuit 14.

The check bit generation circuit 14 generates a check bit (12 bits) for guaranteeing the data to be written, issues the data with the check bit added to the RAM 15, and requests the RAM access identification circuit 17 to output the data. The issued data is stored in the RAM 1 by the chip select signal issued from the RAM access identification circuit 17.
5 is written.

Next, a description will be given of a partial write operation for reducing the power consumption of the storage device 10.

When the RAM control circuit 11 receives the partial write command signal and the address from the processor unit, it issues a select signal for selecting the partial write data to the selector 13 and then firstly executes the eight RAMs of the data section 151 to perform the read operation. Issue a 8 bit chip select signal to the RAM access identification circuit 17, and issue an address to the 3 bit chip select signal accessible to the 3 RAMs in the check bit section 152 and the 11 RAMs in the RAM 15.

The RAM access identification circuit 17 issues the received chip select signal 8-bit signal to the RAM 15 as a chip select signal. Target RA for partial write
8 bits of n-block rewrite information indicating M are held. The RAM 15 reads the data section 151, and the read data is notified to the partial write circuit 12 via the data correction circuit 16.

The partial write circuit 12 is provided with the partial rewrite data notified from the processor device and the data correction circuit 1.
6- Generate partial write data from the notified data and the n-block rewrite information. The generated partial write data is selected by the selector 13 based on the select signal notified from the RAM control circuit 11, and is input to the check bit generation circuit 14. Check bit generation circuit 1
Reference numeral 4 denotes a RAM 15 which generates 12 bits of check bits for guaranteeing data and is added to the generated partial write data and
And an output request is notified to the RAM access identification circuit 17.

The RAM access identification circuit 17 issues an 8-bit chip select signal for accessing the RAM of the data section 151 from the n-block rewrite information held when the output request is notified, and stores the partial write data in R.
Output to AM15.

In the case of a normal write command, the RAM 1
Since the n-block rewriting information indicating the writing of the data portion 151 of No. 5 to all the RAMs is notified from the processor device, the normal rewriting data is written to all the RAMs of the RAM 15.

As described above, according to the present invention, since the write operation is performed only on the RAM of the RAM to be rewritten, the power consumption can be reduced.

[0037]

As described above, the storage device according to the present invention can be used in a partial write operation in a RAM to be partially written.
This has the effect of reducing power consumption by accessing only the RAM and suppressing access to RAMs other than the target.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of a conventional example.

[Explanation of symbols]

 10, 20 Storage device 11, 21 RAM control circuit 12, 22 Partial write circuit 13, 23 Selector 14, 24 Check bit generation circuit 15, 25 RAM 16, 26 Data correction circuit 17 RAM access identification circuit

Claims (11)

[Claims] A host device receives a normal write command or a partial write command, an address to be written, and normal rewrite data or n-block rewrite information indicating a storage element to be written and accesses a storage element to be written. A RAM composed of n storage elements, a RAM control circuit that receives an address for writing a normal write command or a partial write command and a write address, and controls writing to the RAM; A data correction circuit that corrects the corrected data or detects that the data cannot be corrected, a partial write circuit that generates partial write data for rewriting a part of the data read from the RAM, and the generated partial write data. Normally one of the rewrite data A selector for selecting the selected write data, a check bit generation circuit for generating and adding a check bit for guaranteeing the write data when writing the selected write data, and requesting the output to the RAM; A storage device comprising: a RAM access identification circuit that permits access only to a storage element. 2. The storage device according to claim 1, wherein the RAM includes n storage elements that can divide the data width of data transmitted and received at a time with a host processor device by n. 3. The storage device according to claim 2, wherein the RAM includes a data section including n storage elements for storing data and a check bit section including storage elements for storing check bits. . 4. The RAM control circuit includes: a select signal for selecting normal rewrite data or partial write data for the selector; and a first signal for accessing a storage element of the data unit for the RAM access identification circuit. 2. The semiconductor device according to claim 1, wherein a chip select signal, a second chip select signal for accessing a storage element of the check bit section, and an address for accessing the storage element of the data section and the check bit section are issued. 4. The storage device according to 2, 3 or 4. 5. The RAM control circuit, when receiving the partial write command, issues a select signal for selecting partial write data and issues a first chip select signal for instructing a read operation of all storage elements of the data section. The storage device according to claim 1, 2 or 3, wherein the storage device performs issuance. 6. The storage device according to claim 1, wherein the n-block rewrite information indicates a storage element of the data section accessed by a normal write instruction or a partial write instruction. 7. The RAM access identification circuit creates a third chip select signal for accessing only the storage element indicated by the n-block rewrite information based on the notified first chip select signal, and outputs a write operation output request. 5. The storage device according to claim 1, wherein the third chip select signal is issued to the storage element of the data section when the notification is sent. 8. The data correction circuit corrects the data read from the RAM when an error can be corrected by a check bit in a check bit portion, and issues an error notification when the data cannot be corrected. 2. The storage device according to claim 1, wherein when the write command is issued, the read data is notified to the partial write circuit. 9. The partial write circuit according to claim 1, wherein the partial write circuit generates partial write data from the data notified from the data correction circuit, the partial rewrite data, and the n-block rewrite information. A storage device as described. 10. The storage device according to claim 1, wherein the selector selects the partial write data or normal rewrite data based on the notified select signal and notifies the check bit generation circuit. 11. The check bit generation circuit generates a check bit for guaranteeing data to be written selected by the selector, issues write data with the check bit added to the RAM, and identifies an output request to the RAM access identification. 2. The storage device according to claim 1, wherein the notification is sent to a circuit.