JPH11211432A - Semiconductor device and glass mask - Google Patents

Abstract

(57) Abstract: In verifying the processing accuracy of a semiconductor device at the time of manufacturing the semiconductor device, a dimension is measured with a layout pattern for verifying the processing accuracy close to an actual layout pattern, so that a contact by a miniaturization process or the like is performed. The processing accuracy of the hole data is guaranteed, and high quality can be guaranteed. [Effect] By using a layout pattern for verifying the processing accuracy close to the actual layout pattern, the processing accuracy can be verified in a case where hole data of contacts and the like are densely collected with a single unit. Further, the technology is not limited to the manufacture of semiconductor devices, but can be widely applied to dimensional control in manufacturing a glass mask. Further, by distinguishing the dimension verification of aluminum wiring and POLY data from the dimension verification of hole data such as contacts, it is possible to guarantee the dimension of the processing accuracy of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to means for verifying the processing accuracy of a semiconductor device.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a pattern 200 for verifying the processing accuracy of a conventional semiconductor device.

Conventionally, this layout pattern is arranged in a region (for example, a chip corner portion) different from a region in which logic is actually formed, and a photo process in a semiconductor manufacturing process is performed.
Alternatively, in the etching step, the processing accuracy is verified by measuring the dimensions of the layout pattern, and the quality of the actual layout pattern is assured. For this reason, for example, even in a product such as a gate array in which the layout pattern differs depending on the customer, the processing accuracy can be confirmed by measuring the dimensions of the layout pattern fixed and arranged in advance, and depending on the customer, the processing accuracy can be confirmed. There was no need to specify the measurement location each time.

[0004]

In the layout pattern shown in FIG. 2, the shape of aluminum wiring and POLY data has a shape close to the actual layout pattern.
A correlation can be obtained between the verification of the processing accuracy of the actual layout pattern 200 and the actual layout pattern. However, in the current situation where the fine processing is progressing, the opening data of contacts and the like has become smaller, and it has become impossible to correlate the verification of the processing accuracy between the 200 and the actual layout pattern. For example,
When the hole data of 0.5 μm is controlled by 200, even if the measurement result using 200 is 0.5 μm, the actual size of the layout pattern is 0.3 to 0.3 μm.
There is a risk of becoming 0.4um □. As described above, the difference in layout pattern between the dimension 200 and the actual layout pattern causes a difference in the measurement result of the processing accuracy, and it has become difficult to guarantee sufficient processing accuracy using the 200.

[0005]

Means for Solving the Problems At least the above objects are attained.
In a semiconductor device provided with a mark for processing accuracy verification,
A first mark of the same shape or a second mark in which at least two or more first marks are densely arranged with one of the layout data in which the mark for processing accuracy verification exists in the logical area. This is achieved by being composed of marks.

[0006]

According to the structure of the present invention, a layout pattern for verifying the processing accuracy of a semiconductor device more accurately without being affected by a layout pattern of a customer in an area different from a logic area actually used. Can be realized.

[0007]

FIG. 1 shows a layout pattern for verifying the processing accuracy of a semiconductor device according to the present invention. In the figure, reference numeral 100 denotes a layout pattern in which hole data of contacts and the like are arranged alone, and 101 denotes a layout pattern in which nine holes data such as contacts are densely arranged. In this embodiment, a layout pattern for processing accuracy verification of two semiconductor devices 100 and 101 is provided.

In an actual layout pattern, since the density distribution of the layout data is not uniform, hole data such as contacts may exist in isolation by itself, or depending on locations, several hole data may exist densely. . Generally, in this case, the opening data of a single contact or the like may have a smaller value for the opening than the opening data of a dense contact or the like. Therefore, in order to realize a highly accurate and highly reliable semiconductor device, it is necessary to control both dimensions.

In FIG. 1 of the present invention, the hole data of the contact and the like can be measured by the dimension measurement of a single body by 100, and the hole data of the contact and the like densely measured by 101 can be measured. Furthermore, if this layout pattern is arranged in a completely different area (for example, a chip corner portion) from the layout area forming the actual logic, even if the data of the layout area is changed by the customer, the processing accuracy verification is always performed. By measuring the layout pattern for use, the processing accuracy of the semiconductor device can be guaranteed, and the time required for verifying the processing accuracy can be drastically reduced. In addition, since the dimension measurement is performed using the opening data having the same shape as the actual layout pattern, the processing of the semiconductor device due to the difference between the actual layout pattern and the layout pattern for processing accuracy verification, which is a problem in the related art, is performed. Accuracy dimensional measurement errors can be eliminated.

In the above description, 101 is 9
Although the description has been made with the individual hole data, these are not limited to nine, and it goes without saying that the same effect can be obtained by arranging more than nine.

Further, these inventions are not limited to the manufacture of semiconductor devices as in the present invention, but are techniques which can be widely applied to general fine pattern dimensional control such as the production of a Cr pattern in the production of a glass mask. Clearly there is.

Further, in the present description, the description has been made with respect to the opening data of contacts and the like, but these ideas can be applied to the wiring data shown in FIG. It is apparent that the same effect can be obtained by manufacturing a processing accuracy verification layout pattern in which a plurality of wiring layout patterns are densely arranged.

[0013]

As described above, according to the configuration of the present invention, in the verification of the processing accuracy at the time of manufacturing a semiconductor device,
By using a layout pattern for verification close to the actual layout pattern, an error between the dimension of the actual layout pattern and the dimension of the layout pattern for processing accuracy verification can be reduced, and highly accurate dimension assurance can be achieved. Also,
By arranging both the single layout data and the dense layout data, it is possible to manage the dimensional variation of the processing accuracy due to the density of the data.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing an embodiment of the present invention.

FIG. 2 is a layout diagram showing an embodiment used conventionally.

[Explanation of symbols]

100: A layout pattern in which hole data such as contacts is a single unit 101: A layout pattern in which hole data such as contacts are dense 200: A layout pattern for verifying processing accuracy of a conventional semiconductor device

Claims (5)

[Claims] 1. A semiconductor device provided with a mark for processing accuracy verification, wherein the mark for processing accuracy verification is constituted by a first mark having the same shape as one of layout data existing in a logical area. A semiconductor device. 2. The semiconductor device according to claim 1, wherein said first mark comprises at least two or more second marks arranged closely. 3. The semiconductor device according to claim 1, wherein a third mark in which both the first mark and the second mark are combined is arranged. . 4. The semiconductor device according to claim 1, wherein said first, second, and third marks are arranged in a first area different from a logic area. Semiconductor device. 5. The first to third aspects according to claim 1 to claim 4.
A glass mask, wherein at least one mark is arranged.