JPH11219237A - Electronic apparatus and control method for electronic apparatus - Google Patents

Abstract

(57) [Problem] To reduce the power consumption of an electronic device in which the operation of the microcomputer is in a standby state in the electronic device incorporating the microcomputer. SOLUTION: In an electronic device incorporating a microcomputer, when the operation of the microcomputer is detected as being in a standby state by a detecting means for detecting that the operation of the microcomputer is in a standby state, the operation of the microcomputer is performed. Means 63 for reducing the frequency of the clock signal that determines the speed is provided so that the power consumption of the electronic device can be reduced when the operation of the microcomputer is in a standby state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic apparatus and a control method for the electronic apparatus, which can reduce power consumption which has not been effectively used in electronic apparatuses.

[0002]

2. Description of the Related Art Conventionally, in an electronic device incorporating a single-chip microcomputer element (hereinafter referred to as a microcomputer), the clock signal frequency of the microcomputer is constant. However, the operating speed of the microcomputer is determined by the clock frequency, and the power consumption of the microcomputer is determined by the clock frequency.

[0003]

In a conventional electric apparatus incorporating such a microcomputer, even when the microcomputer is in a standby state, the operation state in which the microcomputer is executing a predetermined program. Inconveniently, the same amount of power is consumed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to reduce power consumption when a microcomputer is in a standby state and to reduce the power consumption of an electric device incorporating the microcomputer. .

[0005]

An electronic device according to the present invention is provided with a frequency of a clock signal that determines the operating speed of a microcomputer incorporated in the electronic device, and the frequency of the clock signal when the microcomputer is in a standby state. Is controlled to be lower than when the microcomputer is in the operating state, and the power consumption when the microcomputer is in the standby state is reduced.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of an electronic apparatus and a control method of the electronic apparatus according to the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing an embodiment of a microcomputer for controlling the operation of the electronic apparatus and a configuration of a peripheral unit of the microcomputer. FIG. 2 is a block diagram showing a power management section for controlling a clock signal frequency, and FIG. FIG. 3 and FIG. 4 are block diagrams showing an embodiment of a configuration in which a clock signal is supplied from a power management unit to a CPU core unit.
FIG. 4 is a flowchart for executing a procedure for controlling a clock signal frequency in the power management unit.

In FIG. 1, a microcomputer and a peripheral device section of the microcomputer include a microcomputer 1, an operation section 35, an infrared light receiving / emitting element section 40, an RS232C driver section 45,
And a CD module unit 50.

The microcomputer 1 includes a CPU core unit 11, a bus controller unit 13, a bus line unit 15, a ROM unit 17, a RAM 19 unit, a clock signal generation unit 21,
Routing control unit 23, interrupt control unit 25, DMA (Direct Memory Access) unit 27, touch panel I / F unit 29, parallel data → serial data conversion unit 31, digital / analog infrared data It includes a conversion unit 33 and a power management unit 60.

The clock signal generator 21 includes a clock signal generator 21a, a crystal oscillator 21b, a PLL circuit, and 21c.
The operation unit 35 includes a touch panel 35a and an A / D converter 35b, and the LCD module unit 50 includes an LCD panel 50.
a and an LCD driver 50b.

The clock signal generator 21 is a clock signal generator that supplies a clock signal to each of the components included in the microcomputer 1, and the operation unit 35 is an operation that inputs an operation signal of the electronic device from the touch panel 35 a to the microcomputer 1. The RS232C driver section 45 outputs a control signal generated by the microcomputer 1 based on the operation signal input to the microcomputer 1 to a system controller (not shown) of the electronic apparatus in the format of RS232C, and outputs the control signal from the system controller. R transmitted
The driver for inputting the signal of the format of S232C to the microcomputer 1 and the LCD module unit 50 are display means for displaying the operation state of the electronic device according to the operation signal of the electronic device.

The CPU core unit 1 provided in the microcomputer 1
..., An infrared data digital / analog conversion unit 33, an operation unit 35, an infrared light receiving / emitting element unit 40,
RS232C driver 45 and LCD module 5
0 has a well-known configuration, and their respective operations are also well-known. Therefore, description of these configurations and operations will be omitted.

In FIG. 2, a power management unit 60
Includes a standby detection unit 61 and a frequency control unit 63. In FIG. 2, the column labeled "program" indicates the clock frequency speed when the program is executed in the CPU core unit 11, and the column labeled "standby" indicates that the CPU core unit 11 is in a standby state in which no program is being executed. The clock frequency speed at a certain time is shown. The display “(×
“1)” indicates a clock frequency when the CPU core unit 11 is executing a program, and the display “× １ ／” indicates a clock frequency that is ４ times the clock frequency.

The frequency control unit 63 includes the clock signal generation unit 2
A CPU clock signal 63a, a bus clock signal 63b, and a peripheral device clock signal 63c are generated based on the clock signal generated in step 1. The frequency control unit 63 includes a CPU
The clock signal 63a is supplied to the CPU core unit 11, the bus clock signal 63b is supplied to the bus controller unit 13, and the peripheral device clock signal 63c is supplied to the touch panel I / F unit 29, parallel data → serial data conversion unit 31, infrared data Digital / analog conversion unit 33, operation unit 3
5, supply to the RS232C driver unit 45 and the LCD module unit 50.

The standby detecting section 61 is a CPU of the CPU core section 11.
U (not shown), and when it is detected that the operation of the CPU is in a standby state, the standby detection unit 61
Controls the frequency control unit 63 from the CPU clock signal 6
3a and the peripheral device clock signal 63c
X 1/4 of the clock frequency when the PU is in operation
To lower.

However, the frequency of the bus clock signal 63b is set to CP even when the standby state is detected.
The clock frequency when the operation of U is being executed (×
The control is performed by the standby detection unit 61 so as to maintain 1).
In the following description, the clock frequency (× 1) is referred to as high speed, and the clock frequency (× １ ／) is referred to as low speed.

The procedure for controlling the clock signal frequency in the power management unit 60 will be described with reference to FIGS. Note that S used in these flow charts
1, S2, ‥‥ indicate the number of the procedure (step).

S1 ‥‥ Checks a program execution instruction for the CPU core unit 11, and when there is this program execution instruction, shifts to step S2. S2: The frequency control unit 63 is controlled from the standby detection unit 61, and the frequency of the CPU clock signal 63a, the peripheral device clock signal 63c, and the bus clock signal 63b is increased, and the process proceeds to the post-procedure S3. S3: The CPU core unit 11 executes the first program (process A), and when the execution of this program is completed, the process proceeds to step S4.

S4: When the CPU core unit 11 executes the last program (process B) and the execution of this program is completed, the process proceeds to step S5. S5: It is determined by the system clock determination processing whether or not the frequency of the clock signal can be reduced, and if it is determined that the frequency can be reduced, the process proceeds to step S6. S6: The frequency control unit 63 is controlled by the standby detection unit 61 to control the CPU clock signal 63a and the peripheral device clock signal 6
3c, the process returns to step S1 as a stanndby state in which each clock signal is set to a low speed and the frequency of the bus clock signal 63b is maintained at a high speed.

The above S1, S2, S3, S4, S5, S
6. The means for executing the procedure of repeating S1 # is the means for controlling the clock signal frequency in the power management unit 60.

Next, a procedure for controlling the clock signal frequency in the power management unit 60 in the case of the interrupt processing will be described with reference to FIG.

S10 ‥‥ CP in response to an interrupt processing instruction
U clock signal 63a and peripheral device clock signal 63c
And the clock frequency of the bus clock signal 63b at the time of receiving this instruction is stored in the DRAM 19, and the procedure proceeds to step S11.
Move to S11: The frequency control unit 63 is controlled from the standby detection unit 61 to control the CPU clock signal 63a and the peripheral device clock signal 6
3c and the frequency of the bus clock signal 63b are set to a high frequency, and the process proceeds to step S12.

S12 ‥‥ Executes the interrupt program, and when the execution of the interrupt program ends, shifts to step S13. S13: The clock frequencies of the CPU clock signal 63a, the peripheral device clock signal 63c, and the bus clock signal 63b stored in the DRAM 19
And the clock frequencies of the CPU clock signal 63a and the peripheral device clock signal 63c and the bus clock signal 63b which have been set to high speed in step S11
Return to the frequency read from M19.

When the means for executing the procedure repeating steps S10, S11, S12 and S13 is an interrupt process, the power management unit 60 controls the frequency of the clock signal.

According to the embodiment of the electronic apparatus of the present invention described with reference to FIGS. 1 to 4, the C signal generated based on the clock signal generated by the clock signal generator 21.
PU clock signal 63a and peripheral device clock signal 63c
Each clock frequency is set to the CP of the CPU core unit 11.
When U is in the standby state, the clock signal is controlled to be a low-speed clock signal. Therefore, when the CPU is in the standby state, it is possible to reduce the power consumption of the electronic apparatus incorporating the microcomputer having the CPU core unit 11. it can.

According to an experiment conducted by the applicant of the present invention, while the current consumption of the conventional microcomputer was 20 mA on average, the current consumption of the electronic device of the present invention described with reference to FIGS. The microcomputer according to the embodiment requires only an average of 12.5 mA of current consumption, and it has been confirmed that the power consumption can be reduced by about 40% compared to the conventional microcomputer.

In controlling such a low-speed clock signal, if the clock frequency is reduced, the bus clock signal 63b having a functional problem is prevented from being reduced. When switching to the operation in the program execution state, no operation failure occurs.

In this embodiment of the electronic apparatus according to the present invention, the electronic apparatus is further placed in a sleep mode.
When the CPU clock signal 63a
The clock frequency of each of the peripheral device clock signals 63c may be set to a lower speed to further reduce the power consumption.

Also, in this embodiment, the clock frequency of the electronic device is set to the CPU clock signal 63a, the peripheral device clock signal 63c, and the bus clock signal 63b.
The control is performed by dividing the system into two systems. However, the present invention is not limited to such two systems, and the system may be further divided into a larger number of systems to perform fine-grained control and further reduce power consumption. It may be.

[0030]

According to the present invention, in an electronic apparatus incorporating a microcomputer, a detecting means 60 for detecting that the operation of the microcomputer is in a standby state, and the operation of the microcomputer being in a standby state by the detecting means. Means 63 for reducing the frequency of a clock signal that determines the operation speed of the microcomputer based on the detection result when the microcomputer is in the standby state. The power consumption of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a main part of a configuration of an electronic apparatus of the present invention.

FIG. 2 is a circuit block diagram illustrating a main part of a clock signal frequency control unit according to the present invention.

FIG. 3 is a flowchart illustrating a clock signal frequency control procedure according to the present invention.

FIG. 4 is a flowchart showing another procedure of the above control according to the present invention.

[Explanation of symbols]

1 microcomputer, 11 CPU core, 13 bus controller, 15 bus line, 17 RO
M section, 19 RAM section, 21 clock signal generation section, 23 path control section, 25 interrupt control section, 2
7 ‥‥ DMA unit, 35 ‥‥ operation unit, 40 ‥‥ Infrared light receiving / emitting element unit, 45 ‥‥ RS232C driver unit, 50 ‥‥
LCD module, 60 ° power management

Claims (2)

[Claims] In an electronic apparatus incorporating a microcomputer, detecting means for detecting that the operation of the microcomputer is in a standby state, and detecting that the operation of the microcomputer is in a standby state by the detecting means. Means for reducing the frequency of a clock signal that determines the operation speed of the microcomputer based on the detection result. 2. A method for controlling an electronic apparatus incorporating a microcomputer, comprising: reducing a frequency of a clock signal that determines an operation speed of the microcomputer when detecting that the operation of the microcomputer is in a standby state. Control method for electronic equipment.