JPH11203136A - Information processing device and recording medium - Google Patents

Abstract

(57) [Summary] Information with high processing performance can be obtained by reducing interruption of processing when the immediately following instruction uses data read from a memory device or when reading data from a memory device with a low reading speed. It is an object to provide a processing device. When an instruction decoded by a decoder is a data prefetch instruction, a data prefetch circuit reads and stores data stored in a read data holding circuit from a memory device by a previous data prefetch instruction. The data is read and stored in the register file 2, while the data is newly read from the memory device 40 and stored in the read data holding circuit 6. By reading the data stored by the previous instruction, there is no need to wait for the completion of the data reading.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for reading data from a memory device in a pipeline manner in accordance with an instruction and performing an arithmetic operation, an information processing apparatus functioning as a compiler, and a computer-readable recording medium. .

[0002]

2. Description of the Related Art With the recent development of electronic technology, microcomputers and other information processing devices have become widespread and used in various fields. Conventionally, information processing apparatuses often perform pipeline processing in order to improve processing performance. The pipeline processing divides processing of one instruction into a plurality of stages, and executes a plurality of instructions in parallel by shifting the stages.

FIG. 8 is a block diagram showing a configuration of a conventional information processing apparatus. 8, reference numeral 101 denotes a memory device 1
It is a decoder that decodes the instruction 120 read from 40, and outputs the decoding results 113 and 114 and the immediate value 121 included in the instruction. Reference numeral 102 denotes a register file having a plurality of registers for storing data used for calculation, and 103 denotes data 117, data 110 and 111 read from the register file 102, and a decoder 1
Numeral 104 denotes an arithmetic unit that performs an arithmetic operation using the immediate value 121 output. Numeral 104 denotes a unit that reads data from the memory device 140 or writes data to the memory device 140 in accordance with a decoding result 113 obtained by decoding an instruction in the decoder 101. This is a memory control circuit that performs control for performing the operation. 10
5 is a decoding result 11 obtained by decoding the instruction by the decoder 101.
4, the arithmetic unit 103 and the register file 102
It is an execution control circuit for controlling the operation. For example, a case will be described in which one instruction is divided into five stages and pipelined.

The five stages are an instruction fetch stage (hereinafter, IF stage), an instruction decode stage (hereinafter, DEC stage), an operation stage (hereinafter, EX stage), a memory stage (hereinafter, MEM stage), and a write stage (hereinafter, stage). , WB stage). IF
The instruction is read from the memory device 140 in the stage, and the read instruction 120 is decoded by the decoder 101 in the DEC stage. If the decoded instruction is an arithmetic instruction, the data 11 read from the register file 102 in the EX stage
0, 111 or immediate 121 output by the decoder 101
To perform the operation specified by the instruction. The result of the operation is stored in the register specified by the instruction in the register file 102 in the WB stage.

If the decoded command is a data read command or a data write command, in the EX stage, the arithmetic unit 103 uses the data 110, 111 read from the register file 102 or the immediate value 121 given by the command to store data in the memory. An address 115 indicating a location in the device 140 is generated and output to the memory control circuit 104. If the decoded instruction is a data read instruction, the memory control circuit 104 uses the MEM stage to
03 is output as an address 116, data is read from the memory device 140, and the read data 117 is given to the register file 102 and stored in a designated register in the register file 102 in the WB stage. You. Furthermore, when the subsequent instruction uses the data resulting from the data read instruction, the register file 102 stores the data in the register in the WB stage and outputs it directly to the arithmetic unit 103 as data 110 or 111 at the same time. In the case of a data write command, data 118 read from the register file 102 is given to the memory device 140 in the MEM stage, and at the same time, the memory control circuit 104
Is supplied to the memory device 140 as the address 116, and the data 118 is stored in the location specified by the address 116 in the WB stage.

FIG. 9 shows an example of a pipeline operation of a conventional information processing apparatus. FIG. 9 shows a state where four instructions are being executed. In this figure, a0, d0, d1, d2
Is the name of the register in the register file 102. (A0) indicates data in the memory device designated by using the value of the register a0 as an address. The first instruction and the third instruction are data read instructions mov, and the second instruction
The instruction and the fourth instruction are addition instructions add. The first instruction mov reads data from the memory device 140 using the value of the register a0 as an address and stores the data in the register d0. The second instruction add adds the value of the register d2 to 1 and stores the addition result in the register d2. 3rd instruction mo
As for v, 4 is added to the value of the register a0, data is read from the memory device 140 using the result as an address, and stored in the register d1. The fourth instruction add is the register d
The value of 2 and 1 are added, and the addition result is stored in the register d2.

Each instruction includes IF, DEC, EX, MEM,
The WB is divided into five stages, and each stage is executed during one clock cycle. The four instructions are executed in parallel, shifted by one stage. Therefore, processing of each instruction requires 5 clock cycles,
By performing such pipeline processing, a result of an instruction can be obtained every cycle, and high processing performance can be realized.

[0008]

However, when the data read by the data read command is used by the next command for the operation or when the reading of the memory device is slow, the processing performance is reduced. FIG. 10 shows a case where the data read by the mov instruction is used by the immediately following instruction for the operation.

In FIG. 10, a first instruction mov reads data from the memory device 140 using the value of the register a0 as an address and stores it in the register d0. This data is assumed to be A. The second instruction add adds the data A stored in d0 by the first instruction mov and the value of the register d1, and stores the resulting data in the register d1. 3rd instruction
mov reads data from the memory device 140 using the value obtained by adding 4 to the value of the register a0 as an address and stores the data in the register d0. This data is B. 4th instruction ad
d adds the data B stored in d0 by the third instruction mov and the value of the register d1, and stores the resulting data in the register d1. In this case, the second and fourth instructions a
Since dd uses the data read from the memory device 140 by the immediately preceding instruction mov for the operation, the data read from the register file 102 is not correct unless the EX stage of the add instruction is after the WB stage of the mov instruction. At this time, the register file 102 stores the data 117
Is directly supplied to the arithmetic unit 103 as data 110, so that the EX stage of the add instruction
It can be parallel to the B stage. However, since the data read by the mov instruction cannot be used until the WB stage of the mov instruction is reached, the EX stage of the add instruction is kept waiting until the WB stage of the mov instruction. As described above, when the next instruction uses the data read by the data read instruction for the operation, the execution of the instruction is waited, and the processing performance is reduced.

FIG. 11 shows a case where the reading speed of the memory device is low. In this example, the instructions to be executed are the same as in FIG. 9, but reading the memory device requires an additional two clock cycles more than in FIG. Second
Although the instruction and the fourth instruction add do not use the data read by the immediately preceding instruction mov, the WB stage of the add instruction is suspended until the WB stage of the mov instruction is completed.
As described above, the processing of the add instruction is interrupted, and the processing performance is reduced.

An object of the present invention is to provide an information processing apparatus with high processing performance and a recording medium storing a program, in which interruption of processing of a subsequent instruction by a data read instruction from a memory is reduced. .

[0012]

According to a first aspect of the present invention, there is provided an information processing apparatus comprising: an instruction sequence including a specific instruction for instructing at least reading of first data from a memory device and operation of second data; Command reading means for extracting the data read from the memory device, data holding means for storing data read from the memory device, decoding means for decoding the instruction read by the instruction reading means, and a register. If it is deciphered that the instruction has been placed,
Executing means for calculating a read address of the first data, starting access to read the first data from the memory device based on the calculated address, extracting the second data from the data holding means, and storing it in a register Wherein the second data is data read as the first data based on the specific command decoded by the decoding unit before the specific command is decoded.

According to the information processing apparatus of the first aspect, after the data read from the memory device based on the execution of the specific instruction previously decoded by the decoding means is read from the data holding means, a new memory is read. The data can be read from the device, and the next instruction can be processed without waiting for the completion of the data reading from the memory device, thereby reducing the processing time and improving the processing performance. Can be very useful.

[0014] The information processing apparatus according to the second aspect is the first aspect.
In the above, the execution means performs the operation of storing the read first data in the data holding means when the access for reading the first data started by the specific instruction is completed. Is performed in parallel with the execution of the instruction following the. According to the information processing apparatus of the second aspect, the same effect as that of the first aspect is obtained.

According to a third aspect of the present invention, there is provided the information processing apparatus according to the first aspect.
Alternatively, the information processing apparatus according to claim 2, wherein the first stage for reading the instruction, the second stage for decoding the instruction, and the second stage for performing an operation specified by the instruction or calculating an address for accessing a memory device. A pipeline structure including five stages, a third stage, a fourth stage for accessing the memory device, and a fifth stage for storing a result of an operation specified by the instruction in a register, The instruction reading means operates in the first stage, the decoding means operates in the second stage, and the executing means operates in the third to fifth stages, and in particular, fetches the second data from the data holding means. This is performed in the fourth stage.

According to the information processing apparatus of the third aspect, the same effects as those of the first or second aspect can be obtained. The information processing device according to claim 4, wherein at least the first
Instruction reading means for extracting an instruction from an instruction sequence including a specific instruction for instructing the reading of the data and the operation of the second data, and the second means for storing two or more n data read from the memory device. A first to an n-th data holding unit, a decoding unit for decoding an instruction read by the instruction reading unit, and an increment by one each time a specific instruction is decoded by the decoding unit. And a register circulating between n and n. When the decoding means decodes that a specific instruction is placed, a read address of the first data is calculated, and the calculated address is calculated. , Access is started to read the first data from the memory device, and the second data is taken out from the k-th data holding means determined by the value k indicated by the counting means and stored in the register. And a performing unit that, the second data is characterized in that the particular instruction that is decoded is data that has been read as the first data based only on the front of a particular instruction n.

According to the information processing apparatus of the fourth aspect, in addition to the same effect as the first aspect, the next instruction can be processed without waiting for the completion of the reading of data from the n memory devices. Thus, the processing time can be further reduced. According to a fifth aspect of the present invention, in the information processing apparatus according to the fourth aspect, the execution means includes:
This is performed when the access for reading the first data started by the specific instruction is completed, and the first read data is read.
Is stored in the k-th data holding means in parallel with the execution of the instruction following the specific instruction.

According to the information processing apparatus of the fifth aspect, the same effect as that of the fourth aspect is obtained. 7. The information processing device according to claim 6, wherein the instruction reading unit extracts an instruction from an instruction sequence including a specific instruction instructing at least reading of the first data from the memory device and operation of the second data, and the memory device. A data holding unit for storing data read from the data holding unit, a data valid flag indicating whether the data stored by the data holding unit is valid or invalid, a decoding unit for decoding the instruction read by the instruction reading unit, A decoding unit that calculates a read address of the first data and decodes the first data from the memory device based on the calculated address when the decoding unit determines that the specific instruction is placed. When access is started to read and the data valid flag indicates valid, the second data is taken out from the data holding means and stored in the register. Executing means for, when the data valid flag indicates invalid, waiting for the data valid flag to indicate valid, extracting the second data from the data holding means and storing the second data in a register; Is data read as first data based on a specific command decoded by the decoding means before the command is decoded.

According to the information processing apparatus of the present invention, in addition to the same effects as those of the first aspect, it is possible to prevent reading of an incorrect value from the data holding means before data reading is completed. Useful. 7. The information processing apparatus according to claim 7, wherein the execution unit stores the read first data when the access for reading the first data started by the specific instruction ends. The operation of storing the data in the holding unit and validating the data valid flag is performed in parallel with the execution of the instruction following the specific instruction.

According to the information processing apparatus of the seventh aspect, the same effect as that of the sixth aspect is obtained. In the information processing apparatus according to the present invention, when the decoding means further receives an interrupt request from the outside when the data valid flag indicates valid, the decoding means receives the interrupt request, When the valid flag indicates invalid, the interrupt request is accepted after the data valid flag indicates valid.

According to the information processing device of the present invention, in addition to the same effects as those of the sixth or seventh embodiment, it is possible to cope with an interrupt request generated after a specific instruction without inconsistency. The information processing device according to claim 9 is the information processing device according to claim 8, wherein when the decoding unit receives the interrupt request,
The data held in the data holding means is saved in a predetermined area of the memory device or another memory device.

According to the information processing apparatus of the ninth aspect, the same effect as that of the eighth aspect can be obtained. 11. The information processing device according to claim 10, wherein the instruction reading unit extracts an instruction from an instruction sequence including a specific instruction instructing at least reading of the first data from the memory device and operation of the second data, and the memory device. A data holding means for storing data read from the memory, a decoding means for decoding the instruction read by the instruction reading means, and a register, wherein the decoding means decodes that a specific instruction is placed. If
The read address of the first data is calculated, access is started to read the first data from the memory device based on the calculated address, the second data is taken out from the data holding means, and the operation specified by the instruction is performed. And executing the data stored in a register after the execution of the second instruction. The second data is data read out as first data based on the specific instruction decoded by the decoding means before the specific instruction is decoded. It is characterized by having.

According to the information processing apparatus of the tenth aspect,
In addition to the same effect as in claim 1, the memory is operated by using data stored in the data holding means, that is, data read from the memory device by a specific instruction previously decoded by the decoding means. The calculation can be performed while reducing the time required for reading the device, and the processing performance can be improved, which is extremely useful.

[0024] In the information processing apparatus according to claim 11, in claim 10, the execution means is executed when the access for reading the first data started by the specific instruction ends, and The operation of storing one data in the data holding means is performed in parallel with the execution of the instruction following the specific instruction. According to the information processing apparatus of the eleventh aspect, the same effect as that of the tenth aspect is obtained.

According to a twelfth aspect of the present invention, there is provided the information processing apparatus according to the tenth or eleventh aspect, wherein the first stage for reading the instruction, the second stage for decoding the instruction,
A third stage for performing an operation specified by the instruction or calculating an address for accessing the memory device, a fourth stage for accessing the memory device, and a fifth stage for storing a result of the operation specified by the instruction in a register An instruction reading unit operates in a first stage, a decoding unit operates in a second stage, and an execution unit operates in the third to fifth stages. The operation is performed in the third stage, and in particular, the extraction and the calculation of the second data from the data holding means are performed in the third stage.

According to the information processing apparatus of claim 12,
There is an effect similar to that of the tenth or eleventh aspect. 14. The information processing apparatus according to claim 13, wherein the information processing apparatus generates, from the high-level language program, a machine instruction program for a processor that performs a pipeline process, wherein the variable allocated to the memory device in the high-level language program. Read code detecting means for detecting a code for reading the data, and, when the code is detected, calculating an address of the memory device assigned to the variable, and starting a read access of the memory device based on the calculated address. It is provided with a machine instruction generating means for generating a first machine instruction and a second machine instruction for storing data read when access is completed in a predetermined register.

According to the information processing apparatus of claim 13,
A machine instruction program capable of processing the next machine instruction can be generated without waiting for the completion of the first machine instruction.
Therefore, processing performance can be improved. According to a fourteenth aspect of the present invention, in the information processing apparatus according to the thirteenth aspect, the machine instruction generating means generates the first machine instruction and the second machine instruction by separating them by a fixed number of instructions.

[0028] According to the information processing apparatus of the fourteenth aspect,
This has the same effect as the thirteenth aspect. 16. The information processing apparatus according to claim 15, wherein the information processing apparatus generates a machine instruction program for a processor performing a pipeline process from the high-level language program, wherein n is assigned to a memory device in the high-level language program. Read code detecting means for detecting a code for reading the variables; and, when the code is detected, calculating respective addresses of the memory devices allocated to the n variables, and based on the calculated addresses. For each of the first to n-th machine instructions for starting a read access of the memory device and the first to n-th accesses corresponding to the first to n-th machine instructions, data read when the access is completed. Are stored in a predetermined register, and the (n + 1) -th to (2n) -th machine instructions are generated in the order of first to second-n machine instructions. It is obtained by a means.

According to the information processing apparatus of claim 15,
A machine instruction program capable of processing the nth next machine instruction can be generated without waiting for completion of the first to nth machine instructions. Therefore, processing performance can be improved. The information processing device according to claim 16 is the information processing device according to claim 15,
The machine instruction generating means generates the k-th machine instruction and the (k + n) -th machine instruction for k from 1 to n by a fixed number of instructions.

According to the information processing apparatus of the sixteenth aspect,
There is an effect similar to that of claim 15. 18. The information processing apparatus according to claim 17, wherein the information processing apparatus generates, from the high-level language program, a machine instruction program for a processor that performs a pipeline process, wherein the variable allocated to the memory device in the high-level language program. Read code detecting means for detecting a code for reading the data, and, when the code is detected, calculating an address of the memory device assigned to the variable, and starting a read access of the memory device based on the calculated address. A machine instruction generating means for generating a first machine instruction and a second machine instruction to perform a proper operation on the data read when the access is completed and to store the second machine instruction in a predetermined register; Information processing device provided with.

According to the information processing apparatus of claim 17,
The next machine instruction can be processed without waiting for the completion of the first machine instruction, and furthermore, the operation is defined in parallel by the second machine instruction, so that a machine instruction program with high code efficiency can be generated. . An information processing apparatus according to claim 18 is the information processing apparatus according to claim 1.
In 7, the machine instruction generating means generates the first machine instruction and the second machine instruction by separating them by a fixed number of instructions.

[0032] According to the information processing apparatus of the eighteenth aspect,
There is an effect similar to that of the seventeenth aspect. In the information processing apparatus according to claim 19, in claim 13, claim 14, claim 17, or claim 18, the machine instruction generating means is configured to generate a group of the generated machine instruction program in the group. An instruction for disabling interrupt reception is arranged and generated at a position preceding the first first machine instruction, and an instruction for permitting interrupt reception is generated at a position prior to the last second machine instruction in the group. It is generated by arranging.

According to the information processing apparatus of the nineteenth aspect,
Claim 13, Claim 14, Claim 17, or Claim 1
In addition to the effect similar to that of FIG. 8, it is possible to prevent inconsistency in the read data due to an interrupt request generated between the first machine instruction and the second machine instruction. 21. The recording medium according to claim 20, wherein a machine instruction program executed by a processor performing pipeline processing is recorded, wherein the machine instruction program calculates an address of a memory device allocated to a variable, and calculates A first machine instruction for starting a read access of the memory device based on the read address, and a second machine instruction for storing data read in a predetermined register when the access is completed. It is assumed that.

According to the recording medium of the twentieth aspect, the first
A machine instruction program capable of processing the next machine instruction without waiting for the completion of the previous machine instruction is recorded. The recording medium according to claim 21 is the recording medium according to claim 20, wherein the first machine instruction and the second
Are separated from each other by a fixed number of instructions. According to the recording medium of claim 21, claim 2 is provided.
It has the same effect as 0.

A recording medium according to a twenty-second aspect is a recording medium recording a machine instruction program to be executed by a processor that performs pipeline processing, wherein the machine instruction program is stored in a memory device assigned to n variables. First to n-th machine instructions for calculating respective addresses and initiating read access of the memory device based on the calculated addresses; and first to n-th access instructions corresponding to the first to n-th machine instructions. Each of them is characterized by including (n + 1) -th to (2n) -th machine instructions for storing data read out at the time of completion of access in a predetermined register in order of first to second-n.

According to the recording medium of the twenty-second aspect, the first
, A machine instruction program capable of processing the nth next machine instruction without waiting for completion of the nth machine instruction.
The recording medium according to claim 23 is the recording medium according to claim 22, wherein
K to the k-th machine instruction and the (k +
The machine instruction of n) is arranged to be separated by a fixed number of instructions.

According to the recording medium of the twenty-third aspect, the same effect as that of the twenty-second aspect is obtained. The recording medium according to claim 24, wherein the machine instruction program executed by a processor that performs a pipeline process is recorded.
The machine instruction program calculates a memory device address assigned to a variable, and a first machine instruction for initiating a read access of the memory device based on the calculated address; and a machine instruction program read when the access is completed. And a second machine instruction to store the data in a predetermined register after performing an appropriate operation on the data.

According to the recording medium of the twenty-fourth aspect, the first
The next machine instruction can be processed without waiting for the completion of this machine instruction, and the operation is defined in parallel by the second machine instruction, so that a machine instruction program with high code efficiency is recorded. A recording medium according to a twenty-fifth aspect is the recording medium according to the twenty-fourth aspect, wherein the first machine instruction and the second machine instruction are arranged apart from each other by a fixed number of instructions.

According to the recording medium of the twenty-fifth aspect, the same effect as that of the twenty-fourth aspect can be obtained. The recording medium according to claim 26 is the recording medium according to claim 20, 21, 24 or 25, wherein a group of machine instruction programs precedes a first first machine instruction in the group. An instruction for disabling interrupt acceptance is arranged at a position, and an instruction for permitting interrupt acceptance is arranged at a position preceding the last second machine instruction in the group.

According to the recording medium of the twenty-sixth aspect, in addition to the same effects as those of the twentieth, twenty-first, twenty-fourth, or twenty-fifth aspects, the first medium instruction and the second machine instruction are It is possible to prevent read data from being accompanied by inconsistency due to an interrupt request generated therebetween.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. (First Embodiment) A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of the information processing apparatus according to the first embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a decoder which decodes an instruction 20 read from the memory device 40, and outputs decoded results 13 and 14, an immediate value 21 included in the instruction, and a data prefetch signal 22. Reference numeral 2 denotes a register file having a plurality of registers for storing data used for the operation. Reference numeral 3 denotes data 10 and 11 read from the register file 2 or immediate data 2 output from the decoder 1.
1 is an arithmetic unit for performing an arithmetic operation, and 4 is a decoder 1
The data is stored in the memory device 40 according to the decoding result 13 of the
And a memory control circuit that performs control for reading data from and writing data to the memory device 40. 5 is an arithmetic unit 3 according to a decoding result 14 of the decoder 1;
An execution control circuit for controlling the register file 2 and the like.

A read data holding circuit 6 temporarily holds data read from the memory device 40.
Reference numeral 8 denotes a data pre-reading circuit which reads data previously stored in the read data holding circuit 6 and outputs the data to the register file 2 before reading data from the memory device 40. The information processing apparatus mainly includes an instruction reading unit that extracts an instruction from an instruction sequence including a specific instruction instructing at least reading of the first data from the memory device 40 and operation of the second data. An instruction read control circuit 25, a read data holding circuit 6 constituting data holding means for storing data read from the memory device 40, and a decoder 1 serving as a decoding means for decoding the instruction read by the instruction reading means. And a register file 2, and when it is determined by the decoding means that a specific instruction is placed, a read address of the first data is calculated, and from the memory device 40 based on the calculated address. Access is started to read out the first data, and the second data is taken out from the data holding means and stored in the register file 2. And an execution unit 26 mainly configured as an execution unit for storing the second instruction. The second data is read out as first data based on the specific instruction decoded by the decoding unit before the specific instruction is decoded. This is the data.

Also in the first embodiment, FIG.
As in the conventional information processing apparatus shown by, the IF stage, D
Instructions are processed in five stages: an EC stage, an EX stage, a MEM stage, and a WB stage. Data reading, data writing, and processing of operation instructions are processed in the same manner as in the related art. However, in the case of data reading, the data 17 read from the memory device 40 is given to the register file 2 as data 24.

The processing of the data prefetch instruction will be described. The data read-ahead instruction reads the data stored in the read data holding circuit 6 before storing the data read from the memory device 40 using the specified address in the read data holding circuit 6 and specifies the register file 2 This is the instruction to be stored in the registered register. That is,
This is an instruction to store data read from the memory device 40 by the previously executed data prefetch instruction in the register file 2 and to execute a new read from the memory device 40 at the same time.

The operation of the data prefetch instruction will be described with reference to FIG. The decoder 1 decodes the instruction 20 read from the memory device 40 by the instruction read control circuit 25. The decoding results 13 and 14 are output to the memory control circuit 4 and the execution control circuit 5. Further, when the decoded instruction is a data prefetch command, the decoder 1 outputs a data prefetch signal 22 to the data prefetch circuit 8. The arithmetic unit 3 calculates an address using the data 10 and 11 read from the register file 2 in the EX stage or the immediate 21 output from the decoder 1 under the control of the execution control circuit 5, and outputs the address to the memory control circuit 4. . The memory control circuit 4 outputs the address 15 output from the arithmetic unit 3 as the address 16 in the MEM stage,
0 is requested to read data. Data prefetch circuit 8
When the data prefetch signal 22 is applied, the data read signal 23 is output at the MEM stage, and the data stored in the read data holding circuit 6, that is, the data read from the memory device 40 by the previous data prefetch command is stored. The read data is read and given to the register file 2 as data 24, and the register file 2 stores the data 24 in the register specified by the instruction in the WB stage. Further, when the subsequent instruction uses data resulting from the data prefetch instruction, the register file 2 stores the data in the register at the same time as storing the data in the register in the WB stage.
Output directly to the arithmetic unit 3 as 0 or 11.

The data prefetch instruction is executed before it becomes necessary for the operation. Then, when necessary for the operation, the data prefetch instruction is executed again. By the second data prefetch instruction, data read from the memory device 40 by the first data prefetch instruction is obtained,
Used for calculation. Further, data is read from the memory device 40 by the second data prefetch command, and the read data is obtained by the third data prefetch command and used for the operation. This operation will be described with reference to FIGS.

FIGS. 2 and 3 are diagrams showing examples of the pipeline operation of the information processing apparatus according to the first embodiment. In FIG. 2, the first, third, and fifth
Is a data prefetch instruction movp. First instruction m
In the ovp, the address calculation is performed in the EX stage, the data is read from the memory device 40 to the MEM stage using the obtained address a0, and the data already stored in the read data holding circuit 6 is read. , To the register file 2. The register file 2 stores the data read from the read data holding circuit 6 in the register specified in the WB stage of the first instruction movp. The next data look-ahead instruction, ie, the third
In the instruction movp, an address is calculated in the EX stage, data is read from the memory device 40 in the MEM stage using the obtained address a0 + 4, and at the same time, data already stored in the read data holding circuit 6 is read. This is given to register file 2. At this time, the read data holding circuit 6 stores the address a0 with the previous data prefetch instruction, that is, the first instruction movp.
And the data A read from the memory device 40 is stored in the register file 2, and is stored in the register d0 specified in the WB stage of the third instruction movp.

The fourth instruction add performs addition using the data A stored in d0 in the third instruction. E of the fourth instruction add
The X stage is in parallel with the MEM stage of the third instruction movp, and the data d has not yet been stored in the register d0. Therefore, the register file 2 stores the third instruction mov
The data A read from the read data holding circuit 6 is immediately supplied to the arithmetic unit 3 as the data 10 or the data 11 to the p MEM stage. As a result, the EX stage of the fourth instruction add executes the addition without waiting.

Similarly, the fifth instruction movp is transmitted from the read data holding circuit 6 to the third instruction movp in the MEM stage.
p reads the data B read from the memory device 40 and outputs it to the register file 2, and the sixth instruction add uses the data B output from the read data holding circuit 6 to the register file 2 to add data to the EX stage. Do.

As described above, the data prefetch instruction executes the reading of data from the memory device 40 and simultaneously executes the data read from the memory device 40 and stored in the data holding circuit 6 by the previous data prefetch instruction. , The process can be performed without waiting even when the instruction immediately after uses the result of the data prefetch instruction.

FIG. 3 illustrates the operation of the data prefetch command when the read speed of the memory device 40 is low. In FIG. 3, the first, fourth, and seventh instructions are data prefetch instructions movp. Here, compared to the case of FIG.
The data reading time of the memory device 40 is longer by two clock cycles, and the data 17 read at L (hereinafter, quasi-L stage) written two clock cycles after the WB stage of the movp instruction. Is stored in the read data holding circuit 6. However, since the movp instruction reads the data already stored in the read data holding circuit 6 and stores the data in the register file 2, the subsequent instruction is processed without waiting for the completion of the data read from the memory device 40 of the movp instruction. It can be performed. The L stage of the first instruction movp is the fourth instruction mov
p is parallel to the MEM stage, so the fourth instruction mov
In p, data stored in the read data holding circuit 6, that is, data A read from the memory device 40 by the first instruction movp is read in the MEM stage and stored in the register d0 in the WB stage. Similarly, in the MEM stage of the seventh instruction movp, the data stored in the read data holding circuit 6, ie,
The data B read from the memory device 40 is read by the fourth instruction movp, and the register d is set in the WB stage.
1 is stored. As described above, even when the reading speed of the memory device 40 is low, the instruction can be executed without stopping the processing. Here, an appropriate instruction is inserted between the two data prefetch instructions, and after the memory read of the preceding data prefetch instruction movp is completed, the succeeding data prefetch instruction movp receives the data from the read data holding circuit 6. The timing is adjusted so as to read out.

As described above, according to the first embodiment of the present invention, data previously read from the memory device 40 can be read from the read data holding circuit 6 by the data prefetch circuit 8 when necessary. Therefore, the time for stopping for waiting for data can be reduced, and the processing performance is improved. Further, even when the reading speed of the memory device 40 is low, the subsequent instruction can be executed without waiting for the completion of the reading of the data from the memory device 40, and the processing performance is improved.

It is assumed that a plurality of data can be held in the read data holding circuit 6, and the data read out and stored from the memory device 40 by the data pre-read command a plurality of times before is read out from the read data holding circuit 6. Is also good. In this case, the read data holding circuit 6 is provided with first to n-th n sub-data holding circuits,
Further, an n-ary counter that is incremented by one each time the data prefetch instruction is decoded by the decoder 1 and circulates from 1 to n is provided, and data is read from the k-th sub-data holding circuit determined by the value k indicated by the counter. This can be realized by storing the data read from the memory device 40 in the k-th sub-data holding circuit. (Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram illustrating a configuration of an information processing apparatus according to the second embodiment of the present invention.

In FIG. 4, the same components as those of the information processing apparatus according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals, the description thereof will be omitted, and different points will be mainly described. FIG.
In the figure, reference numeral 30 denotes a data valid flag, which determines whether data read from the memory device 40 by the previous data pre-read instruction is stored or not stored in the read data holding circuit 6 by a data valid signal 31. Show. When the data valid signal 31 is “1”, it indicates that the data read from the memory device 40 by the previous data prefetch command has been completed and the data has already been stored in the read data holding circuit 6, and when the data valid signal 31 is “0”. Indicates that the data according to the previous data prefetch instruction has not been stored in the read data holding circuit 6 yet. Note that the initial value of the data valid signal 31 is “1”.

When the instruction 20 given to the decoder 1 is a data prefetch instruction, the decoder 1
3 and 14 are output to the memory control circuit 4 and the execution control circuit 5, and the data prefetch signal 22 is output to the data prefetch circuit 8. The arithmetic unit 3 operates according to the control of the execution control circuit 5,
The address 15 is calculated using the data 10 and 11 read from the register file 2 or the immediate 21 output from the decoder 1 in the EX stage, and output to the memory control circuit 4. The data prefetch circuit 8 examines the data valid signal 31 output from the data valid flag 30 when the data prefetch signal 22 is supplied, and when the data valid signal 31 is “0”, that is, the memory device according to the previous data prefetch command. If it is determined that the reading from the memory 40 has not been completed, the execution stop request signal 33 is output to the execution control circuit 5 and the memory control circuit 4, whereby the execution control circuit 5 and the memory control circuit 4 process the instruction. To stop. When the data read from the memory device 40 by the previous data prefetch command is completed and the read data 17 is stored in the read data holding circuit 6, the memory device 40 simultaneously outputs the read completion signal 32 to the data valid flag 30. As a result, the data valid signal 31 is set to "1". When the data valid signal 31 is set to "1", the data prefetch circuit 8 releases the execution stop request signal 33, and the execution control circuit 5 and the memory control circuit 4 resume processing. The data prefetch circuit 8 outputs a data read signal 23 to read data 24 from the data holding circuit 6. The read data 24 is supplied to the register file 2 and stored in the register specified by the instruction in the WB stage. Further, when the data read signal 23 is output, the data valid signal 31 of the data valid flag 30 is reset to “0”, and at the same time, the memory control circuit 4 uses the address 15 given from the arithmetic unit 3 to Requests data reading to 40. When the reading of the requested data is completed, the memory device 40 stores the data 1
7, and the read data 17 is stored in the read data holding circuit 6. When the data is stored in the read data holding circuit 6 and the read completion signal 32 is given, the data valid flag 30 outputs “1” to the data valid signal 31.

The data valid signal 31 is already "1" at the MEM stage of the data prefetch instruction, and the data read from the memory device 40 by the previous data prefetch instruction is already stored in the read data holding circuit 6. When indicated, the data prefetch circuit 8 executes the execution stop request signal 3
The processing is continued without outputting 3. In this way, when executing the data prefetch instruction, if the data reading of the memory device 40 by the previous data prefetch instruction is not completed, the data reading is performed until the data reading is completed.
The execution of the instruction can be stopped, and the value before storing the data can be prevented from being read from the read data holding circuit 6 by mistake.

Therefore, between two data prefetch instructions,
Even if a valid instruction cannot be inserted for the number of data reading cycles, there is no need to insert a NOP instruction for instructing no operation, and the size of the program can be reduced. Further, when the data read time changes depending on whether the cache memory hits or does not hit, as in the case where a cache memory is used as the memory device 40, two data prefetches are performed in accordance with the case where the data read is fast. Instructions can be stopped even if data reading is delayed by inserting instructions between instructions, preventing an incorrect value from being read from the read data holding circuit and reducing the size of the program. Program creation is easy.

Note that, in addition to the above configuration, the decoder 1
Then, it is determined whether or not to accept an externally applied interrupt request based on the value of the data valid signal 31, and when the interrupt is received, the data stored in the read data holding circuit 6 is saved to an appropriate area. A function may be added. That is, the interrupt request transmitted by the predetermined signal line is pending while the data valid signal 31 is “0”, and is accepted when the data valid signal 31 becomes “1”.
The saving of the data in the read data holding circuit 6 is for restoring the data when returning from the interrupt processing. By doing so, it is possible to cope with an interrupt request generated after the data prefetch instruction without inconsistency. (Third Embodiment) A third embodiment of the present invention will be described with reference to FIGS. FIG. 5 shows a third embodiment of the present invention.
It is a block diagram showing the structure of the information processing apparatus in embodiment.

In FIG. 5, the same components as those of the information processing apparatus according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. The different points will be mainly described. FIG.
In the information processing device, the data 24 read from the read data holding circuit 6 can be given to the arithmetic device 3 and used for the arithmetic. A case of executing a data prefetch operation instruction will be described. The data prefetch operation instruction is an instruction for performing an operation using data read from the memory device 40 by the previously executed data prefetch operation instruction.

When the decoder 1 decodes that the instruction 20 given to the decoder 1 is a data prefetch operation instruction,
The data prefetch signal 22 is output to the data prefetch circuit 8. When receiving the data pre-reading signal 22, the data pre-reading circuit 8 reads out the data read from the memory device 40 by the previous data pre-reading operation instruction from the read data holding circuit 6 and outputs the data to the arithmetic unit 3. In the EX stage, the arithmetic unit 3 controls the data 10 read from the register file 2 under the control of the execution control circuit 5,
11 or the immediate value 21 output from the decoder 1, and at the same time, the data 24 read from the read data holding circuit 6 and the data 10, 11 or the decoder read from the register file 2 are calculated. The operation indicated by the instruction is executed using the immediate value 21 output from 1. The operation result 12 is the register file 2
And stored in the register specified by the instruction in the WB stage. Further, the memory control circuit 4 uses the address 15 output from the arithmetic unit 3 for the MEM stage,
Data is read from the memory device 40, and the read data is stored in the read data holding circuit 6. This operation will be described with reference to FIG.

FIG. 6 is a diagram showing a pipeline operation when a data prefetch operation instruction is executed by the information processing apparatus according to the third embodiment. In FIG. 6, the first instruction is a data prefetch instruction movp, and the third and fifth instructions are a data prefetch addition instruction addp which is one of data prefetch operation instructions. The third instruction addp is the first
The data A read from the memory device 40 by the instruction movp is added to the value of the register d0, and the result is stored in the register d0. Further, a0 + 4 is calculated and used as an address, and data B is read from the memory device 40. The fifth instruction addp adds the data B read from the memory device 40 by the third instruction addp to the value of the register d0, and stores the result in the register d0. Further, the data C is read from the memory device 40 by calculating a0 + 8 as an address.

As described above, according to the third embodiment of the present invention, the data prefetch operation instruction performs the operation using the data read by the previous data prefetch operation instruction, and simultaneously executes the next data prefetch operation. Since the reading of the data used in the operation instruction is started, the operation can be performed without waiting for the reading of the data from the memory device 40, the data waiting cycle can be reduced, and the processing performance can be improved.

Here, the data prefetch addition instruction a
In the ddp, the address calculation and the operation are performed simultaneously in the EX stage. However, the address calculation and the operation may be performed sequentially in another clock cycle.
In this example, addition is performed as an operation of a data prefetch operation instruction. However, the present invention can be applied to various operations other than addition, such as subtraction, logical product, and logical sum. (Fourth Embodiment) A fourth embodiment of the present invention will be described with reference to FIG. This information processing apparatus is an information processing apparatus that generates a machine instruction program for a processor that performs pipeline processing from a high-level language program, and a code that reads a variable assigned to a memory device in the high-level language program. And a machine instruction generating means for calculating the address of the memory device assigned to the variable when the code is detected, and based on the calculated address. A first machine instruction for starting a read access of the memory device and a second machine instruction for storing data read in a predetermined register when the access is completed.

FIG. 7 is a block diagram showing a configuration of an information processing apparatus according to the fourth embodiment of the present invention. The information processing device 702 functions as a compiler that translates a C language program 701 written by a user and outputs a machine instruction program 710. The information processing device 702
A file reading unit 703 that reads the language program 701 into the reading buffer 704, and a syntax analysis unit that generates an intermediate code by analyzing the syntax and meaning of the C language program read into the reading buffer 704 and writes the intermediate code into the intermediate code buffer 706. 705, a machine instruction generation unit 707 that receives the intermediate code stored in the intermediate code buffer 706 to generate a machine instruction program and writes the machine instruction program to the output buffer 708, and stores the machine instruction program stored in the output buffer 708 in a file. File output unit 709 to output to
It is composed of

Table 1 is a program list showing an example of a C language program.

[0067]

[Table 1]

Table 2 is a list showing the intermediate code programs stored in the intermediate code buffer 706 of the information processing device 702 when the C language program shown in FIG.

[0069]

[Table 2]

Table 3 is a list showing a machine instruction program 710 generated by the information processing device 702 when the C language program shown in Table 1 is given as an input. Note that the machine instruction program is originally a bit string of 0s and 1s, but is represented by a mnemonic in FIG. 10 to represent the meaning.

[0071]

[Table 3]

Hereinafter, the operation of the information processing apparatus having the above configuration when the program list of Table 1 is input will be described with reference to Tables 1 to 3. File reading unit 7
03 reads the C language program 701 written by the user and stores it in the read buffer 704. The syntax analysis unit 705 extracts the C language program stored in the read buffer 704. "Int" of the program shown in Table 1
eger A, B; "and" register "
r; ”, when the following lines are expanded into intermediate code, the variables A and B are allocated to the memory, and the variable r
Proceeds assuming that is assigned to a register.

Next, the syntax analyzer 705 extracts the C language program stored in the read buffer 704. Table 1
For the program “r = r + A;”, the intermediate code 1 “d0 ← mem” meaning that data is read from the memory storing the variable A and stored in the register d0
(A) ", an intermediate code 2 meaning that the register d0 and the register d1 storing the variable r are added and stored in d1.
“D1 ← d1 + d0” is stored in the intermediate code buffer 706
Output to

Further, the syntax analyzer 705 extracts the C language program stored in the read buffer 704. For “r = r + B;” in the program shown in Table 1, data is read from the memory in which the variable B is stored, and the data is read from the register d0.
Code "d0 ← mem (B)" meaning intermediate code 3
And the intermediate code 4 “d1 ← d” which means to add the register d0 and the register d1 in which the variable r is stored and store the result in d1.
1 + d0 ”to the intermediate code buffer 706.

It is assumed that the following description is made in the C language program. The machine instruction generation unit 707 extracts the intermediate code 1 stored in the intermediate code buffer 706 and generates a corresponding instruction 1. It is assumed that the variable A is assigned to the address indicated by the register a0 of the memory. Next, the machine instruction generation unit 707 extracts the intermediate code 2 stored in the intermediate code buffer 706. Here, since the register d0 depends on the result of the instruction 1, no instruction is generated at this time.

Next, the machine instruction generation unit 707 extracts the intermediate code 3 stored in the intermediate code buffer 706. At this time, since the intermediate code is for reading the memory, the instruction 3 is generated before the instruction corresponding to the addition of the intermediate code 2 is generated.
And then an instruction 4 corresponding to the addition of the intermediate code 2
Generate However, since it is required to insert two instructions between the instruction 1 and the instruction 4, the no-operation instruction nop
Insert instruction 2 before instruction 3. It is assumed that the variable B is allocated at a position which is four addresses away from the address indicated by the register a0 of the memory.

Next, the machine instruction generation unit 707 extracts the intermediate code 4 stored in the intermediate code buffer 706. Here, since the register d0 depends on the result of the instruction 3, no instruction is generated at this time. . Next, the machine instruction generation unit 707 extracts the intermediate code (not shown) stored in the intermediate code buffer 706. At this time,
Since the intermediate code is for reading the memory, the instruction 5 is generated before generating the instruction corresponding to the addition of the intermediate code 4, and subsequently, the instruction 6 corresponding to the addition of the intermediate code 4 is generated.
At this time, since two instructions have already been inserted between the instruction 3 and the instruction 6, there is no need to newly insert a nop instruction.

The file output unit 709 outputs the machine instruction stored in the output buffer 708 to a file.
Table 3 shows the machine instruction program output to this file.
As shown in the list. The instruction sequence shown in Table 3 is the first
Since the instruction sequence is the same as the instruction sequence shown in the example of the pipeline operation in FIG. Instruction 2 is a non-operation instruction.

As described above, according to the fourth embodiment of the present invention, a machine instruction program including a data prefetch instruction can be generated from a C language program. In this case, the number of instructions between the data prefetch instruction and the instruction using the prefetched data is kept constant. However, the machine executing the machine instruction program sends the data from the memory device 40 by the data prefetch instruction to the machine. Is provided with a data valid flag indicating whether or not the reading of data has been completed, the above-mentioned nop instruction inserted in order to keep the number of instructions between the data prefetch instruction and the instruction using the prefetched data constant. 2 need not be generated.

Further, when generating a machine instruction program, the machine instruction generation unit 707 arranges an instruction for inhibiting interrupt acceptance before a first data prefetch instruction for a group of the program, and An instruction for permitting interrupt acceptance may be arranged after the prefetch instruction. The group of the machine instruction program may be a semantic delimiter such as a subroutine or a module, or a delimiter of a place where the appearance of a data prefetch instruction is higher than others. However, it is assumed that the data prefetch instruction immediately before the instruction that permits the acceptance of the interrupt does not lead to the next data prefetch instruction. By doing so, it is possible to prevent inconsistency in the read data due to an interrupt request generated during the data prefetch instruction. (Fifth Embodiment) As an embodiment of the recording medium of the present invention, a magnetic disk (floppy disk, hard disk, or the like), an optical disk (CD-ROM, PD, or the like) on which the machine instruction program 710 of FIG. There are a magnetic disk and a semiconductor memory (ROM, flash memory, etc.).

[0081]

According to the information processing apparatus of the first aspect,
After reading the data read from the memory device based on the execution of the specific instruction previously decoded by the decoding device from the data holding device, data can be newly read from the memory device. The next instruction can be processed without waiting for the completion of reading the data of
The processing time can be shortened and the processing performance can be improved, which is extremely useful.

According to the information processing apparatus of the second aspect, the same effect as that of the first aspect is obtained. According to the information processing apparatus of the third aspect, the same effects as those of the first or second aspect can be obtained. According to the information processing apparatus of the fourth aspect, in addition to the same effect as the first aspect, processing of the next instruction can be performed without waiting for completion of reading of data from up to n memory devices. The time can be further reduced.

According to the information processing apparatus of the fifth aspect, the same effect as that of the fourth aspect is obtained. According to the information processing apparatus of the sixth aspect, in addition to the same effect as the first aspect, it is possible to prevent reading an erroneous value from the data holding unit before data reading is completed, which is extremely useful. . According to the information processing apparatus of the seventh aspect, the same effect as that of the sixth aspect is obtained.

According to the information processing apparatus of the eighth aspect, in addition to the same effects as those of the sixth and seventh aspects, it is possible to cope with an interrupt request generated after a specific instruction without contradiction. According to the information processing apparatus of claim 9,
This has the same effect as the eighth aspect. According to the information processing apparatus of the tenth aspect, in addition to the same effect as the first aspect, in addition to the data stored in the data holding unit, that is, the data read from the memory device by a specific instruction previously decoded by the decoding unit. By performing an operation using the data obtained, the operation can be performed while reducing the time required for reading data from the memory device, and the processing performance can be improved, which is extremely useful.

According to the information processing apparatus of claim 11,
An effect similar to that of the tenth aspect is obtained. According to the information processing apparatus of the twelfth aspect, the same effect as that of the tenth or eleventh aspect is obtained. According to the information processing apparatus of the thirteenth aspect, it is possible to generate a machine instruction program capable of processing the next machine instruction without waiting for the completion of the first machine instruction. Therefore, processing performance can be improved.

According to the information processing apparatus of claim 14,
This has the same effect as the thirteenth aspect. According to the information processing apparatus of the present invention, it is possible to generate a machine instruction program capable of processing the next n-th machine instruction without waiting for completion of the first to n-th machine instructions. Therefore, processing performance can be improved. According to the information processing apparatus of the sixteenth aspect, the same effect as that of the fifteenth aspect can be obtained.

According to the information processing apparatus of the seventeenth aspect,
The next machine instruction can be processed without waiting for the completion of the first machine instruction, and furthermore, the operation is defined in parallel by the second machine instruction, so that a machine instruction program with high code efficiency can be generated. . According to the information processing apparatus of the eighteenth aspect, the same effect as that of the seventeenth aspect can be obtained. According to the information processing apparatus of claim 19, claim 13, claim 14, claim 1
In addition to the same effect as that of the seventh or the eighteenth aspect, inconsistency of read data due to an interrupt request generated between the first machine instruction and the second machine instruction can be prevented.

According to the recording medium of the twentieth aspect, the first
A machine instruction program capable of processing the next machine instruction without waiting for the completion of the previous machine instruction is recorded. According to the recording medium of the twenty-first aspect, the same effects as those of the twentieth aspect can be obtained.
According to the recording medium of the twenty-second aspect, a machine instruction program capable of processing the next n-th machine instruction without waiting for completion of the first to n-th machine instructions is recorded.

According to the recording medium of the twenty-third aspect, the same effects as those of the twenty-second aspect are obtained. According to the recording medium of the twenty-fourth aspect, the next machine instruction can be processed without waiting for the completion of the first machine instruction, and the operation is defined in parallel by the second machine instruction, thereby improving the code efficiency. High machine instruction program is recorded. According to the recording medium of the twenty-fifth aspect, the same effect as that of the twenty-fourth aspect can be obtained.

According to the recording medium of the twenty-sixth aspect, in addition to the effects similar to the twentieth, twenty-first, twenty-fourth, and twenty-fifth aspects, the recording medium of the first and second machine instructions It is possible to prevent read data from being accompanied by inconsistency due to an interrupt request generated therebetween.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of a pipeline operation of the information processing device according to the first embodiment.

FIG. 3 is an explanatory diagram showing an example of a pipeline operation of the information processing device according to the first embodiment when the reading speed of the memory device is low.

FIG. 4 is a block diagram illustrating a configuration of an information processing apparatus according to a second embodiment.

FIG. 5 is a block diagram illustrating a configuration of an information processing device according to a third embodiment.

FIG. 6 is an explanatory diagram showing an example of a pipeline operation of the information processing device.

FIG. 7 is a block diagram illustrating a configuration of an information processing apparatus according to a fourth embodiment.

FIG. 8 is a block diagram illustrating a configuration of a conventional information processing apparatus.

FIG. 9 is an explanatory diagram showing a pipeline operation of a conventional data processing device.

FIG. 10 is an explanatory diagram showing a pipeline operation of a conventional data processing device when data read by an MOV instruction is used by an immediately following instruction for an operation.

FIG. 11 is an explanatory diagram showing a pipeline operation of the conventional data processing device when the reading speed of the memory device is low.

[Explanation of symbols]

1, 101 Decoder 2, 102 Register file 3, 103 Arithmetic unit 4, 104 Memory control unit 5, 105 Execution control circuit 6 Read data holding circuit 8 Data pre-reading circuit 10, 11, 12, 17, 18, 24, 110, 11
1, 112, 117, 118 Data 15, 16, 115, 116 Address 25 Instruction read control circuit 26 Execution unit 40, 140 Memory device 21, 121 Immediate value 22 Data prefetch signal 23 Data read signal 30 Data valid flag 31 Data valid signal 32 Read completion signal 33 Execution stop request signal 701 C language program 702 Compiler 703 File reading unit 704 Reading buffer 705 Syntax analysis unit 706 Intermediate code buffer 707 Machine instruction generation unit 708 Output buffer 709 File output unit 710 Machine instruction program

Claims (26)

[Claims] 1. Instruction reading means for extracting an instruction from an instruction sequence including a specific instruction instructing at least reading of first data and operation of second data from a memory device, and data read from the memory device And a decoding means for decoding the instruction read by the instruction reading means, and a register, wherein the specific instruction is decoded by the decoding means. In this case, a read address of the first data is calculated, access is started to read the first data from the memory device based on the calculated address, and the second data is read from the data holding unit. Executing means for extracting and storing the data in the register, wherein the second data is read before the specific instruction is decoded. First based on the specific instruction of decoding
An information processing apparatus characterized in that the data is data read as the data. 2. The execution means, which is executed when the access for reading the first data started by a specific instruction is completed, and stores the read first data in the data holding means. 2. The information processing apparatus according to claim 1, wherein said instruction is executed in parallel with execution of an instruction subsequent to said specific instruction. 3. An information processing apparatus comprising: a first stage for reading an instruction; a second stage for decoding an instruction;
A third stage for performing an operation specified by the instruction or calculating an address for accessing the memory device, a fourth stage for accessing the memory device, and a fifth stage for storing a result of the operation specified by the instruction in a register Wherein the instruction reading means operates in the first stage,
The decoding means operates in the second stage, and the execution means operates in the third to fifth stages, and in particular, fetches the second data from the data holding means in the fourth stage. Alternatively, the information processing apparatus according to claim 2. 4. An instruction reading means for extracting an instruction from an instruction sequence including a specific instruction for instructing at least reading of first data from a memory device and operation of second data; First to n-th data holding means for storing at least n pieces of data; decoding means for decoding the instruction read by the instruction reading means; and the specific instruction being placed by the decoding means. A counting means that increments by one each time it is deciphered, and a register that circulates between 1 and n; and a register. Calculating an address for reading the first data, starting access to read the first data from the memory device based on the calculated address, Executing means for taking out the second data from the k-th data holding means determined by the value k indicated by and storing the second data in the register, wherein the second data is n times before the decoded specific instruction. An information processing apparatus characterized in that the information is data read out as first data based on the specific instruction. 5. The execution means is executed when the access for reading the first data started by the specific instruction is completed, and stores the read first data in the k-th data holding means. The information processing apparatus according to claim 4, wherein the operation of performing the instruction is performed in parallel with execution of an instruction subsequent to the specific instruction. 6. An instruction reading means for extracting an instruction from an instruction sequence including a specific instruction for instructing at least reading of first data and operation of second data from a memory device, and data read from the memory device , A data valid flag indicating whether data stored in the data holding unit is valid or invalid, a decoding unit for decoding the instruction read by the instruction reading unit, and a register. When the decoding means decodes that the specific instruction is located, the read address of the first data is calculated, and the first address is read from the memory device based on the calculated address. Access is started to read data, and when the data valid flag indicates valid, the second data is read from the data holding unit. If the data valid flag indicates invalid, wait for the data valid flag to indicate valid, take out the second data from the data holding means, and store the second data in the register. Executing means for performing the first data based on the specific instruction decoded by the decoding means before the specific instruction is decoded.
An information processing apparatus characterized in that the data is data read as the data. 7. The execution means stores the read first data in a data holding means when the read access of the first data started by a specific instruction is completed, and executes the data validity. 7. The information processing apparatus according to claim 6, wherein an operation of validating the flag is performed in parallel with execution of an instruction subsequent to the specific instruction. 8. The decoding means further comprises: when receiving an interrupt request from outside, when the data valid flag indicates valid,
The information processing apparatus according to claim 6, wherein the interrupt request is accepted, and when the data valid flag indicates invalid, the interrupt request is accepted after waiting for the data valid flag to indicate valid. 9. The information processing apparatus according to claim 8, wherein the decoding means saves the data held in the data holding means to a predetermined area of the memory device or another memory device when receiving the interrupt request. 10. An instruction reading means for extracting an instruction from an instruction sequence including a specific instruction for instructing at least reading of first data and operation of second data from a memory device, and data read from the memory device. And a decoding means for decoding the instruction read by the instruction reading means, and a register, wherein the specific instruction is decoded by the decoding means. In this case, a read address of the first data is calculated, access is started to read the first data from the memory device based on the calculated address, and the second data is read from the data holding unit. Executing means for taking out and performing an operation instructed by the instruction and storing the result in the register, wherein the second data is: First the serial particular instruction based on the particular instruction to said decoding means is decrypted before being decrypted
An information processing apparatus characterized in that the data is data read as the data. 11. The execution means, which is executed when the access for reading the first data started by the specific instruction is completed, and stores the read first data in the data holding means. The information processing apparatus according to claim 10, wherein the instruction is executed in parallel with execution of an instruction subsequent to the specific instruction. 12. A first stage for reading an instruction, a second stage for decoding an instruction, a third stage for performing an operation specified by the instruction or an address calculation for accessing a memory device, An information processing apparatus having a pipeline structure including five stages of a fourth stage for accessing a memory device and a fifth stage for storing a result of an operation specified by an instruction in a register, comprising: an instruction reading means. Acts in the first stage,
The decryption means operates in the second stage, and the execution means operates in the third to fifth stages. In particular, the second data is fetched from the data holding means and the operation is performed in the third stage. The information processing device according to claim 10. 13. An information processing apparatus for generating, from a high-level language program, a machine instruction program for a processor performing a pipeline process, reading a variable allocated to a memory device in the high-level language program. Read code detecting means for detecting a code, when the code is detected, calculating an address of the memory device allocated to the variable, and starting a read access of the memory device based on the calculated address. An information processing apparatus comprising: a first machine instruction; and a second machine instruction generating unit configured to generate a second machine instruction for storing data read when the access is completed in a predetermined register. 14. The information processing apparatus according to claim 13, wherein the machine instruction generating means generates the first machine instruction and the second machine instruction by separating them by a fixed number of instructions. 15. An information processing apparatus for generating, from a high-level language program, a machine instruction program for a processor performing a pipeline process, wherein the n high-level language program includes n variables assigned to a memory device. Read code detecting means for detecting a code to be read; and, when the code is detected, calculating respective addresses of the memory device allocated to the n variables, based on the calculated address. The first to n-th machine instructions for starting the read access of the memory device and the first to n-th accesses corresponding to the first to n-th machine instructions are read when the access is completed. (N + 1) -th to (2n) -th machine instructions for storing data in a predetermined register, in order from first to (2n) -th The information processing apparatus that includes a command generating unit. 16. The information processing apparatus according to claim 15, wherein the machine instruction generating means generates the k-th machine instruction and the (k + n) -th machine instruction for k from 1 to n by a fixed number of instructions. . 17. An information processing apparatus for generating, from a high-level language program, a machine instruction program for a processor performing pipeline processing, reading a variable assigned to a memory device in the high-level language program. Read code detecting means for detecting a code, when the code is detected, calculating an address of the memory device allocated to the variable, and starting a read access of the memory device based on the calculated address. Machine instruction generating means for generating a first machine instruction and a second machine instruction to be stored in a predetermined register after performing an appropriate operation on data read when the access is completed An information processing apparatus comprising: 18. The information processing apparatus according to claim 17, wherein the machine instruction generating means generates the first machine instruction and the second machine instruction by separating them by a fixed number of instructions. 19. A machine instruction generating means arranges an instruction for inhibiting interrupt acceptance at a position preceding a first machine instruction in the group of generated machine instruction programs. And generating an instruction that permits interrupt acceptance at a position preceding the last of the second machine instruction in the group. Item 19. The information processing device according to Item 18. 20. A recording medium recording a machine instruction program executed by a processor that performs pipeline processing, wherein the machine instruction program calculates an address of a memory device allocated to a variable, and calculates the calculated address. A first machine instruction for starting a read access to the memory device based on the first and second machine instructions for storing data read in a predetermined register when the access is completed. Recording medium. 21. The recording medium according to claim 20, wherein the first machine instruction and the second machine instruction are arranged apart by a fixed number of instructions. 22. A recording medium recording a machine instruction program executed by a processor that performs pipeline processing, wherein the machine instruction program calculates respective addresses of a memory device allocated to n variables. A first to an n-th machine instruction for starting a read access of the memory device based on the calculated address, and a first to an n-th access corresponding to the first to the n-th machine instruction. A (n + 1) -th to (2n) -th machine instruction for storing data read in a predetermined register when the processing is completed, in the order of first to second n. 23. The recording medium according to claim 22, wherein, for k from 1 to n, a k-th machine instruction and a (k + n) -th machine instruction are spaced apart by a fixed number of instructions. 24. A recording medium recording a machine instruction program executed by a processor performing pipeline processing, wherein the machine instruction program calculates an address of a memory device assigned to a variable, and calculates the calculated address. A first machine instruction for starting a read access of the memory device based on the first and second instructions, and performing a proper operation on the read data when the access is completed, and storing the result in a predetermined register. Recording medium comprising: a second machine instruction. 25. The recording medium according to claim 24, wherein the first machine instruction and the second machine instruction are spaced apart by a fixed number of instructions. 26. An instruction for inhibiting acceptance of an interrupt is arranged at a position preceding a first first machine instruction in the group of machine instruction programs, and the last one of the group of machine instruction programs is arranged in the group. 26. The recording medium according to claim 20, wherein an instruction for permitting interrupt reception is arranged at a position preceding the second machine instruction.