JPH11202971A - Semiconductor integrated circuit - Google Patents

Abstract

(57) Abstract: The present invention provides a semiconductor integrated circuit in which the delay difference between clock signals having different frequencies is reduced and the circuit operation is stabilized without increasing the circuit configuration. As an issue. The present invention provides a variable delay for adjusting a phase difference between a reference clock signal and a clock signal source clock signal of a corresponding clock signal system based on a comparison result of phases between a reference clock signal and a termination clock signal. The circuit 3 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having at least two or more clock signal system circuits having different frequencies.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit operating in synchronization with a clock signal, clock skew in a single clock signal can be sufficiently suppressed by applying a clock tree structure or the like, and a circuit designer is aware of clock skew. Circuit design can be performed without having to do so. In a current semiconductor integrated circuit using a large number of clock signals having different frequencies for reasons such as large scale and low power consumption, a clock divider 102 built in an LSI chip 101 as shown in FIG. Clock signals A, B, C, D having different frequencies generated from the source clock signal S
Are adjusted so as to eliminate clock skew by clock trees 103A, 103B, 103C and 103D respectively corresponding to the respective clock signals, and are supplied to, for example, the synchronous storage element 104 of a circuit group of the corresponding clock signal system. .

However, there is a delay variation among the clock trees 103A, 103B, 103C, and 103D.
It is very difficult to reduce the delay time difference between the respective clock signals A, B, C, D by using A, 103B, 103C, and 103D to a negligible level. further,
If it is not possible to correct the timing violation caused by the delay time difference by changing the layout of the circuit, it is necessary to change the circuit configuration such as the algorithm, which has led to a longer development period of the circuit. On the other hand, if the predicted value of the delay time difference between different types of clock signals is designed to be large in advance in order to avoid such inconveniences, useless insertion of a delay element or high-speed operation of a circuit that is originally slow may be achieved. However, there is a possibility that the number of elements and the power consumption of the entire integrated circuit may increase. Further, there is a possibility that a circuit operation becomes unstable due to a timing violation due to a delay time difference between different types of clock signals caused by process variations, temperature changes, and power supply voltage variations.

To solve such a problem, FIG.
As shown in the figure, the LSI chips 106A mounted on the board 105 and receiving the corresponding clock signals A and B on the board 105 respectively receive the clock signals A and B.
By applying PLLs (phase locked loop circuits) 107A and 107B used to match the phases of the respective clock signals at the end of B, as shown in FIG.
Clock signals A and B having different frequencies generated from the source clock signal S by a clock divider 109 built in the I chip 108, and clock trees 110A and 11 respectively corresponding to the respective clock signals.
The terminal clock signal phase-matched by 0B and P
Although it is conceivable to perform phase adjustment using the LLs 111A and LL, in such a case, for example, a PLL as shown in FIG. 8 is required for each clock signal system, and the phases of the clock signals A and B are adjusted. Divider 10
9 also requires a PLL.

[0005]

As described above,
In a conventional semiconductor integrated circuit using a large number of clock signals having different frequencies, it has been extremely difficult to reduce the delay difference between the clock signals having different frequencies. On the other hand, a method of reducing the delay difference by using a PLL is conceivable. However, such a method requires a large number of PLLs, which may cause a problem such as an increase in the circuit configuration.

Accordingly, the present invention has been made in view of the above, and an object of the present invention is to reduce the delay difference between clock signals having different frequencies without increasing the size of the circuit configuration, and to reduce the circuit operation. To provide a semiconductor integrated circuit with improved stability.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit having at least two or more clock signal system circuits having different frequencies. The clock signal supplied to the clock signal input terminal of the clock signal receiving end which is the terminal of the clock signal of the lowest frequency clock signal in the system is used as a reference clock signal. Receiving the clock signal of the signal supply source and the terminal clock signal fed back from the clock signal input terminal of the corresponding clock signal system, comparing the phases of the reference clock signal and the terminal clock signal, and based on the comparison result The clock signal supply of the clock signal system corresponding to the reference clock signal A variable delay circuit that adjusts the phase difference with the original clock signal is provided at the clock signal supply source of the clock signal system except for the clock signal system of the reference clock signal, so that the circuit configuration can be made larger than when using a PLL. Without inviting, the delay difference between clock signals having different frequencies is reduced, and the circuit operation is stabilized.

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the variable delay circuit includes a phase comparator that receives the reference clock signal and the terminal clock signal and compares the phases of the two signals. A loop filter that generates a control voltage signal corresponding to a phase difference between a reference clock signal and a termination clock signal based on a comparison result of the phase comparator; and a control voltage signal generated by the loop filter and the clock signal supply. A voltage control delay circuit that receives the original clock signal and delay-controls the clock signal supply source clock signal based on the control voltage signal, thereby reducing the size of the circuit configuration as compared with the case where a PLL is used; Features.

According to a third aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, a frequency divider which receives a source clock signal and generates a clock signal of each of the clock signal systems is provided. Features.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

In FIG. 1, an LSI chip 1 of a semiconductor integrated circuit according to this embodiment receives a source clock signal S from the outside and generates four clock signals A, B, C and D having different frequencies. Delay circuits 2 and variable delay circuits (VDL_B, VDL_C, VD) that are provided corresponding to the clock signals B, C, and D generated by the clock frequency divider 2 and adjust the phases of the clock signals B, C, and D, respectively.
L_D,) 3 and the corresponding clock signals B, C, D output from the clock signal A or the variable delay circuit 3, respectively.
Clock tree 4 that adjusts clock skew in response to
And the terminal clock signals (clock signals A ', B', C ', D') of the respective clock trees 4 are received at the clock input terminals to form, for example, the synchronous storage elements 5 constituting the respective clock signal system circuit groups. It is configured with.

The variable delay circuit 3 includes clock signals A, B,
A clock signal A ', which is the terminal clock signal of the clock signal system to which the clock signal A having the lowest frequency is supplied, is used as a reference clock signal. And corresponding clock signals B, C, and D, and clock signals B ', C, which are the end clock signals of the respective clock signal systems.
', D', the phases of the reference clock signal and the terminal clock signal are compared, and based on the comparison result, the phase difference between the reference clock signal and the clock signals B, C, D is adjusted to delay the respective signals. Adjust the difference to a sufficiently small value. Such a variable delay circuit 3 includes an output of the clock divider 2 serving as a clock signal supply source of each clock signal system except for the clock signal system in which the reference clock signal is set, and an input of the corresponding clock tree 4. It is provided between.

The reference clock signal is a signal at the clock input terminals of all the synchronous memory elements 5 driven by the terminal clock signal of the clock tree 4 receiving the clock signal A. That is, since the clock skew of the clock signal A in the clock signal system is adjusted to a sufficiently small value by the corresponding clock tree 4, any one clock signal is used as the reference clock signal. It is enough.
Alternatively, the terminal clock signal of the clock tree 4 of the clock signal system of the clock signal A may be merged into one reference clock signal. On the other hand, as shown in FIG.
B, C, and D may be directly supplied to the LSI chip 1 from the outside.

In such a configuration, clock signals A, B, C, and D generated by dividing the frequency of the source clock signal S by the clock divider 2 and having different frequencies are generated.
Is adjusted to a sufficiently small value by a variable delay circuit 3 provided in each clock signal system except for the clock signal system of the clock signal A serving as a reference clock signal, and the corresponding clock signal It is supplied to the clock input terminal of the synchronous storage element 5 in the circuit group of the system. Thereby, at the stage of designing a semiconductor integrated circuit using a plurality of clock signals having different frequencies, a delay time difference between different types of clock signals can be accurately assumed, and a circuit with optimized clock signal timing can be designed. . In addition, since the difference in delay time between different types of clock signals caused by process variations, temperature changes, and power supply voltage fluctuations is reduced, manufacturing margins can be reduced, yields can be improved, and operating conditions such as temperature and power supply voltage can be used over a wide range. It is possible to guarantee.

Further, as described in the background art, since the operation of the variable delay circuit 3 of this embodiment is limited, the configuration of the variable delay circuit 3 can be reduced to about half that of the PLL. And the variable delay circuit 3 becomes unnecessary for the clock signal system of the reference clock signal, and the number of required variable delay circuits 3 may be (the number of clock signals minus 1). The circuit configuration can be significantly reduced in size as compared with the case of using in a signal system. Further, when it is not necessary to mount the clock divider 2 in the LSI chip 1 as shown in FIG. 2, it is necessary to make the phases of a plurality of different clock signals input to the LSI chip 1 exactly coincide with each other. And the design becomes easier.

FIG. 3 shows the variable delay circuit 3 shown in FIG. 1 or FIG.
3 is a diagram showing a specific circuit configuration of FIG.

In FIG. 3, a variable delay circuit 3 is realized by replacing the VCO of the PLL shown in FIG. 9 with a voltage variable delay circuit (VD), and converts a reference clock signal and a terminal clock signal fed back from the clock tree 4 into a clock signal. And a phase comparator (PD) 6 that compares the two phases and outputs an up signal (UP) or a down signal (DOWN) according to the comparison result, and an up signal or a down signal output from the phase comparator 6. Receiving the signal, perform charging or discharging based on the signal except for the high-frequency components of these signals,
A loop filter (L) that generates a control signal voltage (Vcot) corresponding to the phase difference between the two signals compared by the phase comparator 6
P) 7 and a clock signal corresponding to the clock signals B, C, and D supplied from the clock divider 2 or from the outside and the control voltage signal generated by the loop filter 7, and the clock signal is generated according to the control voltage signal. It is provided with a voltage variable delay circuit (VD) 8 that adjusts the delay time difference between the two signals to a sufficiently small value by adjusting the phase difference between the reference clock signals.

In such a configuration, the phase of the reference clock signal and the terminal clock signal is compared by the phase comparator 6, and when the phase of the terminal clock signal is ahead of the reference clock signal, the down signal is 6 is output to the loop filter 7, and when the phase of the terminal clock signal is behind the reference clock signal, the up signal is output from the phase comparator 6 to the loop filter 7, and when the down signal is output, the loop filter 7 A control voltage signal for delaying the phase of the clock signal by discharging is supplied to the voltage variable control circuit 8, and when an up signal is output, the control voltage signal for charging the loop filter 7 to advance the phase of the clock signal is a voltage. The phase of the clock signal is delayed or advanced by these control voltage signals. , The phase difference between both signals is adjusted.

The voltage variable delay circuit 8 is composed of, for example, MOS transistors as shown in FIG.
Alternatively, as shown in FIG.
And a CMOS inverter 11 connected in cascade to a higher power supply VDD via a P-channel transistor 10 whose control voltage signal is applied to the gate terminal. As described above, since the voltage variable delay circuit 8 can be configured simply and in a small size, the variable delay circuit 3 can be significantly reduced in size as compared with a conventional PLL.

[0021]

As described above, according to the present invention, the delay difference between clock signals having different frequencies can be reduced without increasing the circuit configuration as compared with the case where a PLL is used. Can be improved in stability.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of a variable delay circuit.

FIG. 4 is a diagram showing one configuration of a voltage variable delay circuit.

FIG. 5 is a diagram showing a configuration of a conventional semiconductor integrated circuit using a plurality of clock signals having different frequencies.

6 is a diagram showing a configuration of a conventional semiconductor integrated circuit in which a PLL is used for the circuit shown in FIG. 5;

FIG. 7 shows an example in which a plurality of PLLs are used in the circuit shown in FIG.
FIG. 2 is a diagram illustrating a configuration of a semiconductor integrated circuit formed into a chip.

FIG. 8 is a diagram illustrating a configuration of a PLL.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 LSI chip 2 Clock divider 3 Variable delay circuit 4 Clock tree 5 Synchronous memory element 6 Phase comparator 7 Loop filter 8 Voltage control delay circuit 9, 11, 14, 15 Inverter 10, 12, 13 Transistor

Claims (3)

[Claims] 1. A semiconductor integrated circuit comprising at least two or more clock signal system circuit groups having different frequencies, wherein a clock signal receiving destination which is a terminal of a clock signal of a clock signal system having the lowest frequency in the clock signal system is provided. A clock signal supplied to a clock signal input terminal of the clock signal input terminal of the clock signal supply source in the corresponding clock signal system and the clock signal input terminal of the corresponding clock signal system The phase of the reference clock signal is compared with the phase of the termination clock signal, and based on the comparison result, the reference clock signal and the corresponding clock signal source clock signal supply source clock signal are compared. A variable delay circuit that adjusts the phase difference The semiconductor integrated circuit being characterized in that provided in the clock signal system clock signal source, except for clock signal system click signal. 2. The variable delay circuit according to claim 1, wherein the variable delay circuit receives the reference clock signal and the terminal clock signal, and compares the phases of the two signals; and a reference clock signal based on a comparison result of the phase comparator. A loop filter for generating a control voltage signal according to the phase difference of the terminal clock signal; receiving the control voltage signal generated by the loop filter and the clock signal supplied from the clock signal source; and generating a clock signal based on the control voltage signal. 2. The semiconductor integrated circuit according to claim 1, further comprising a voltage control delay circuit for delay controlling the clock signal of the supply source. 3. The semiconductor integrated circuit according to claim 1, further comprising frequency dividers receiving a source clock signal and generating clock signals of the respective clock signal systems.