JPH11205339A - ATM switch - Google Patents

Abstract

(57) [Problem] To provide an ATM exchange capable of efficiently processing added functions. An ATM switch fabric for switching a cell transmitted via a network to an output destination specified by a header attached to the cell;
And a plurality of PMs 32 for assembling a series of cells sent from the ATM switch fabric 33 into packets and performing predetermined processing. When each of the plurality of PMs 32 is in a busy state, each of the plurality of PMs 32 performs AT
The data is transferred to another PM 32 via the M switch fabric 33.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchro
nous Transfer Mode)

[0002]

2. Description of the Related Art ATM is a technology for communicating voice, video and data on the same network, that is, a technology for realizing a multimedia communication network.

In a network system using this ATM, an ATM exchange (hereinafter, also referred to as an ATM switch) establishes an ATM connection, which is a logical communication path, with the ATM terminal according to a connection request from the ATM terminal. Set. This setting process is called a call process. After the termination of the call processing, the ATM terminal transmits and receives fixed-length data called an ATM cell via the connection.

[0004] Further, the ATM exchange performs switching in accordance with the identification information added to the header of the ATM cell, and distributes the ATM cell to an output destination (destination). In recent ATM exchanges, in addition to this ATM cell switching processing, IP (Internet Protocol) packet routing processing is performed (for example, "I
P-switch ”).

[0005]

The conventional AT
In the M exchange, call processing is performed by a single CPU provided in the ATM exchange. For this reason, when constructing a large-scale network, the load on the CPU becomes excessive and there is a problem in terms of call processing capability.

[0006] In addition to the above-mentioned conventional ATM cell switching processing, an ATM switch that performs an IP packet routing processing uses a hardware switching function to speed up the routing processing. However, it does not have an architecture in which various additional functions such as encryption processing and data compression processing can be installed as needed. For this reason, it is necessary to reconsider the network configuration of the ATM switch and the ATM switching system every time the performance and function are enhanced, and there is a problem in terms of expandability of functions and performance.

[0007] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an ATM exchange capable of efficiently processing added functions.
Another object of the present invention is to provide an ATM switch having excellent expandability of functions and performance.

[0008]

In order to solve the above problems, an ATM switch of the present invention switches a cell transmitted via a network to an output destination specified by a header attached to the cell. And a plurality of packet processing units for assembling a series of cells constituting a packet sent from the ATM switching unit into the packet and performing a predetermined process. When each of the units is in a busy state, the unit does not process a packet composed of a series of cells sent from the ATM switching unit, and transmits the series of cells to another through the ATM switching unit. It is characterized in that it is transferred to a packet processing unit.

According to the present invention, with the above configuration, packet processing is dynamically distributed according to the load situation in each packet processing unit, so that the added functions can be processed efficiently.

[0010] Each of the plurality of packet processing units includes:
A first processor that performs the predetermined processing on the packet,
Measure the number of packets being processed by the first processor,
When the measured value exceeds a prescribed value, a second processor that searches for a packet processing unit in a non-busy state from a table indicating the operation status of other packet processing units, the table, and the first and second processors. At least one memory for storing a program to be executed by the two processors;
When a series of cells constituting a packet sent from the TM switching unit is assembled into the packet and passed to the first processor, and a packet processing unit in a non-busy state is searched by the second processor. A controller for decomposing the assembled packets into cells without passing the cells to the first processor, and transferring these to the retrieved packet processing unit via the ATM switching unit. It may be what you have.

In such a case, it is possible to easily expand functions and performance by changing the program loaded on the memory.

According to another aspect of the present invention, there is provided an ATM switching unit for switching a cell sent via a network to an output destination specified by a header attached to the cell, A plurality of packet processing units provided for each process, assembling a series of cells constituting the packet sent from the switching unit into the packet, and performing one of at least two types of processing; For each of at least two types of processing, a storage device for storing a corresponding program to be executed and a plurality of packet processing units provided for each of the processes, the packet processing unit is A management device that reads a program corresponding to a process to be executed from the storage device and loads the program onto a memory provided in the packet processing unit. And a plurality of packet processing units provided for each of the processes, wherein when the self is in a busy state, there is a non-busy packet processing unit that performs the same processing as the self, the ATM switch unit Without processing the packet composed of a series of cells sent from the, without transferring the series of cells to the packet processing unit, if there is no non-busy packet processing unit to perform the same processing as the self, Notifying the management unit of that fact, the management unit, when receiving the notification from the packet processing unit, reads from the storage device a program corresponding to the process executed by the packet processing unit that has provided the notification, The program is loaded on a memory of a packet processing unit that performs a process different from that of the packet processing unit that sent the notification, and is executed.

According to this aspect, the function (processing to be executed)
Among a plurality of different packet processing units, the function assignment of the packet processing unit can be dynamically changed according to the load of each packet processing unit. Therefore, it is possible to efficiently distribute the load applied to a plurality of packet processing units having different functions.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described.

FIG. 1 is a schematic configuration diagram of an ATM network system to which the first embodiment of the present invention is applied.

As shown in FIG. 1, the ATM network system according to the present embodiment includes a plurality of ATM terminals 1A to 1D.
(Hereinafter simply referred to as ATM terminal 1) are connected to each other by a network 7 via ATM switches 3A and 3B (hereinafter simply referred to as ATM switch 3).

Each of the ATM terminals 1A to 1D has an ATM communication control device 2A to 2D for performing communication by ATM.
(Hereinafter, also simply referred to as the ATM communication control device 2). The ATM communication control device 2 is connected to an ATM switch 3 via a network 7.

In this embodiment, AAL5 (ATM Ad
By converting user data (packets) into ATM cells using a layer called aptation Layer Type 5), AT
Packet communication on M is realized. Where AAL
5 regarding the procedure for converting user data into ATM cells.
A brief description will be given.

FIG. 2 shows A of the user data by AAL5.
FIG. 3 is a diagram for explaining a TM cell conversion procedure. This processing is performed in the ATM communication control device 2.

The AAL5 first receives a CPCS-PDU (Common Part Conv.
ergence Sublayer-Protocol Data Unit), the PAD 43-1 is added to the data 41 (packet) transmitted.
(Padding), LNG43-2 (Length), CRC43
-3 (error correction) and other data (trailer)
ATM frame 43 having a length that is an integral multiple of 48 bytes
Create

Next, the ATM frame 43 is divided every 48 bytes, and a plurality of payloads 44-2 are created.

Next, an ATM cell 44 is created by adding a cell header 44-1 to each of the created payloads 44-2. Then, this is transferred to the ATM switch 3.

Here, the cell header 44-1 has a GFC
(Generic Flow Control) 44-1A, VPI (Virtua
l Path Identifier) 44-1B, VCI (Virtual Chan
(nel Identifier) 44-1C, PT (Payload Type) 4
4-1D, CLP (Cell Loss Priority) 44-1E,
And HEC (Header Error Control) 44-1F. ATM communication control device 2 and ATM switch 3
Is the parameter VPI4 in the ATM cell header 44-1.
The ATM connection is identified by 4-1B and VCI 44-1C.

Next, the ATM switch 3 will be described in detail.

FIG. 3 is a schematic functional block diagram of the ATM switch 3 shown in FIG.

The ATM switch 3, as shown in FIG.
A plurality of line interfaces (LIFs) 31-1 for controlling input / output and transfer of ATM cells via the network 7
31-n (hereinafter, also simply referred to as LIF 31), a plurality of processor modules (PM) 32-1 to 32-n (hereinafter, also simply referred to as PM 32) capable of mounting various additional functions, and between the LIF 31 and PM 32. ATM that exchanges (switches) ATM cells in hardware
The ATM switch 3 includes a switch fabric 33, a management unit 34 that manages the entire ATM switch 3, and a storage device 35 that stores an operation program of the ATM switch 3.

A management terminal 36 is connected to the management unit 34. The management terminal 36 gives a manager's instruction to the management unit 34 or notifies the manager of the operating environment of the ATM switch 3.

A plurality of PMs 32 are provided for each function to be executed, and are configured to dynamically perform load distribution processing between PMs 32 that realize the same function. For example, PM32-1 _{11 to} PM32-
1 _n is provided, and P
M32-2 ₁ ~PM32-2 _n is provided, PM32-3 ₁ ~PM32-3 as PM32-3 performing cryptographic processing
_n (not shown in FIG. 3) is provided, and, PM 32-n ₁ as PM 32-n for performing routing processing
_~PM32-n n is provided. The load balancing process is dynamically performed between the PMs 32 that realize the same function.

It should be noted that the functions realized by the PM 32 described above are merely examples. The function realized by the PM 32 may be determined according to the user's needs, for example, LAN emulation processing.

The LIF 31 stores various PM32s in ATM cells received via the network 7 in the cells.
When processing in -1 to PM 32-n is required, the ATM switch fabric 33 converts the header of the ATM cell so that the ATM cell is switched to the PM 32 to be processed. If the PM 32 does not need to perform the processing, the LIF 31 that is the output destination of the ATM cell is used.
The header of the cell is converted so that the cell is directly switched. This LIF 31 is a header converter (HC) conventionally used in ATM exchanges.
It is basically the same as V).

The operation of the LIF 31 can be controlled by programming the LIF 31 by the management unit 34 or the PM 32.

Next, the PM 32 will be described in detail.

FIG. 4 is a schematic functional block diagram of the PM 32 shown in FIG.

As shown in FIG. 4, the PM 32 includes a main CPU 371 and a main memory 372 connected to a main bus 377, a local CPU 373 and a local memory 374 connected to a local bus 378,
An ATM controller 375 that performs conversion between M cells and packets (user data) and a switch interface (SW-IF) 16 that manages an interface with the switch fabric 33 are provided.

The main CPU 371 includes a main memory 37
2 to perform processing on the packet according to the program loaded on it. The management unit 34 reads out various programs stored in the storage device 35 and transfers each of them to a predetermined PM 32. For example, to transfer the call processing program to PM32-1 ₁ ~PM32-1 _n, and transfers the compressed program PM32-2 ₁ ~PM32-2 _n, and transfers the encrypted program PM32-3 ₁ ~PM32-3 _n and, a routing program PM32-n ₁ ~PM3
2-nn Transfer to _n . In response, the main CPU 37
1 executes the program loaded on the main memory 372. Thereby, it functions as a predetermined functional module.

In the PM 32 of this embodiment, the main CPU 371 is optionally connected to the main bus 377.
Accelerator card 3 that accelerates processing in the
79 can be connected.

The local CPU 373 is the main CPU 3
The CPU 71 monitors the load state and functions as a control CPU for implementing a dynamic load distribution process with another PM 32 that performs the same process on the packet. This is the storage device 3
5 and is executed by executing a predetermined program loaded on the local memory 374 via the management unit 34.

Next, the ATM controller 375 will be described in detail.

The ATM controller 375 has a SW-IF
A series of ATM cells received at 376 are assembled and converted into packets (user data). Then, the packet is transferred to one of the local memory 374 and the main memory 372. Further, a packet is read from the local memory 374 or the main memory 372, divided into ATM cells, and sent to the SW-IF 376.

FIG. 5 is a diagram for explaining a control table required for dividing and assembling cells in the ATM controller 375, and an arrangement location of a transmission / reception buffer.

As shown in FIG. 5, the local memory 374
Includes a division management table 45 that holds information necessary for dividing a packet (user data) into ATM cells;
Each connection (VC) has an assembly management table 47 for holding information necessary for assembling an ATM cell into a packet.

In the division management table 45, information
The transmission buffer pointer 45-1 and the transmission data length 45-
2, a transmission CRC calculation result 45-3, a transmission cell header 45-4, and a transmission buffer type 45-5.

The transmission buffer pointer 45-1 stores data for specifying a storage destination of a packet to be transmitted in a memory specified by a transmission buffer type 45-5 described later. The transmission data length 45-2 stores data for specifying the data length of the packet. The transmission CRC calculation result 45-3 stores an intermediate result of error correction that occurs when a packet is converted into an ATM cell (therefore, the error correction result when the packet is completely converted into an ATM cell is stored). Will be done). Transmission cell header 4
5-4 stores header information attached to each cell when a packet is divided into ATM cells. The transmission buffer type 45-5 indicates the transmission buffer definition destination (the main memory 37).
2. Data for specifying the local memory 374) is stored. The transmission buffer is provided in the main memory 371.
And the local memory 374. In the example shown in FIG. 5, the transmission buffer 46 of the connection VC1 is defined in the local memory 374, and the transmission buffer 12-1 of the connection VC2 is
An example defined on the 71 side is shown.

The ATM controller 375 converts the packet into an ATM cell using the AAL5 according to the information stored in the division management table 45. Then, the ATM cell is transmitted to the ATM switch fabric 33 via the AW-IF 376.

The assembly management table 47 includes, as information, a reception buffer pointer 47-1 and a reception data length 4
7-2, a reception CRC calculation result 47-3, and a reception buffer type 47-4 are stored.

The reception buffer pointer 47-1 stores data for specifying the storage destination of the assembled packet in the memory specified by the reception buffer type 47-4 described later. The reception data length 47-2 stores data for specifying the data length of the packet. Receive CR
The C calculation result 47-3 stores the error correction result of the assembled packet. The reception buffer type 47-4 stores data for specifying the definition destination of the reception buffer (main memory 372, local memory 374). The reception buffer may be defined in any of the main memory 371 and the local memory 374. 5 shows an example in which the reception buffer 48 of the connection VC1 is defined on the local memory 374 side, and the reception buffer 12-2 of the connection VC2 is defined on the main memory 371 side.

The ATM controller 375 assembles the ATM cells into packets according to the information stored in the assembling management table 47. Then, the assembled packet is stored in the reception buffer.

The local memory 374 has a management cell transmission buffer 49A and a management cell reception buffer 49B for realizing local communication between the PMs 32 in addition to the above table.

Next, the operation of the ATM switch 3 having the above configuration will be described.

The ATM switch 3 of the present embodiment dynamically distributes loads such as call processing, encryption processing, and compression processing among a plurality of PMs 32 performing the processing. By doing so, efficient processing is performed.

Here, as an example, an operation when call processing is performed according to the Q.2931 protocol standardized by ITUT, which is a standardization organization, will be described.

FIG. 6 shows Q.29 standardized by ITUT.
It is a figure showing the sequence of the call processing protocol prescribed by 31 protocols.

In FIG. 6, the transmitting side ATM terminal 1
The SET-UP packet 70 is decomposed into ATM cells and sent to the nearest ATM switch 3. LIF31 of the ATM switch 3, the ATM cells received over the network 7, PM 32 performs the call processing (e.g., any of the PM32-1 ₁ ~PM32-1 _{n 1}
The header of the cell is converted so that the cell is switched.

The PM 32 that has received the ATM cell assembles it into a SET-UP packet 70 and sets up a call according to the contents.

For example, in FIG.
If the terminal 1A and the receiving side is the ATM terminal 1B,
The ATM terminal 1A decomposes the SET-UP packet 70 into ATM cells and sends it to the nearest ATM switch 3A.

The ATM switch 3A breaks down the CALL PROCEEDING packet 71 into ATM cells and returns it to the ATM terminal 1A, and breaks down the CONNECT packet 72 into ATM cells and sends it out to the ATM terminal 1B. In response to this, the ATM terminal 1B sets the AT
Connect packet 73 to M switch 3A
Is decomposed into ATM cells and transmitted.

The ATM switch 3A decomposes the CONNECT ACKNOWLEDGE packet 74 to the ATM terminal 1B and returns it to the ATM terminal 1B. Thus, A
A connection is established between the TM terminal 1B and the ATM switch 3A.

The ATM switch 3A decomposes the SET-UP packet 75 into ATM cells and sends them to the ATM terminal 1A. In response, the ATM terminal 1A
Sends CONNECT A to the ATM switch 3A.
The CKNOWLEDGE packet 76 is disassembled into ATM cells and returned. As a result, a connection is established between the ATM terminal 1A and the ATM switch 3.

In the example shown in FIG. 6, a case is described in which a connection is established between the ATM terminals 1 via one ATM switch 3, but a connection is established between the ATM terminals via two or more ATM switches. Is set (for example, in FIG. 1, a connection is set between the ATM terminal 1A and the ATM terminal 1D)
Is the same as the above except that a process of setting a connection between a plurality of ATM switches interposed between the ATM terminals is added.

Next, the operation when the load of the call processing is dynamically distributed among a plurality of PMs 32 will be described.

FIG. 7 is a diagram showing how call processing is dynamically load-balanced among a plurality of PMs 32. Here, 3
One of the shows the configuration for load balancing PM32-1 ₁ ~PM32-1 _3. It should be noted, PM32-1 ₁ ~PM32
-1 _3, in order to notify its own load state to the other PM32 each other, it is assumed that dedicated management connections through the ATM switch fabric 33 is set.

FIG. 8 shows the local memory 37 of each PM 32.
4 provided, (in the case of the example shown in FIG. 7, three PM32-1 ₁ ~PM32-1 ₃₎ PM32 performing call processing is a diagram showing a configuration of a status table 13A indicating the load state of. This status table 13A has the PM number field 1
3A-1 and a status field 13A-2. Each PM 32 can know the load state of the PM 32 (including itself) that performs call processing by referring to the state table 13A.

FIGS. 9 to 11 are flowcharts showing the operation of the local CPU 374. These flows are started by executing a program read from the storage device 35 by the management unit 34 and loaded on the local memory 374.

First, in FIG. 9, the local CPU 37
3 waits for the occurrence of an event, and determines whether or not the occurred event is the reception of the SET-UP packet 70 (step 1001). SET-UP packet 7
If it is the reception of 0, the process moves to the flow shown in FIG.
Otherwise, the process moves to step 1002.

In step 1002, it is determined whether or not the event that has occurred is a call processing completion notification from the main CPU 371. If it is a call processing completion notification from the main CPU 371, the flow shifts to the flow shown in FIG. 11; otherwise, the flow shifts to step 1003.

In step 1003, it is determined whether or not the event that occurred is a dedicated management connection and a status notification change cell received from another PM 32 via the management cell reception buffer. If the cell is a status notification change cell from another PM 32, the status table 13A shown in FIG. 8 stored in the local memory 374 is updated according to the contents of the received cell (step 1004), and thereafter, the process returns to step 1001. Wait for a new event to occur. Otherwise, the process immediately returns to step 1001 and waits for a new event to occur.

In the flow shown in FIG. 10, first, by referring to the state table 13A stored in the local memory 374, the own PM 32 (more specifically, the main C
It is determined whether or not the PU 371) is busy (step 1005).

If not in the busy state, the main C
The PU 371 is notified of the address of the reception buffer storing the SET-UP packet 70 and requests the PU 371 for call processing (step 1006). In response, the main CPU 3
Reference numeral 71 denotes a transmission / reception ATM in the manner shown in FIG.
The connection between the terminals 1 is established.

Next, the local CPU 374 determines whether or not the number of calls being processed by its own main CPU 371 has exceeded a prescribed value (step 1007). Note that the number of call processes in process can be determined based on the number of call processes requested in step 1006 and the number of process completion notifications from the main CPU 371 detected in step 1002. If the number of calls being processed exceeds the specified value, the process proceeds to step 1008. On the other hand, if it does not exceed the specified value, the process returns to step 1001 in FIG. 9 and waits for a new event to occur.

In step 1008, the state table 13
The status of its own PM 32 indicated by A is updated to a busy state. Thereafter, the ATM controller 375 is requested via the management connection to transfer a cell indicating that the own PM 32 is busy to another PM 32 (step 1009). In response to this, ATM
The controller 375 sends a cell indicating that it is busy on the management connection via the management cell transmission buffer 49B of the local memory. Then Figure 9
The process returns to step 1001 to wait for a new event to occur.

On the other hand, if it is determined in step 1005 that the PM 3 is not busy, the other PM 3 that is not busy is referred to by referring to the status table of the local memory 374.
2 is searched (step 1010). If there is a non-busy PM 32 as a result of the search (step 101)
1) Request the ATM controller 375 to transfer the SET-UP packet 70 to the PM 32 (step 1012). In response, the ATM controller 37
5 indicates that the SET-UP packet 70 is a non-busy PM
32. In the example shown in FIG. 7, from PM32-1 ₁ to PM32-1 _3, SET-UP packet 70 indicates a state to be transferred. Note that the transfer of the SET-UP packet 70 is, specifically, the SET-UP packet 70.
Is decomposed into ATM cells, and the header of the cell is exchanged so that the cell is switched to the PM 32 in the non-busy state via the ATM switch fabric 33.

After transferring the SET-UP packet 70 to the PM 32 in the non-busy state, the flow returns to step 1001 in FIG. 9 to wait for a new event to occur.

[0073] search result in step 1010, if there is no PM32 non busy (step 1011), the processing capacity throughout multiple PM32-1 ₁ ~PM32-1 ₃ to perform call processing is insufficient Is notified to the management unit 34 (step 1013). After that, your main C
The PU 371 is notified of the address of the reception buffer storing the SET-UP packet 70 and requests the PU 371 for call processing (step 1014). In response, the main CPU 3
Reference numeral 71 denotes a transmission / reception ATM in the manner shown in FIG.
The connection between the terminals 1 is established.

After requesting the main CPU 371 for call processing, the flow returns to step 1001 in FIG. 9 to wait for a new event to occur.

In the flow shown in FIG. 11, first, it is determined whether or not the number of calls being processed by its own main CPU 371 is equal to or smaller than a specified value (step 1015).

If not, the flow returns to step 1001 in FIG. 9 to wait for a new event to occur.

On the other hand, if it is not more than the specified value, the status of its own PM 32 indicated in the status table 13A is updated to the non-busy status (step 1016). afterwards,
Via the management connection, it requests the ATM controller 375 to transfer a cell indicating that its own PM 32 is not busy to another PM 32 (step 1017). In response, the ATM controller 375
Sends a cell indicating that it is not busy on the management connection via the management cell transmission buffer 49B of the local memory. Next, the local CPU 373
Returns to step 1001 in FIG. 9 and waits for a new event to occur.

Each of the PMs 32 executes the above flow.

In this embodiment, the processing (call processing) to be performed by the ATM switch 3 is performed by distributing the load among a plurality of PMs 32. In addition, it is possible to dynamically perform the processing distribution according to the load situation in each PM 32.
So even if you ’re building a large network,
Processing can be performed efficiently.

In this embodiment, two CPUs are mounted on each PM 32, and the local CPU 374 executes a process for distributing the load between the PMs 32 having the same function. By doing so, the main CPU 11 can concentrate on the original function processing. Therefore, it is possible to configure a high-performance functional module by minimizing the overhead associated with the load distribution control.

Further, in this embodiment, since each PM 32 executes the flow of FIGS. 9 to 11, for example, the LIF
PM3 specified by 31 as an ATM cell as a destination
2 is down, the LI is set so that another PM 32 performing the same processing as the PM 32 is designated as the destination of the ATM cell.
By controlling (programming) F31, it is not necessary to interrupt the processing.

In addition, in this embodiment, the PM 32 realizes various additional functions by executing a program read from the storage device 35 and loaded on the memory. Scalability becomes easy.

In this embodiment, the call processing is performed by a plurality of Ps.
Although the case where the load is distributed by M32 has been described as an example, in the present invention, as described above, various processes such as encryption processing and compression processing can be distributed by a plurality of PM32.

As an example, in FIG.
Compression processing is performed in _{1 ~PM32-2 n,} PM32-3 ₁
When the cryptographic processing is performed in ~PM32-3 _n (not shown in FIG. 3), described load distribution of each processing.

FIG. 12 is a diagram showing how the compression processing and the encryption processing are dynamically load-balanced among a plurality of PMs 32. Here, a plurality of PM32-2 (PM32-2
_{1 ~PM32-2 3)} compression process is load balanced, by a plurality of PM32-3 (PM32-3 ₁ ~PM32-3 _3), shows a configuration in which the encryption process is load balancing.

[0086] It should be noted, PM32-2 ₁ ~PM32-2 ₃ is,
It is assumed that a dedicated management connection has been set up via the ATM switch fabric 33 in order to mutually notify other PMs 32 of their own load status. Similarly, PM32-3 ₁ ~PM32-3 _3, together other PM
It is assumed that a dedicated management connection has been set via the ATM switch fabric 33 in order to notify its own load state to the switch 32.

The LIF 31-1 receives a series of ATM cells making up a packet (user data), and compresses the series of ATM cells.
The header is converted so that it is forwarded to one. Thereby, the series of ATM cells are stored in the ATM switch fabric 3
3 switches to one of the plurality of PMs 32-2.

In response, the plurality of PMs 32-2 perform compression processing while distributing the load in the same manner as in the above-described call processing.

That is, each PM 32-2 has a series of ATs.
When the M cell is received, it is assembled into a packet. Thereafter, if the own device is in a busy state, the assembled packet is decomposed into ATM cells and transferred to another PM 32-2 in a non-busy state. On the other hand, if it is not busy, it compresses the assembled packet and
A plurality of PM32s that decompose into TM cells and perform encryption processing
To one of the two.

In response, the plurality of PMs 32-3 perform the encryption process while distributing the load in the same manner as in the above-described call process.

That is, each PM 32-3 is connected to a series of ATs.
When the M cell is received, it is assembled into a packet. Thereafter, if the self is busy, the assembled packet is decomposed into ATM cells and transferred to another PM 32-3 that is not busy. On the other hand, if it is not busy, it encrypts the assembled packet,
It is decomposed into ATM cells and transmitted to the network 7 via the LIF 31-2.

Now, in FIG. 1, it is assumed that the transmitting side is the ATM terminal 1A and the receiving side is the ATM terminal 1B. In this case, the ATM switch 3A performs the compression and encryption processing of the packet shown in FIG.
By performing the packet decryption / decompression processing in the same manner as the packet compression / encryption processing shown in FIG. 11, it is possible to encrypt user data flowing on the network 7 connecting the ATM switch 3A and the ATM switch 3B.

FIG. 13 is a diagram showing the flow of a packet when the packet compression / encryption process is performed by the ATM switch 3A and the decryption / decompression process is performed by the ATM switch 3B.

In this embodiment, the ATM switch 3A
Can perform the compression process and the encryption process while dynamically distributing the load by using a plurality of prepared PMs 32-2 and PM32-3. ATM switch 3B
Can be used for P and P
In M32-4 and PM32-5, the load can be dynamically distributed. Therefore, each process can be performed efficiently.

The first embodiment of the present invention has been described.

Next, a second embodiment of the present invention will be described.

In the first embodiment described above, the load is dynamically distributed among a plurality of PMs performing the same processing according to the load status of each PM. On the other hand, in the present embodiment, a function to be mounted (specifically, a function to be executed) is performed not only between a plurality of PMs performing the same process but also between PMs performing different processes according to the load status of each PM. A program that dynamically distributes the load by changing the program will be described.

FIG. 14 is a diagram showing how the compression processing and the encryption processing are dynamically load-balanced among a plurality of PMs 32 in the second embodiment of the present invention. Note that the configuration of the ATM switch of the present embodiment is the same as that of the first embodiment shown in FIG. 3, so that the drawing is omitted.

In this embodiment, a plurality of PMs 32-2 for performing the compression process and a plurality of P32s for performing the encryption process shown in FIG.
In the ATM switch 3 equipped with the M32-3, when the processing capability of the plurality of PMs 32-2 is insufficient, at least one of the plurality of PMs 32-3 having a sufficient processing capability.
One of them is modified to perform compression processing.

This is realized by controlling the program executed by the PM 32 in the management unit 34.

FIG. 15 is a flowchart showing the operation of the management unit 34 of this embodiment. Note that the local CPU 3
The operation of 73 is the same as that of the first embodiment of the present invention shown in FIGS.

First, the management unit 34 sets the PM for performing a certain process.
32 (e.g., PM32-2 ₁ ~PM performing compression processing
32-2 _n ), waits for the notification of the processing capacity shortage at step 1013 in FIG. 10 (step 150).
1).

Next, when the notification is received, it is checked whether or not there is a group of PM 32 that performs processing other than the processing performed by the PM 32 that has issued the notification and has a sufficient processing capacity (step 1502). This is one of the groups of the PMs 32 that perform processing other than the processing performed by the PM 32 that has issued the notification (if there is a plurality of processings other than the processing performed by the PM 32 that has issued the notification, , One of the groups of the PMs 32 performing the processing, may be inquired about whether or not there is a PM 32 in the non-busy state in the state table 13A stored in the local memory 374.

When there is a group of PM32s having sufficient processing capacity, at least one PM32 in the non-busy state is selected from the group, and the operation of the PM32 is stopped. Then, the main memory 37 of the PM 32
2, the destination PM3 of the notification received in step 1501
2 is loaded with a processing program (step 15).
03). Thereby, the function of the PM 32 is changed.

For example, the destination of the notification received in step 1501 is the PM 32-2 which performs the compression process, and the P which is determined in step 1502 to have a sufficient processing capacity.
When the group of M32 is the PM32-3 that performs the decoding process, the function of the PM32-31 to PM32-3 that is in the non-busy state is changed to perform the compression process.

[0106] At this time, the management unit 34 (in the above example, PM32-2 ₁ ~PM32-2 _n performs compression processing) PM 32 extension is performed in the processing capability for each, the local memory 374 Control is performed to add the PM 32 whose function has been changed to the stored state table 13A. Also,
(In the above example, PM32-2 ₁ ~PM32-2 _n performs encryption processing) PM32 reduction is carried out in the processing capability for each, in the state table 13A stored in the local memory 374, which is operably changed PM32 Is controlled to be deleted.

On the other hand, in step 1502, if there is no PM32 group with
The occurrence of resource shortage of the PM 32 in the switch 3 is output to the management terminal 36 (step 1504).

In the present embodiment, by executing the above-described flow, each PM3 between a plurality of PMs 32 having different functions is used.
2, the function assignment of the PM 32 can be dynamically changed. Therefore, according to the present embodiment, a plurality of types of functions can be realized while efficiently distributing the loads on the plurality of PMs 32.

According to the present embodiment, a plurality of PM3
2 When the processing capacity is insufficient as a whole, PM3
Since the resource shortage 2 is output to the management terminal 36,
The operator can add the PM 32 efficiently, that is, without waste.

The second embodiment of the present embodiment has been described.

Next, a third embodiment of the present embodiment will be described.

In each of the above embodiments, it is assumed that the ATM switch is configured as one device. This embodiment uses the AT described in each of the above embodiments.
A description will be given of an M switch configured using a network.

FIG. 16 shows a third embodiment A of the present invention.
FIG. 2 is a diagram illustrating a schematic configuration of a TM switch. Here, FIG.
The same components as those of the first embodiment shown in FIG.

In FIG. 16, the packet processing server 50
0-1 to 500-n (also simply referred to as the packet processing server 500) correspond to the PMs 32-1 to PM-1 of the first embodiment shown in FIG.
The management device 520 corresponds to the management unit 34 of the first embodiment. These are composed of information processing devices such as workstations. The front-end switches 530-1 to 530-n correspond to the LIFs 31-1 to 31-n of the first embodiment,
The M switch 533 corresponds to the ATM switch fabric 33 of the first embodiment. These components are LAN
And so on.

FIG. 17 is a diagram showing a schematic configuration of the packet processing server 500.

As shown, the packet processing server 50
0 is an intelligent ATM provided with a local CPU 506 and an ATM controller 504 in an information processing apparatus including a main CPU 501, a main memory 502, and an acceleration card 503 for accelerating processing in the main CPU 501 as necessary. The communication control device 509 is connected and configured.

Here, the main CPU 501, the main memory 502, and the accelerated card 503 are the same as those in FIG.
The main CPU 371 of the PM 32 according to the first embodiment shown in FIG.
Main memory 372 and accelerated card 37
Equivalent to 9. In addition, the AT of the ATM communication control device 509
The M controller 504, the PH-LSI 505, the local CPU 506, and the local memory 507 are the ATM controller 375, the SW-
It corresponds to the IF 376, the local CPU 373, and the local memory 374.

In the present embodiment, an ATM switch is configured by connecting the above-described components via a network. In this way, the processing capability and functions of the ATM switch can be easily expanded. For this reason,
The ATM switch can be configured more efficiently according to the scale of the ATM communication network (specifically, the number of ATM terminals). Particularly, it is optimal as an ATM switch for a large-scale ATM communication network.

[0119]

As described above, according to the present invention,
ATM that can process added functions efficiently
An exchange can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an ATM network system to which a first embodiment of the present invention is applied.

FIG. 2 shows A of user data (packet) by AAL5.
FIG. 3 is a diagram for explaining a TM cell conversion procedure.

FIG. 3 is a schematic functional block diagram of the ATM switch 3 shown in FIG.

FIG. 4 is a schematic functional block diagram of a PM 32 shown in FIG.

FIG. 5 is a diagram for explaining a control table necessary for dividing and assembling cells in an ATM controller 375 shown in FIG. 4, and an arrangement location of a transmission / reception buffer.

FIG. 6 is a diagram showing a sequence of a call processing protocol defined by a Q.2931 protocol standardized by ITUT.

FIG. 7 shows a plurality of Ps in the ATM switch shown in FIG.
FIG. 11 is a diagram illustrating a state in which call processing is dynamically load-balanced between M32s.

FIG. 8 is a diagram showing an example of an ATM switch shown in FIG.
The PM 32 that performs call processing and is provided in the local memory 374 of the second PM (in the case of the example shown in FIG.
_{1 ~PM32-1 3)} status table 13 indicating the load state of the
FIG. 2 is a diagram illustrating a configuration of A.

9 is a flowchart showing an operation of a local CPU 374 in the ATM switch shown in FIG.

10 is a flowchart showing an operation of a local CPU 374 in the ATM switch shown in FIG.

11 is a flowchart showing an operation of a local CPU 374 in the ATM switch shown in FIG.

FIG. 12 is a diagram showing a state where compression processing and encryption processing are dynamically load-balanced among a plurality of PMs 32 in the ATM switch shown in FIG. 3;

FIG. 13 is a block diagram showing a packet compression / encryption process performed by an ATM switch 3A in FIG.
FIG. 4 is a diagram showing a flow of a packet when a decoding / decompression process is performed.

FIG. 14 shows a second embodiment of the present invention.
FIG. 14 is a diagram showing a state where compression processing and encryption processing are dynamically load-balanced among 32.

FIG. 15 is a flowchart illustrating an operation of the management unit according to the second embodiment of the present invention.

FIG. 16 is a diagram showing a schematic configuration of an ATM switch according to a third embodiment of the present invention.

17 is a diagram showing a schematic configuration of a packet processing server 500 shown in FIG.

[Explanation of symbols]

 1A to 1D ATM terminal 2A to 2D ATM communication control device 3A, 3B ATM switch 12-1, 46 Transmission buffer 12-2, 48 Receiving buffer 13A Status table 31-1 to 31-n Line interface (LIF) 32-1 32-n processor module (PM) 33 ATM switch fabric 34 management unit 35 storage device 36 management terminal 45 division management table 47 assembly management table 49A management cell reception buffer 49B management cell transmission buffer 371, 501 main CPU 372, 502 main Memory 373, 506 Local CPU 374, 507 Local memory 375, 504 ATM controller 376 SW-IF 378 Local bus 379, 503 Accelerate card 500-1 to 500-n packet Server 505 PH-LSI 520 management device 530-1 to 530-n front-end switch 533 backbone ATM switch

Claims (13)

[Claims] 1. An ATM exchange, comprising: an ATM switching unit for switching a cell transmitted via a network to an output destination specified by a header attached to the cell; A plurality of packet processing units for assembling a series of cells constituting the received packet into the packet and performing a predetermined process, wherein each of the plurality of packet processing units, when itself is in a busy state, An ATM switch for transferring a series of cells to another packet processing unit via the ATM switching unit without processing a packet composed of a series of cells sent from the ATM switching unit. . 2. The ATM switch according to claim 1, wherein each of the plurality of packet processing units includes a first processor for performing the predetermined processing on a packet, and a number of packets being processed by the first processor. Measure
When the measured value exceeds a specified value, a second processor that searches for a packet processing unit in a non-busy state from a table indicating the operation status of other packet processing units, the table, and the first and second At least one memory for storing a program to be executed by the two processors; and a series of cells constituting a packet transmitted from the ATM switching unit, assembled into the packet and passed to the first processor, If the second processor finds a packet processing unit in a non-busy state, the assembled packets are disassembled into cells without being passed to the first processor,
An ATM switch comprising: a controller configured to transfer the packet to the searched packet processing unit via a TM switching unit. 3. The ATM switch according to claim 2, wherein said second processor is busy when its own packet processing unit exceeds a prescribed number of packets being processed by said first processor. State, and, when the number of packets falls below a specified value, notify the other packet processing units that their own packet processing unit has become non-busy, and An ATM switch for updating the table according to a busy / non-busy state notified from the packet processing unit. 4. The ATM switch according to claim 2, wherein said storage device stores a program to be executed by said first processor, and said storage device is provided in a memory provided in each of said plurality of packet processing units. An ATM switch, further comprising: a management device for loading a program stored in the ATM switch. 5. The ATM switch according to claim 2, wherein the second processor stores a packet in the table when the number of packets being processed by the first processor exceeds a prescribed value. If there is no busy packet processing unit, the ATM switch notifies the outside to that effect. 6. An ATM switch, comprising: an ATM switching unit for switching a cell transmitted via a network to an output destination specified by a header attached to the cell; A plurality of packet processing units provided for each process, which assembles a series of cells constituting the received packet into the packet and performs one of at least two types of processes. Each of the plurality of packet processing units provided in each case, when it is in a busy state, processes the series of cells without processing the packet composed of a series of cells sent from the ATM switching unit. An ATM switch for transferring, via a switching unit, to another packet processing unit that performs the same processing as the ATM switching unit. 7. The ATM switch according to claim 6, wherein each of a plurality of packet processing units provided for each of said processes performs one of said at least two types of processes on a packet. And the number of packets being processed by the first processor,
When the measured value exceeds a prescribed value, the second processor searches for a packet processing unit in a non-busy state from a table indicating the operation status of another packet processing unit that performs the same processing as its own packet processing unit. And at least one memory for storing the table, and a program to be executed by the first and second processors, and assembling a series of cells constituting a packet sent from the ATM switching unit into the packet. Passing the packet to the first processor and, when the second processor finds a packet processing unit in a non-busy state, decomposes the assembled packet into cells without passing the packet to the first processor. These are referred to as A
An ATM switch comprising: a controller configured to transfer the packet to the searched packet processing unit via a TM switching unit. 8. The ATM switch according to claim 7, wherein said second processor is busy when its own packet processing unit exceeds a prescribed number of packets being processed by said first processor. Another packet that performs the same processing as its own packet processing unit, indicating that the packet processing unit has entered the non-busy state when the number of packets has become equal to or less than the specified value. An ATM switch which notifies the processing unit and updates the table according to a busy / non-busy state notified from another packet processing unit which performs the same processing as its own packet processing unit. 9. The ATM switch according to claim 7, wherein said ATM switch is provided for each of said at least two types of processing.
A storage device for storing a program for executing a corresponding process; and a storage device storing, for each of a plurality of packet processing units provided for each of the processes, a program corresponding to a process to be executed by the packet processing unit. And a management device for reading from the memory and loading the data on a memory provided in the packet processing unit. 10. An ATM exchange, comprising: an ATM switching unit for switching a cell transmitted via a network to an output destination specified by a header attached to the cell; A plurality of packet processing units provided for each processing, assembling a series of cells constituting the received packet into the packet, and performing one of at least two types of processing; and the at least two types of processing. Provided for each,
A storage device for storing a corresponding program to be executed, and for each of a plurality of packet processing units provided for each of the processes, a program corresponding to a process to be executed by the packet processing unit is read from the storage device A management device for loading on a memory provided in the packet processing unit, wherein each of the plurality of packet processing units provided for each of the processes performs the same process as itself when the device is in a busy state. If there is a packet processing unit in a non-busy state to perform, the series of cells is transferred to the packet processing unit without processing a packet composed of a series of cells sent from the ATM switch unit. If there is no non-busy packet processing unit that performs the same processing as that described above, the management unit is notified to that effect, and the management unit When receiving the notification, reads a program corresponding to the processing performed by the packet processing unit that the notification from the storage device, the program,
An ATM exchange characterized by being loaded on a memory of a packet processing unit that performs a process different from that of the packet processing unit that sent the notification and executed. 11. The ATM switch according to claim 10, wherein each of a plurality of packet processing units provided for each of said processes performs one of said at least two types of processes on a packet. And the number of packets being processed by the first processor,
When the measured value exceeds a prescribed value, the second processor searches for a packet processing unit in a non-busy state from a table indicating the operation status of another packet processing unit that performs the same processing as its own packet processing unit. And assembling a series of cells constituting the packet sent from the ATM switching unit into the packet and passing the assembled packet to the first processor. When it is determined that the number of packets has exceeded the prescribed value, if a packet processing unit in a non-busy state is detected, the assembled packet is decomposed into cells without passing to the first processor, These are transferred to the detected packet processing unit via the ATM switching unit, and the packet processing unit in the non-busy state If it is not issued, ATM switch, characterized in that it comprises a controller notifies to the management device. 12. The ATM switch according to claim 11, wherein said second processor is busy when its own packet processing unit exceeds a prescribed number of packets being processed by said first processor. The other packet processing units that perform the same processing as the own packet processing unit, indicating that the packet processing unit is in a non-busy state when the number of packets is equal to or less than a prescribed value. And a new program is loaded by the management device,
When the process executed by the first processor is changed, to that effect, the other packet processing unit that performs the process before the change, and the other packet processing unit that performs the process after the change,
Notifying each, and according to the busy / non-busy state notified from another packet processing unit that performs the same processing as its own packet processing unit, and the processing change content notified from the other packet processing unit, An ATM exchange characterized by updating a table. 13. An ATM switch for switching a cell transmitted from an ATM terminal to an output destination specified by a header attached to the cell, and a series of packets constituting the packet transmitted via the ATM switch. A plurality of information processing devices for assembling the cells into the packet and performing a predetermined process; and a network connecting the plurality of information processing devices and the ATM switch. When the self is in a busy state, the series of cells is transferred to another information processing device via the ATM switch without processing a packet composed of a series of cells sent from the ATM switch. AT characterized by doing
M exchange system.