JPH11187006A - Pcm digital communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide PCM digital communication equipment provided with a frame synchronizing circuit with simple configuration capable of remarkably shortening line disconnection time by automatically, speedily and exactly recovering frame synchronism even when the frame synchronism falls into pseudo synchronism. SOLUTION: The detection of a frame alignment signal(FAS) after the establishment of frame synchronism is performed by a frame synchronizing detection circuit 3, the detection of a frame alignment signal bar(FASB) is performed by an FASB detection circuit 5, an alarm is issued by detecting the pseudo synchronism based on the compared result of the detected FAS and FASB, a reset signal generated by a reset signal generating circuit 7 is applied to the frame synchronizing detection circuit 3 based on this alarm and reset and frame synchronism is detected again. Thus, a frame synchronizing circuit is provided for enabling automatic recovery from the above pseudo synchronism.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PCM digital communication device for transmitting a high-speed digital signal to a transmission line and an intra-station device after frame conversion, multiplexing and demultiplexing, and more particularly to an improvement in a frame synchronization circuit.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a configuration example of a frame synchronization circuit of a conventional PCM digital communication apparatus of this kind.
This frame synchronization circuit is a clock extraction tank circuit 1
, An elastic store memory 2, a frame synchronization detection circuit 3, and a multi-frame synchronization detection circuit 4.

The clock extraction tank circuit 1 extracts a clock component from input data a of a transmission line and outputs a transmission line extraction clock b. The clock extraction tank circuit 1 maintains the transmission line extraction clock b by the previously extracted clock component even if the transmission line clock is cut off.

The elastic store memory 2 writes the input data a of the transmission path with the transmission path extraction clock b, reads out the written data by the clock q from the main body of the apparatus, and as data r in the apparatus. Output.

The frame synchronization detection circuit 3 receives the input data a of the transmission path and the transmission path extraction clock b, and inputs FAS (Frame Alinment Signal) and FA of the input data a.
It detects an SB (Frame Alinment Signal Bar) match, establishes frame synchronization, and outputs a frame synchronization establishment signal g.

The multi-frame synchronization detection circuit 4 receives the read data r from the elastic store memory 2, the internal clock q, and the frame synchronization establishment signal g, and reads the data after the frame synchronization is established. -Detecting a match of the MFS of the data r, establishing multi-frame synchronization,
Output a system synchronization establishment signal n.

[0007]

The above-mentioned conventional frame synchronization circuit has the following disadvantages. In the case of a line having a high bit error rate in which fading can occur, such as a micro line, for example, a high error rate line using a 2.048 Mbps PCM digital signal (hereinafter referred to as 2.048 Mbps data). At the time of use, data bits in the frame at the time of synchronization pull-in, a frame synchronization signal, FAS,
If the bit pattern of the FASB matches, a pseudo-synchronization may be established.

FIG. 7 is a diagram showing a frame format of 2.048 Mbps data. As shown in FIG.
The 8 Mbps data is composed of 16 multi-frames, each having a bit length of 256 bits. That is, FAS [10011] which is the specific bit pattern in one frame
011] and FASB [** 0 *****] (* is undefined), and an MFS (Multi Frame Signal) [a
aaa ****] (aaaa is 0000 other frames every 16 frames
The frame has a multi-frame synchronization signal of 8 bits (* is undefined). When synchronizing from the asynchronous state to the synchronous state, first, the frame synchronization pattern
FAS, FASB, FAS
After establishing the system synchronization, the MFS is detected and the synchronization of 16 multiframes is established.

Conventionally, communication using data of 2.048 Mbps having such a frame format has been performed only through a wired line, and an error rate of 10-6 or less is used. Only used for late lines. Error
In some cases, the instantaneously becomes high, but since it does not continue for several tens to several hundreds of milliseconds such as to enter pseudo-synchronization, once synchronization is pulled in, there is no need to detect FASB.

Therefore, as described above, at the time of synchronization pull-in, the data bits in the frame and the frame synchronization signal, F
Even if the bit patterns of AS and FASB match and the pseudo-synchronization has been established, since only the establishment of frame synchronization by the FAS is monitored after the synchronization is established, the multi-frame is accidentally detected. Once the system synchronization is established,
There is no means for restoring the frame synchronization, and it is difficult to recover the frame synchronization except by taking a means such as temporarily disconnecting the line completely.

If the establishment of synchronization between the FAS and the FASB is constantly monitored, the number of data processing steps increases, and the circuit becomes complicated.

An object of the present invention is to automatically and quickly recover frame synchronization even when frame synchronization falls into pseudo synchronization (including erroneous synchronization), greatly reducing the line disconnection time. It is an object of the present invention to provide a PCM digital communication apparatus provided with a frame synchronization circuit having a simple configuration.

[0013]

In order to solve the above-mentioned problems, a PCM digital communication apparatus according to the present invention has the following characteristic configuration. (1) In the PCM digital communication apparatus of the present invention, the FAS after frame synchronization is established is detected by the frame synchronization detection circuit, the FASB is detected by the FASB detection circuit, and the detected FAS is compared with the FASB. Based on the result, a false synchronization is detected and an alarm is issued. Based on the alarm, a reset signal generated by a reset signal generation circuit is applied to the frame synchronization detection circuit for resetting, and the frame synchronization is detected again. And a frame synchronization circuit which enables automatic recovery from the pseudo synchronization.

(2) In the PCM digital communication apparatus according to the present invention, the FA after frame synchronization is established by the frame synchronization detection circuit.
S is detected, FASB is detected by a FASB detection circuit, and the detected FAS is used as a count-up signal.
The detected FASB is counted as a countdown signal by an up / down counter circuit, and when this count value exceeds a certain value, it is determined that an abnormality has occurred, and an alarm signal is output.
The reset signal generated by the reset signal generation circuit based on the alarm signal is given to the frame synchronization detection circuit to reset the frame synchronization detection again, thereby enabling the automatic recovery from the pseudo synchronization. It is characterized by having a frame synchronization circuit that can be used.

(3) The PCM digital communication apparatus of the present invention extracts a clock from transmission line data and outputs a transmission extraction clock, and a transmission line extraction circuit output from the clock extraction tank circuit. The transmission line data is written with a clock, and the written data is written.
An elastic store memory for reading data with a clock from the main unit of the apparatus, the transmission line data and the transmission extraction clock are input, and the FAS of the transmission line data is detected to establish frame synchronization. , And outputs a frame synchronization establishment signal, and generates and outputs a FAS detection signal.
A frame synchronization detection circuit for re-executing a frame synchronization operation in response to an external reset signal, and detecting a match between the MFSs of the data read from the elastic store memory to establish multi-frame synchronization;
A multi-frame synchronization detection circuit for outputting a frame synchronization establishment signal; and inputting the transmission line data, the transmission extraction clock, and the frame synchronization establishment signal to receive the FA of the transmission line data.
The operation mode is set by the FASB detection circuit for detecting the SB and outputting the FASB detection signal, and the frame synchronization establishment signal. The FAS detection signal is used as a count-up signal, and the FASB detection signal is received as a count-down signal. An up / down counter circuit that outputs an alarm signal when the value is other than 0 or 1, and the transmission extraction clock, the multi-frame synchronization establishment signal, and the alarm signal are input, and when multi-frame synchronization is not established or A frame synchronizing circuit comprising a reset signal generating circuit for outputting a reset signal to the frame synchronizing circuit when an alarm signal is output from the up / down counter circuit.

(4) The PCM digital communication apparatus according to the present invention is the apparatus according to the above (3), wherein the frame synchronization detection circuit comprises an 8-bit shift register, an 8-bit comparison circuit,
It is characterized by comprising an M-bit counter circuit, an inverter, an OR gate, an N-bit counter circuit, and a flip-flop.

(5) The PCM digital communication apparatus according to the present invention is the apparatus according to the above (3), wherein the FASB detection circuit comprises an X-bit counter circuit, an inverter, and an OR gate. It is characterized by.

[0018]

(First Embodiment) FIG. 1 shows a frame of a PCM digital communication apparatus according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of the system synchronization circuit, and FIG. 2 is a block diagram showing a more detailed configuration.

This frame synchronization circuit comprises a clock extraction tank circuit 1, an elastic store memory 2,
Multi-frame synchronization detection circuit 3 and multi-frame synchronization detection circuit 4
, An FASB detection circuit 5, an up / down counter circuit 6, and a reset signal generation circuit 7.

Since the clock extraction tank circuit 1 and the elastic store memory 2 have the same functions as those shown in FIG. 6, detailed description will be omitted.

The frame synchronization detection circuit 3 includes an 8-bit shift register 31, an 8-bit comparison circuit 32, an M-bit counter circuit 33, an inverter 34, an OR gate 35, an N-bit counter circuit 36, and a flip-flop 37. Consists of

The multiframe synchronization detecting circuit 4 comprises a 4-bit shift register 41, a 4-bit comparing circuit 42, an L-bit counter circuit 43, a flip-flop 44, an SR latch 45, and an AND gate 46. FASB
The detection circuit 5 includes an X-bit counter circuit 51, an inverter 52, and an OR gate 53. The up / down counter circuit 6 includes an inverter 61, an inverter 62, and an up / down counter circuit 63. The reset signal generation circuit 7 includes an inverter 71, a Y-bit counter circuit 72, a flip-flop 73, and a NOR gate 74.

Next, the function and operation of the frame synchronization circuit having the above configuration will be described with reference to the timing charts of FIGS. 3 is a timing chart showing a normal operation until frame synchronization is established, FIG. 4 is a timing chart showing an operation when frame synchronization is abnormal, and FIG. 5 is a timing chart showing an operation when multi-frame synchronization is abnormal. .

The clock extraction tank circuit 1 extracts a clock component from input data a of the transmission line and outputs a transmission line extraction clock b. The clock extraction tank circuit 1 maintains the transmission line clock b by the previously extracted clock component even if the transmission line clock is cut off.

The elastic store memory 2 writes the input data a of the transmission path with the transmission path extraction clock b, reads out the data written by the internal clock q, and uses this as data r in the apparatus. Output to The frame synchronization detection circuit 3 receives the input data a of the transmission path and the transmission path extraction clock b, detects the coincidence of the FAS of the input data a with the 8-bit comparison circuit 32, and outputs the FAS detection pulse. Generate c.

The M-bit counter circuit 33 inputs the FAS detection pulse c as a load signal, counts two frames (512 bits) until the next FAS detection, and performs FAS.
Outputs a confirmation signal. The OR gate 35 is an inverter 34
, The FAS confirmation signal output from the M-bit counter circuit 33 and the FAS detection pulse c are input,
An S detection signal d is output.

The N-bit counter circuit 36 receives the FASB detection signal e output from the FASB detection circuit 5 as a load signal, and counts one frame (256 bits) to generate a frame synchronization establishment pulse f. Output. The flip-flop 37 receives the FAS detection signal d and the frame synchronization establishment pulse f, and outputs a frame synchronization establishment signal g at the rising edge of the frame synchronization establishment pulse f.

The frame synchronization detection circuit 3 outputs an FAS detection signal d, and uses the reset signal p output from the reset signal generation circuit 7 to generate an M-bit counter circuit 33.
Is reset, and the frame synchronization establishing operation is performed again.

The multi-frame synchronization detecting circuit 4 is configured to execute the MF of the read data r from the elastic store memory 2.
The coincidence of S is detected by a 4-bit shift register 41 and a 4-bit comparison circuit 42, and an MFS detection pulse i is generated.

The L-bit counter circuit 43 inputs the MFS detection pulse i as a load signal, counts 16 frames (4096 bits) until the next MFS detection, and outputs the M signal.
An FS confirmation signal j is output. The flip-flop 44
The MFS confirmation pulse j and the internal clock q are input, retiming is performed, and the MFS detection set signal k and the MFS
And outputs a detection reset signal l.

The SR latch 45 receives the MFS detection set signal k and the MFS detection reset signal 1 and outputs a multiframe synchronization detection signal m. The AND gate 46 receives the multi-frame detection signal m and the frame synchronization establishment signal g and outputs a multi-frame synchronization establishment signal n. F
The ASB detection circuit 5 receives the input data a of the transmission line, the transmission line extraction clock b, and the reset signal p, detects the FASB of the input data a, and outputs the FASB detection signal e. The X-bit counter circuit 51 inputs the FAS detection pulse c as a load signal, counts one frame (256 bits) until the next FASB detection, and outputs a FASB confirmation signal. The OR gate 53 is a FASB output from the X-bit counter circuit 51 via the inverter 52.
The confirmation signal and the transmission line input data a are input, and the FASB detection signal e is output.

The up / down counter circuit 6 outputs a frame synchronization establishment signal g output from the frame synchronization detection circuit 3.
To set the counter to the operation mode. And the frame
The FAS detection signal d output from the system synchronization detection circuit 3 is input as a count-up signal, and the FASB detection signal e output from the FASB detection circuit 5 is input as a count-down signal. When the value is other than 1, an alarm signal h is output.

The reset signal generation circuit 7 receives the transmission line extraction clock b, the multi-frame synchronization establishment signal n output from the multi-frame synchronization detection circuit 4, and the alarm signal h output from the up / down counter circuit 6. When the multi-frame synchronization is not established, or when the up / down counter circuit 6 issues the alarm signal h, the reset signal p is output to the frame synchronization detection circuit 3 and the FASB detection circuit 5.

[0034]

According to the present invention, when frame synchronization falls into pseudo synchronization (including erroneous synchronization), frame synchronization is detected again and automatic recovery from pseudo synchronization can be achieved. Even if the frame synchronization falls into a pseudo synchronization, the frame synchronization is automatically and quickly and accurately recovered, and the frame with a simple configuration that can greatly reduce the line disconnection time.
A PCM digital communication device provided with a system synchronization circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a frame synchronization circuit in a PCM digital communication device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a more detailed configuration of a frame synchronization circuit in the PCM digital communication device according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing a normal operation until the frame synchronization of the frame synchronization circuit in the PCM digital communication device according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the frame synchronization circuit in the PCM digital communication apparatus according to the first embodiment of the present invention when the frame synchronization is abnormal.

FIG. 5 is a timing chart showing an operation of the frame synchronization circuit in the PCM digital communication device according to the first embodiment of the present invention when multi-frame synchronization is abnormal.

FIG. 6 is a diagram showing an example of the configuration of a frame synchronization circuit in a conventional PCM digital communication device.

FIG. 7 is a diagram showing a general 2.048 Mbps data frame format.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 clock extraction tank circuit 2 elastic store memory 3 frame synchronization detection circuit 4 multi-frame synchronization detection circuit 5 FASB detection circuit 6 up / down counter circuit 7 reset signal generation circuit 31 8-bit shift register 32 8-bit comparison circuit 33 M Bit counter circuit 34 Inverter 35 OR gate 36 N-bit counter circuit 37 Flip-flop 41 4-bit shift register 42 4-bit comparison circuit 43 L-bit counter circuit 44 Flip-flop 45 SR latch 46 AND gate 51 X Bit counter circuit 52 Inverter 53 OR gate 61 Inverter 62 Inverter 63 Up / down counter circuit 71 Inverter 72 Y bit counter circuit 73 Flip-flop 74 NOR gate

Claims (5)

[Claims] An FAS after frame synchronization is established is detected by a frame synchronization detection circuit, and an FAS is detected by a FASB detection circuit.
B is detected, a false synchronization is detected based on the result of comparison between the detected FAS and FASB, and an alarm is issued. Based on the alarm, a reset signal generated by a reset signal generation circuit is supplied to the frame synchronization detection circuit. A PCM digital communication apparatus, comprising: a frame synchronization circuit which enables automatic recovery from the pseudo synchronization by resetting and resetting the frame synchronization again. 2. An FAS after frame synchronization is established is detected by a frame synchronization detection circuit, and the FAS is detected by a FASB detection circuit.
B is detected, the detected FAS is used as a count-up signal, and the detected FASB is counted as a count-down signal by an up / down counter circuit. When the count value exceeds a certain value, it is determined that an abnormality has occurred and an alarm signal is generated. Then, a reset signal generated by a reset signal generation circuit based on the alarm signal is given to the frame synchronization detection circuit to be reset, and the frame synchronization is detected again. PCM characterized by comprising a frame synchronization circuit enabling recovery
Digital communication device. 3. A clock extraction tank circuit for extracting a clock from transmission line data and outputting a transmission extraction clock, and writing the transmission line data with the transmission line extraction clock output from the clock extraction tank circuit. An elastic store memory for reading out the written data with a clock from the apparatus main unit; and inputting the transmission path data and the transmission extraction clock.
A frame synchronization is established by detecting the FAS coincidence of the transmission line data, a frame synchronization establishment signal is output, and an FAS detection signal is generated and output. A frame synchronization detection circuit for re-establishing the establishment operation; a multi-frame synchronization circuit for detecting a match between the MFSs of the data read from the elastic store memory to establish multi-frame synchronization and outputting a multi-frame synchronization establishment signal. A synchronization detection circuit, the transmission line data, the transmission extraction clock, and the frame.
Input the system synchronization establishment signal and
And an operation mode is set by the frame synchronization establishment signal and a FASB detection circuit that outputs a FASB detection signal.
The FAS detection signal is used as a count-up signal.
Accepting the ASB detection signal as a countdown signal,
An up / down counter circuit that outputs an alarm signal when the count value is other than 0 or 1, and the transmission extraction clock, the multi-frame synchronization establishment signal, and the alarm signal are input, and when multi-frame synchronization is not established, or A reset signal generation circuit for outputting a reset signal to the frame synchronization circuit when an alarm signal is output from the up / down counter circuit; and a frame synchronization circuit comprising: P
CM digital communication device. 4. A frame synchronization detection circuit comprising: an 8-bit shift register, an 8-bit comparison circuit, an M-bit counter circuit,
2. The PCM digital communication device according to claim 1, wherein the PCM digital communication device comprises an inverter, an OR gate, an N-bit counter circuit, and a flip-flop. 5. The PCM digital communication apparatus according to claim 1, wherein said FASB detection circuit comprises an X-bit counter circuit, an inverter, and an OR gate.