JPH11177892A - Solid-state imaging device for motion detection - Google Patents

Abstract

(57) Abstract: The present invention relates to a solid-state imaging device for motion detection that performs motion detection based on a difference between frames, and does not require an external image comparison process for motion detection, and erroneously detects motion. It is intended to reduce SOLUTION: A plurality of light receiving units, a plurality of vertical read lines provided for each column of the plurality of light receiving units, and a specific row of the plurality of light receiving units are sequentially selected and held from the light receiving units of the specific row. A vertical transfer circuit that sequentially outputs the pixel output of the previous frame and the pixel output of the current frame newly held from the light receiving unit of the specific row to the vertical read line, and is time-divisionally transferred via the vertical read line. A comparison circuit that compares the pixel output of the previous frame with the pixel output of the current frame; a horizontal transfer circuit that horizontally transfers the comparison result of the comparison circuit; and a logic that reduces an isolated region of a logic change with respect to the comparison result of the comparison circuit. A solid-state imaging device for motion detection, comprising: a logic operation circuit that executes an operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a solid-state imaging device for motion detection for detecting a difference between frames. In particular, the present invention relates to a solid state imaging device for motion detection, which eliminates the need for an external processing circuit for motion detection, and reduces erroneous motion detection due to minute background motion or noise.

[0002]

2. Description of the Related Art Conventionally, there has been known a motion detection image processing apparatus which sequentially captures image data via a solid-state imaging device and performs motion detection based on a difference between frames of the image data. FIG. 9 is a diagram illustrating a motion detection image processing apparatus 100 of this type.

In FIG. 9, an image processing apparatus 1 for motion detection
Reference numeral 00 denotes a solid-state imaging device 101, an AD conversion circuit 102 that converts an image signal (analog signal) from the solid-state imaging device 101 into a digital signal, and an image memory (first memory) that stores the digital signal from the AD conversion circuit 102. Image memory) 103 and image memory (second image memory) 104
And an image processing circuit 105 for comparing digital image data stored in the image memories 103 and 104 with each other to detect a motion.

In the motion detection image processing apparatus 100 having such a configuration, first, the first
The image signal (analog signal) of the frame is converted to an AD conversion circuit 1
After being converted into a digital signal at 02, it is stored in the first image memory 103. Next, in a second frame subsequent to the first frame (the immediately preceding frame), after the image signal (analog signal) obtained by the solid-state imaging device 101 is converted into a digital signal by the AD conversion circuit 102, 2 is stored in the second image memory 104.

The image processing circuit 105 converts the digital signal stored in the first image memory 103 and the digital signal stored in the second image memory 104 into
Compare in pixel units. At this time, pixels that differ by a predetermined threshold or more are detected, and a signal indicating detection of a moving object (hereinafter, referred to as a “moving object signal”) is generated. Such comparison between frames makes it possible to detect the motion of the subject.

[0006]

However, in the conventional motion detection image processing apparatus 100, the peripheral circuit of the solid-state imaging device 101 is complicated, and the motion detection image processing apparatus
There is a problem that the whole 00 becomes large and expensive. The image signal output from the solid-state imaging device 101 is an analog signal.
It is supplied to the conversion circuit 102. Therefore, the transmission path of the analog signal is routed, and there is a problem that the transmission path is easily affected by ambient noise.

Further, in the conventional motion detection image processing apparatus 100, the dynamic range of the image signal (analog signal) is limited by the AD conversion circuit 102. Normal,
The input dynamic range of the AD conversion circuit 102 is smaller than the dynamic range of the solid-state imaging device 101. Therefore, there is a problem that the wide dynamic range of the solid-state imaging device 101 cannot be effectively used in the process of detecting the moving object.

Further, there is a possibility that the sampling timing in the AD conversion circuit 102 is slightly shifted between the previous frame and the current frame. As described above, when the sampling timing is shifted between the frames, a slight shift occurs in the pixel positions to be compared in the external image processing circuit 105. If such a shift occurs, a difference between frames occurs at an edge portion or the like even in a stationary body. For this reason, a problem occurs in that the accuracy and reliability of moving object detection are reduced.

In order to avoid the above-mentioned problems, a memory for storing the image signals of the immediately preceding frame and the current frame is provided for each pixel of the solid-state imaging device 101, and the image signal stored in this memory is further provided. May be provided for each pixel to generate a moving object signal for each pixel. However, in such a measure, the structure of the unit pixel becomes complicated, and the solid-state imaging device 101
However, there arises a problem that the aperture ratio is lowered and the resolution is lowered. Furthermore, in the above measures, since only a moving object signal is output from each pixel, there is a problem that an image signal to be originally output in the solid-state imaging device cannot be obtained at the same time.

It is generally known that a solid-state imaging device including a semiconductor device generates shot noise due to fluctuations of electric charge. The magnitude of such shot noise is proportional to the square root of the magnitude of the signal. Therefore, as the field becomes brighter and the signal level increases, the shot noise increases. As a result, in a bright place, a large amount of shot noise appears in the difference between frames. If the shot noise included in the difference between the frames exceeds the threshold value for moving object discrimination, erroneous motion detection is performed.

In order to avoid such erroneous detection due to shot noise, it is conceivable to set the comparison threshold value of the difference between frames uniformly high. However, such a measure has a problem that sufficient motion cannot be detected for a low-contrast subject. In addition to the cases described above, for example, when the leaves of trees sway due to the wind, a difference between frames occurs. Such a movement is a minute movement of the background portion, and it is preferable that the movement can be distinguished from the movement of the detection target to be monitored.

Therefore, the present invention according to any one of the first to tenth aspects provides a motion detection method which does not require an external image comparison process for motion detection and does not detect shot noise or minute motion of a background portion. It is an object to provide a solid-state imaging device. In particular, an object of the present invention is to provide a motion detection solid-state imaging device capable of simultaneously outputting a moving object signal and an image signal.

[0013] Further, the invention according to claim 3 is based on claim 2.
It is another object of the present invention to provide a motion detection solid-state imaging device that selectively reduces erroneous motion detection due to shot noise.

Still another object of the present invention is to provide a solid-state imaging device for motion detection that reduces erroneous motion detection in the horizontal direction of the screen. Claim 5
An object of the invention described in (1) is to provide a motion detection solid-state imaging device that reduces erroneous detection of motion in the vertical direction of the screen. Still another object of the present invention is to provide a solid-state imaging device for motion detection that reduces erroneous motion detection in the time axis direction.

[0015]

According to a first aspect of the present invention, a plurality of light receiving units arranged in a matrix and generating a pixel output corresponding to incident light, and a plurality of light receiving units are provided. While sequentially selecting a plurality of vertical read lines provided for each column and a plurality of specific rows of the light receiving sections, the pixel outputs of the previous frame held in the past from the light receiving sections of the specific rows, and the light receiving sections of the specific rows A vertical transfer circuit for sequentially outputting the newly held pixel output of the current frame to the vertical readout line, and a pixel output of the previous frame provided for each vertical readout line and transferred in a time division manner via the vertical readout line A comparison circuit that compares the pixel output of the current frame with the pixel output of the current frame, a horizontal transfer circuit that horizontally transfers the comparison result of the comparison circuit output for each vertical read line, and an isolated region of a logical change with respect to the comparison result of the comparison circuit. Logic performance to reduce And a logic operation circuit for executing, constitute a motion detection for a solid-state imaging device.

In the solid-state imaging device for motion detection having such a configuration, the "electric signal of the previous frame" and the "electric signal of the current frame" are displayed on the vertical readout line by the operation of the vertical transfer circuit.
Are output in a time-divisional manner on a line-by-line basis. The comparison circuit captures the “electric signal of the previous frame” and the “electric signal of the current frame” output in a time-sharing manner as described above, and compares them. The horizontal transfer circuit horizontally transfers the comparison result.

The logical operation circuit calculates the comparison result
A logical operation for reducing an isolated region of a logical change is executed. Generally, the difference between frames caused by shot noise, minute movement of the background, and the like occurs randomly and instantaneously. Therefore, most of such noise components are, in the comparison result between frames, isolated regions of logical change (in many cases,
(Isolated point).

On the other hand, the detection target has a certain area on the screen and moves collectively. Therefore, such a motion of the detection target appears as a band-like region along the edge portion in the comparison result between frames. Therefore, the above-described logical operation circuit executes a logical operation for reducing an isolated region of a logical change, whereby it is possible to efficiently reduce erroneous detection of motion caused by shot noise and minute motion of the background. .

Although the expression "frame" is used in the description of claim 1, this means an image for one frame in the present application. Therefore, the solid-state imaging device for motion detection according to claim 1 need not be limited to a device that performs progressive scanning, and may be one that performs, for example, interlaced scanning. In such interlaced scanning, motion detection is performed based on the difference between the current field and the previous field before the current field.

According to a second aspect of the present invention, in the solid-state imaging device for motion detection according to the first aspect, the pixel output of the previous frame or the current pixel output transferred in a time division manner via the vertical readout line is provided. An image signal output circuit for selectively taking in one of the pixel outputs of the frame and performing horizontal transfer is provided.

In such a configuration, it is possible to output the image signal of the current frame or the previous frame by selectively outputting one of the pixel outputs transferred on the vertical readout line in a time-division manner. .

In particular, the output operation of such an image signal is as follows.
Since the operation is performed without occupying the vertical read line, the operation on the motion detection side is not hindered. Therefore, it is possible to simultaneously output the moving object signal and the image signal. According to a third aspect of the present invention, in the solid-state imaging device for motion detection according to the second aspect, a level determination circuit that determines a level of an image signal output from the image signal output circuit, and a level determination circuit And an output switching circuit for switching and outputting the output of the logical operation circuit and the comparison result of the comparison circuit in accordance with the result of the determination.

By the way, since shot noise is generated in proportion to the square root of the signal level, it appears intensively in the high luminance portion of the image signal. Therefore, the level determination circuit determines whether the image signal exceeds a predetermined level,
It is possible to specify a region containing a lot of shot noise. Therefore, for example, in the output switching circuit, the output of the logical operation circuit may be selectively output when the image signal exceeds a predetermined level, and the comparison result of the comparison circuit may be output when the image signal falls below the predetermined level. In such a switching operation, erroneous detection of motion due to shot noise can be selectively and reliably reduced. Further, in an area with a small shot noise, an isolated area is not unnecessarily removed, and a small detection target motion can be reliably detected.

Conversely, when the signal level is extremely low, random noise generated from a circuit system or the like becomes dominant (especially when a peak AGC circuit or the like is interposed in the circuit, the signal level decreases. Random noise is amplified and appears greatly). Therefore, for example, in the output switching circuit, when the image signal falls below a predetermined level, the output of the logic operation circuit is selectively output, and when the image signal exceeds the predetermined level,
The comparison result of the comparison circuit may be output. In such a switching operation, erroneous detection of motion due to random noise can be selectively and reliably reduced. In addition, in a region where the signal level is large and the random noise is small, the isolated region is not removed unnecessarily, and the motion of a small detection target can be reliably detected.

As in the above-described example, by performing the output switching between the "output of the logical operation circuit" and the "comparison result of the comparison circuit" in accordance with the determination result of the level determination circuit, the movement due to noise or the like is performed. It is possible to detect a small motion of a small detection target as much as possible while selectively reducing detection errors. According to a fourth aspect of the present invention, in the solid-state imaging device for motion detection according to any one of the first to third aspects, the logical operation circuit horizontally transfers the comparison result. It is characterized by having a bit memory circuit that stores data for each pixel and a horizontal AND circuit that performs a logical AND operation between the storage contents of the bit memory circuit and the comparison result.

According to a fifth aspect of the present invention, in the solid-state imaging device for motion detection according to any one of the first to third aspects, the logical operation circuit determines the comparison result as 1 It is characterized by having a line memory circuit for storing for each line, and a vertical AND circuit for performing a logical AND operation between the storage contents of the line memory circuit and the comparison result.

According to a sixth aspect of the present invention, in the solid-state imaging device for motion detection according to any one of the first to third aspects, the logical operation circuit determines the comparison result as 1 It is characterized by having a frame memory circuit for storing for each screen, and a time axis AND circuit for performing an AND operation between the storage contents of the frame memory circuit and the comparison result.

According to a seventh aspect of the present invention, in the solid-state imaging device for motion detection according to any one of the first to sixth aspects, the vertical transfer circuit is provided for each light receiving section. A pixel output holding unit that holds the pixel output from the light receiving unit and outputs the held pixel output in a non-destructive manner, and is provided for each pixel output holding unit, and includes an output stage and a vertical readout line of the pixel output holding unit. A connection / separation unit for connecting / disconnecting the pixel output, and a pixel output of the previous frame previously held in the pixel output holding unit of the specific row is output to the vertical readout line via the connection / separation unit, and then the light receiving unit is connected to the pixel output holding unit Vertical transfer control means for newly holding the pixel output of the current frame and outputting the held pixel output of the current frame to the vertical readout line via the connection / separation unit.

(Eighth Aspect) According to the eighth aspect, in the solid-state imaging device for motion detection according to the seventh aspect, the pixel output holding unit has a control area for holding a pixel output. An amplification element that outputs a pixel output corresponding to the pixel output held in the region, a transfer circuit that transfers the pixel output generated by the light receiving unit to a control region of the amplification device, and a pixel that is accumulated in the control region of the amplification device A reset circuit for resetting an output.

According to a ninth aspect of the present invention, in the solid-state imaging device for motion detection according to the eighth aspect, the amplifying element is a junction-type field effect transistor and is transferred via a transfer circuit. The pixel output is stored directly in the gate region of the junction field effect transistor.

According to a tenth aspect of the present invention, in the solid state imaging device for motion detection according to any one of the first to ninth aspects, the comparison circuit includes a pixel output of the current frame and a pixel output of the current frame. The circuit is characterized in that it is a circuit that determines whether or not the pixel output of the previous frame matches within an allowable range, and outputs a binary signal according to the determination result.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) The first embodiment is directed to Claims 1, 2, and 3.
It is an embodiment corresponding to the invention described in 4, 7 to 10.

FIG. 1 is a diagram showing a circuit configuration of the first embodiment. In FIG. 1, a solid state imaging device 10 for motion detection
, The unit pixels 1 are arranged in a matrix of n rows and m columns. The outputs of these unit pixels 1 are commonly connected for each vertical column, and form m vertical read lines 2. Also,
The vertical scanning circuit 3 for determining the timing of vertical transfer is arranged in the solid-state imaging device 10 for motion detection. The vertical scanning circuit 3 supplies three types of control pulses φTG1, φPX1, and φRG1 to the unit pixels 1 in the first row. Similarly, three types of control pulses φTG2 to n, φPX2 to n, and φRG2 to 3 are output from the vertical scanning circuit 3 for the unit pixels 1 in the remaining 2nd to nth rows.
n are supplied respectively.

A current source 4 for supplying a bias current, a difference processing circuit 5 (correlated double sampling circuit), and a different value detection circuit 6 are connected to the m vertical read lines 2 respectively. Is done. A control pulse φV is commonly supplied to the sample control terminals of these m difference processing circuits 5. Note that such a control pulse φV is output from, for example, the vertical scanning circuit 3 or the like. All the output terminals of the m difference processing circuits 5 are commonly connected to form a horizontal readout line 7 for image signals. The image signal output on the horizontal read line 7 is output to the outside of the motion detection solid-state imaging device 10 via the video amplifier circuit 7a and the like.

The horizontal read line 7 is connected to a reset MOS switch QRSH. These MOs
The control pulse φRSH for reset is supplied to the gate of the S switch QRSH. Such a control pulse φR
SH is output from, for example, the horizontal scanning circuit 8 or the like. Further, the solid-state imaging device for motion detection 10 is provided with a horizontal scanning circuit 8 for determining the timing of horizontal transfer.
The horizontal scanning circuit 8 supplies a control pulse φH1 to the scanning control terminal of the difference processing circuit 5 in the first column. Similarly, the control pulses φH2 to φHm output from the horizontal scanning circuit 8 are supplied to the scanning control terminals of the remaining difference processing circuits 5 in the second to mth columns, respectively.

On the other hand, two types of control pulses φSA and φSB are commonly supplied to the sample control terminals of the m different value detection circuits 6. Such control pulses φSA and φSB are output from, for example, the vertical scanning circuit 3 or the like. The output terminals Q1 to Qm of the m different value detection circuits 6 are connected to the parallel inputs of the shift register 9, respectively. The shift register 9 is supplied with a control pulse φLD for determining the timing for taking in parallel data and a transfer clock φCK for serial transfer. These pulses φ
LD and φCK are supplied from, for example, the horizontal scanning circuit 8 or the like. The serial output of the shift register 9 is supplied to a data input of a D flip-flop 9a and one input of an AND circuit 9b.

The clock input to the D flip-flop 9a also receives the transfer clock φ supplied to the shift register 9.
CK is also given. D flip-flop 9
The output Q of a is supplied to the other input of the AND circuit 9b. The output of the AND circuit 9b is output to the outside of the solid-state imaging device 10 for motion detection as a moving object signal. (Circuit Configuration of Unit Pixel 1) Next, a specific circuit configuration and connection relationship of the unit pixel 1 located in the first row and the first column will be described with reference to FIG. Note that the other unit pixels 1 also differ only in the subscript of the control pulse.
The circuit configuration is the same as that of the unit pixel 1 in the first row and first column.

First, a photodiode PD is arranged in the unit pixel 1. The anode of the photodiode PD is connected to the gate of an amplifying element QA composed of a junction field effect transistor via a charge transfer MOS switch QT. The control pulse φTG1 output from the vertical scanning circuit 3 is supplied to the gate of the charge transfer MOS switch QT.

The gate of the amplifying element QA is connected to a wiring layer maintained at a constant reset potential VRD via a MOS switch QP for resetting signal charges. This M
The control pulse φRG1 output from the vertical scanning circuit 3 is supplied to the gate of the OS switch QP. On the other hand, the source of the amplification element QA is connected to the vertical read line 2 via the vertical transfer MOS switch QX. This MO
The control pulse φPX1 output from the vertical scanning circuit 3 is supplied to the gate of the S switch QX.

(Circuit Configuration of Difference Processing Circuit 5) Next, FIG.
The specific circuit configuration of the difference processing circuit 5 provided in the vertical readout line 2 in the first column will be described based on FIG.
The circuit configuration of the difference processing circuits 5 in the second and subsequent columns is the same as that of the difference processing circuits 5 in the first column, except that the subscripts of the control pulses are partially different.

First, one end of a capacitor CV for holding a dark signal is connected to the vertical read line 2. The other end of the capacitor CV has a MOS switch QV for applying a constant potential such as a ground potential, and an M switch for horizontal transfer.
OS switch QH is connected. The other side of the MOS switch QH is connected to the horizontal read line 7. Here, the control pulse φV is applied to the gate of the MOS switch QV.
Is supplied. A control pulse φH1 output from the horizontal scanning circuit 8 is connected to the gate of the MOS switch QH.

(Circuit Configuration of Outlier Detection Circuit 6) Next, FIG.
The specific circuit configuration of the outlier detection circuit 6 provided in the first column of the vertical readout line 2 will be described based on FIG.
The outlier detection circuits 6 in the second and subsequent columns have the same circuit configuration as the outlier detection circuits 6 in the first column, except for the subscripts of the output signals.

First, one ends of two capacitors CCA and CCB are connected to the vertical read line 2. The other end of the capacitor CCA is connected to NAN via three inverters INV1, INV3, and INV5 in series.
Connected to one input terminal of D circuit NA. Further, a voltage VR1 (= VT−Vt) for determining a threshold is connected to the other end of the capacitor CCA via a MOS switch QB1.
h) is supplied. The control pulse φSA is supplied to the gate of the MOS switch QB1. Further, the other end of the capacitor CCA is connected to the output of the inverter INV3 via the MOS switch QB3 which interrupts the positive feedback loop. The control pulse φSB is supplied to the gate of the MOS switch QB3.

On the other hand, the other end of the capacitor CCB is connected to the NAN via two inverters INV2 and INV4 in series.
Connected to the other input terminal of D circuit NA. A voltage VR2 (= VT + Vt) for determining a threshold value is provided on the other end side of the capacitor CCB via a MOS switch QB2.
h) is supplied. Note that the voltage VT here is a value corresponding to the threshold voltage of the inverters INV1 and INV2. The voltage Vth is a threshold value for determining whether or not the difference between frames is significant.

The control pulse φSA is supplied to the gate of the MOS switch QB2. Furthermore, the capacitor CC
The other end of B is connected to the output of the inverter INV4 via the MOS switch QB4 that interrupts the positive feedback loop. The control pulse φSB is supplied to the gate of the MOS switch QB4. The output of the NAND circuit NA is supplied to the parallel input terminal Q1 of the shift register 9.

(Correspondence between the present invention and the first embodiment)
Here, the correspondence between the present invention and the first embodiment will be described. First, regarding the correspondence between the first and tenth aspects of the present invention and the first embodiment, the light receiving section corresponds to the photodiode PD, and the vertical read line corresponds to the vertical read line 2.
The vertical transfer circuit is composed of a vertical scanning circuit 3, an amplifying element QA, a vertical transfer MOS switch QX, a charge transfer MOS switch QT, and a signal charge reset MOS switch.
The switch circuit corresponds to the switch QP, the comparison circuit corresponds to the different value detection circuit 6, the horizontal transfer circuit corresponds to the shift register 9, and the logical operation circuit corresponds to the D flip-flop 9a and the AND circuit 9b.

As for the correspondence between the second embodiment and the first embodiment, the image signal output circuit corresponds to the difference processing circuit 5, the horizontal readout line 7, and the horizontal scanning circuit 8. Regarding the correspondence between the invention described in claim 4 and the first embodiment, the bit memory circuit corresponds to the D flip-flop 9a, and the horizontal AND circuit corresponds to the AND circuit 9b.

The correspondence between the invention described in claim 7 and the first embodiment is as follows.
A, the MOS switch QT and the MOS switch QP, the connection / separation unit corresponds to the MOS switch QX for vertical transfer, and the vertical transfer control means outputs the pixel output for two frames of the vertical scanning circuit 3 in units of rows. Function to read in divisions ".

Regarding the correspondence between the inventions according to the eighth and ninth aspects and the first embodiment, the amplifying element corresponds to the amplifying element QA, the transfer circuit corresponds to the MOS switch QT, and the reset circuit corresponds to the MOS switch QT. Corresponds to QP. (Operation of the First Embodiment) FIG. 3 is a diagram showing the drive timing of the vertical transfer in the first embodiment. In addition,
This figure shows the i-th vertical transfer.

The operation of the first embodiment will be described below with reference to FIG. First, at the timing of the period t10 shown in FIG. 3, the control pulse φSB falls to a low level. As a result, MOS switch QB in outlier detection circuit 6
3 and QB4 are cut off, and the other ends of the capacitors CCA and CCB are set in a floating state.

Next, at the timing of the period t11 shown in FIG. 3, the control pulse φPXi is held at a low level,
Further, the control pulse φSA is raised to a high level. The fall of the control pulse φPXi causes the MOS in the i-th row
Switch QX conducts. At this time, the signal charge accumulated at the time of reading the previous frame is held in the gate region of the amplification element QA. Therefore, the amplification element QA
Outputs the pixel output Vold of the previous frame and the i-th row onto the vertical readout line 2.

On the other hand, on the side of the different value detection circuit 6, the rise of the control pulse φSA causes the MOS switches QB1, QB
2 conducts. As a result, a charging path passing through the capacitors CCA and CCB is temporarily formed. As a result, a voltage of (Vold-VT + Vth) is charged at both ends of the capacitor CCA.

On the other hand, (V
old-VT-Vth). This period t
Immediately before the end of 11, the control pulse φSA falls. Therefore, the other ends of the capacitors CCA and CCB enter a floating state again. As a result, the above voltage is held as the voltage between both ends of the capacitors CCA and CCB.

Next, at the timing of the period t12 shown in FIG. 3, the control pulse φRGi falls to a low level. Then, in the unit pixel 1 in the i-th row, the MOS switch QP is turned on, and the signal charges of the previous frame held in the gate region of the amplification element QA are discharged. As a result, the gate region is initialized to the reset voltage VRD via the wiring layer.

Immediately before the end of the period t12, the control pulse φ
RGi is returned to a high level. As a result, the MOS switch QP is shut off, and the gate region of the amplifier element QA holds the voltage at the time of reset, while remaining in a floating state.
In the subsequent period t13, the control pulse φ
PXi is still maintained at a low level. Therefore, the dark signal Vd is output to the vertical read line 2 via the source follower circuit of the amplification element QA. This dark signal Vd is a reset noise (so-called kTC noise) during a reset operation.
And a signal including a voltage variation between the gate and the source of the amplifier element QA, which is a main cause of the fixed pattern noise.

On the other hand, in this period t13, the control pulse φV rises to a high level. Difference processing circuit 5
On the side, the rise of the control pulse φV turns on the MOS switch QV. As a result, a charging path passing through the capacitor CV is formed, and the dark signal Vd in the i-th row is charged in the capacitor CV in the difference processing circuit 5. This period t1
Just before the end of 3, the control pulse φV falls. Therefore, one end of the capacitor CV is again in a floating state, and the dark signal Vd in the i-th row is held as a voltage across the capacitor CV group.

Next, at the timing of the period t14 shown in FIG. 3, the control pulse φTGi falls to a low level. Then, in the unit pixel 1 in the i-th row, the MOS
The switch QT is turned on, and the signal charges of the current frame accumulated in the photodiode PD in the i-th row are transferred to the gate region of the amplification element QA. Just before the end of this period t14, the control pulse φTGi is returned to the high level. as a result,
The MOS switch QT is shut off, and the gate region of the amplifier element QA keeps the floating state, with the potential increased in accordance with the transferred signal charge.

At the timing of the subsequent period t15,
Control pulse φPXi is still at the low level. Therefore, the pixel output Vno of the i-th row in the current frame is output from the vertical read line 2 through the source follower circuit of the amplification element QA.
w is newly output. In this period t15, a difference voltage obtained by subtracting the dark signal Vd of the i-th row from the pixel output Vnow of the i-th row in the current frame appears at one end of the capacitor CV of the difference processing circuit 5 side. This difference voltage is the “pixel output of the current frame” from which the dark signal component has been removed.

On the other hand, during this period t15, the other end of the capacitor CCA on the different value detection circuit 6 side has (Vno
w−Vold + VT−Vth) appears. The other end of the capacitor CCB has (Vnow−Vold + V
(T + Vth). These voltages are inverted at the threshold voltage VT via the inverters INV1 and INV2.

According to the voltage relationship described above, when the pixel output difference (Vnow-Vold) between frames exceeds Vth, the inverter INV1 outputs a low level. On the other hand, when the pixel output difference (Vnow-Vold) between frames is lower than Vth, the inverter INV1 outputs a high level. The pixel output difference (Vnow−Vold) between frames is (−V
When th) is exceeded, the inverter INV2 outputs a low level. On the other hand, the pixel output difference between frames (Vnow-Vo
When (ld) falls below (−Vth), the inverter INV2 outputs a high level.

These logic outputs are supplied to the inverter INV3
After passing through ５5, they are respectively input to the NAND circuit NA. As a result, from the NAND circuit NA, the value of the pixel output difference (Vnow−Vold) between the frames is (−Vth) to Vt.
If it is within the allowable range of h, a low level is output.
When the value of the pixel output difference (Vnow−Vold) between frames is outside the allowable range of (−Vth) to Vth, a high level is output. With such an operation, the output of the NAND circuit NA becomes a binary signal indicating whether or not the pixel output between frames matches within an allowable range.

In the state of the period t15, the control pulse φLD rises to a high level. As a result, the binarized signals output from the m NAND circuits NA are fetched collectively from the parallel input terminals Q1 to Qm of the shift register 9, and the internal value D1 of the shift register 9 is read.
ＤDm.

Next, at the timing of the period t16,
By raising control pulse φSB, MOS switches QB3 and QB4 become conductive. As a result, the capacitors CCA and CCB via the inverters INV3 and INV4.
Is recharged in the positive feedback direction, and the output of the NAND circuit NA is stabilized. FIG. 4 is a diagram showing the drive timing of the horizontal transfer in the period t16.

First, at the timing of the period t16,
The horizontal scanning circuit 8 sequentially sets the control pulses φH1 to φHm to the high level instead of the control pulses φH1 to φHm. Therefore, one end of the capacitor CV for m columns is connected to the horizontal read line 7 in the order of 1 to m columns. As a result, on the horizontal readout line 7, the image signals of the current frame and the i-th row (A1 to A1 in FIG. 4)
A5) are sequentially output.

Note that while the control pulses φH1 to φHm are set to the high level, φRSH is temporarily set to the high level. By such an operation, the residual charges on the horizontal read line 7 are discharged every time via the MOS switch QRSH. Therefore, there is no possibility that the residual charges are mixed with the image signal horizontally transferred. On the other hand, at the timing of this period t16, the transfer pulse φC
K are sequentially provided. The internal values D1 to Dm are serially output from the serial output of the shift register 9 in synchronization with the falling of the transfer pulse φCK.

The serial outputs D1 to Dm are delayed by one pixel (one clock) via the D flip-flop 9a. The AND circuit 9b outputs the serial outputs D1 to D1.
A logical product is obtained between Dm and the serial outputs D1 to Dm after the delay, and is output to the outside as a moving object signal. The above-described series of processing for the i-th row is sequentially repeated for the other horizontal rows, so that the image signal of the current frame is sequentially output from the horizontal readout line 7, and the output signal V0 is output for one frame. Are sequentially output.

According to the operation described above, in the first embodiment, the outlier detection circuit 6 compares the pixel output of two frames time-divisionally output to the vertical read line 2 to detect the motion of the detection target. It becomes possible to detect. Therefore, there is no need to provide any peripheral circuits such as an AD conversion circuit, an image memory, and an image processing circuit outside the solid-state imaging device in order to perform motion detection. As a result, it is possible to configure all devices such as a monitoring device and an image compression circuit that require motion detection at a small size and at low cost.

In the first embodiment, a moving object signal is generated without passing through an AD conversion circuit. Therefore, the dynamic range is not limited by the AD conversion circuit, and motion detection can be performed using the wide dynamic range of the solid-state imaging device itself. In the first embodiment, the pixel output of the previous frame and the pixel output of the current frame are compared inside the solid-state imaging device without any phase shift of the pixel position. Therefore, compared to the case where the difference between frames is obtained by an external circuit, there is no problem that the edge portion of the image is erroneously detected as a motion.

In the first embodiment, an image signal can be output by selectively outputting the “pixel output of the current frame” which is time-divisionally output on the vertical readout line 2. Such simultaneous output of a moving object signal and an image signal is very suitable for use in detecting motion while observing (recording) an image, such as a monitoring device. Further, in the first embodiment, the vertical readout line 2 is efficiently used, and in addition to the pixel output for two frames, a dark signal is output in a time sharing manner. The difference processing circuit 5 can obtain a high quality pixel output from which the dark signal has been removed based on the dark signal.

In particular, in the first embodiment, a logical operation circuit including a D flip-flop 9a and an AND circuit 9b is used to output only one pixel in the horizontal direction of the screen from the serial outputs D1 to Dm. Delete the isolated point. Therefore, it is possible to efficiently reduce erroneous motion detection caused by shot noise and minute motion of the background. In the first embodiment, the D flip-flop 9
Although a is arranged and the logical product operation of the moving object signal is executed between two pixels adjacent in the horizontal direction, the present invention is not limited to this. For example, two or more bit memories (e.g., flip-flop circuits) may be arranged in series, and an AND operation of each output of these bit memories and the serial output of the shift register 9 may be performed. In such a configuration, a logical product operation can be performed in a wide range, so that errors in motion detection can be more reliably reduced.

Next, another embodiment will be described. (Second Embodiment) The second embodiment is defined by claims 1 to 5,
It is an embodiment corresponding to the inventions described in 7 to 10. FIG.
FIG. 3 is a diagram illustrating a circuit configuration according to a second embodiment.

The structural features of the second embodiment are as follows. First, the horizontal readout line 7 is provided with a video amplifier 7a. The image signal output from the video amplifier 7a is output to the outside and supplied to the positive input of the comparator 21. The comparator 21 determines a threshold value of the level of the image signal and outputs a binarized level determination signal AL.

The level determination signal AL is delayed by one horizontal pixel via the D flip-flop 23a,
The inverting input of the AND circuit 23 and the first input of the AND circuit 24
And are supplied to the respective inputs. On the other hand, the serial output of the shift register 9 is supplied to the “data input of the D flip-flop 22”, the “second input of the AND circuit 24”, and the “serial input of the shift register 25”.

The data output of the D flip-flop 22 includes “an input on the non-inverting side of the AND circuit 23” and “AN
The third input of the D circuit 24 is supplied to each of them. Further, a serial output of the shift register 25 is supplied to a fourth input of the AND circuit 24 and a data input of the D flip-flop 26, respectively. The data output of the D flip-flop 26 is supplied to a fifth input of the AND circuit 24.

Further, the output of the AND circuit 23 and
The output of the AND circuit 24 is input to the OR circuit 27. The output of the OR circuit 27 is output to the outside as a moving object signal. The other components are the same as those of the first embodiment (FIG. 1).
The same reference numerals are given to FIG. 5 and the description is omitted here.

(Correspondence between the present invention and the second embodiment)
Here, regarding the correspondence between the first and tenth aspects of the present invention and the second embodiment, the light receiving portion is a photodiode PD.
, The vertical readout line corresponds to the vertical readout line 2, and the vertical transfer circuit is “vertical scan circuit 3, amplifying element QA,
MOS switch QX for vertical transfer, MOS for charge transfer
Switch QT and MOS switch QP for resetting signal charges ", the comparison circuit corresponds to the different value detection circuit 6, the horizontal transfer circuit corresponds to the shift register 9, and the logic operation circuit corresponds to D flip-flops 22, 23a,. 26, AN
It corresponds to the D circuit 24 and the shift register 25.

As for the correspondence between the invention described in claim 2 and the second embodiment, the image signal output circuit includes the difference processing circuit 5, the horizontal readout line 7, and the horizontal scanning circuit 8, “the image signal of the current frame”. Function to selectively transfer data horizontally. " Regarding the correspondence between the invention described in claim 3 and the second embodiment, the level discriminating circuit includes a comparator 21.
, And the output switching circuit corresponds to the AND circuits 23 and 24 and the OR circuit 27.

As for the correspondence between the invention described in claim 4 and the second embodiment, the bit memory circuit corresponds to the D flip-flops 22 and 26, and the horizontal AND circuit corresponds to the AND circuit.
It corresponds to the circuit 24. Regarding the correspondence between the invention described in claim 5 and the second embodiment, the line memory circuit corresponds to the shift register 25, and the vertical AND circuit corresponds to the AND circuit 24.

The correspondence between the invention described in claim 7 and the second embodiment is as follows.
A, the MOS switch QT and the MOS switch QP, the connection / separation unit corresponds to the vertical transfer MOS switch QX, and the vertical transfer control means reads the pixel output of two frames of the vertical scanning circuit 3 in a time-division manner. Function ". Regarding the correspondence between the inventions according to claims 8 and 9 and the second embodiment, the amplifying element corresponds to the amplifying element QA,
The transfer circuit corresponds to the MOS switch QT, and the reset circuit corresponds to the MOS switch QP.

(Operation of Second Embodiment) Next, the operation at the time of horizontal transfer in the second embodiment will be described. Note that the operation at the time of vertical transfer in the second embodiment is the same as that of the first embodiment.
Since this embodiment is the same as the embodiment (FIG. 3), the description is omitted here. FIG. 6 is a diagram showing the drive timing at the time of the horizontal transfer in the period t16.

First, at the timing of the period t16,
The horizontal scanning circuit 8 sequentially sets the control pulses φH1 to φHm to the high level instead of the control pulses φH1 to φHm. Therefore, one end of the capacitor CV for m columns is connected to the horizontal read line 7 in the order of 1 to m columns. As a result, on the horizontal readout line 7, the image signals of the current frame and the i-th row (A1 to A1 in FIG. 6)
A5, A11 to A15, etc.) are sequentially output.

The comparator 21 determines the level of the image signal as a threshold value and outputs a level determination signal AL. This level discrimination signal AL is a binary signal indicating a high level in a high luminance portion of the image signal. On the other hand, at the timing of this period t16, the transfer pulse φCK is sequentially applied to the shift register 9 and the shift register 25. In synchronization with the falling of the transfer pulse φCK, the serial value output from the shift register 9 outputs
Are output serially as comparison results D1a to Dma between frames.

The comparison results D1a to Dma between the frames
Are passed through the shift register 25 and are delayed by one vertical line. As a result, from the serial output of the shift register 25, the comparison result D delayed by one vertical line
1b to Dmb are sequentially output. The above comparison result D1
a to Dma are delayed by one pixel (one clock) via the D flip-flop 22.

The comparison results D1b to Dmb delayed by one vertical line are further delayed by one pixel (one clock) via the D flip-flop 26. As a result, the four input terminals of the AND circuit 24
The comparison result between frames is (vertical 2 pixels x horizontal 2 pixels)
Only the minutes are input simultaneously. On the other hand, the AND circuit 23
Input terminal on the non-inverting side of
The pixels D1a to Dma are input with a delay of one horizontal pixel.

The remaining input terminals of these AND circuits 23 and 24 receive the level determination signals AL in opposite phases. Therefore, according to the logical value of the level determination signal AL,
The following output switching is performed. (1) First, in the high-luminance portion of the image signal (when the level discrimination signal AL delayed by one pixel in the horizontal direction is at the high level), the result of comparison between frames is ANDed for each (2 vertical pixels × 2 horizontal pixels). The result is output from the OR circuit 27. As a result, from the comparison result between the frames, an isolated region in which even one pixel is at a low level in any of the horizontal, vertical, and oblique directions is removed.

(2) In a portion other than the high luminance portion of the image signal (when the level discrimination signal AL delayed by one horizontal pixel is at a low level), the comparison result between frames is represented by the D flip-flop 2
2 and output from the OR circuit 27 via the AND circuit 23 in a state delayed by one horizontal pixel. Such a delay operation is a compensation operation for matching the phase with the pixel position in the output on the AND circuit 24 side. This delay operation makes it possible to make joints of moving object signals less noticeable due to output switching.

According to the above operation, in the second embodiment, an isolated area in which only one pixel has a high level in any of the horizontal, vertical, and oblique directions is excluded from the comparison results between frames. Is done. As a result, it is possible to efficiently reduce the isolated region caused by the shot noise. Further, in the second embodiment, the above-described isolated region removal is executed only for a high-luminance portion of an image signal. In particular, such a high-luminance portion of an image signal is a portion where shot noise is intensively generated. Therefore, by removing the isolated region limited to such a high-luminance portion, it is possible to efficiently reduce the isolated region caused by the shot noise.

On the other hand, for the portions other than the high-luminance portion of the image signal, the comparison result between frames is output via the AND circuit 23 in a state delayed by one horizontal pixel. Therefore, there is no possibility of removing an isolated area which is originally irrelevant to shot noise. As a result, it is possible to more reliably detect the movement of a small detection target. In the second embodiment, the shift register 25 (a type of line memory circuit)
Are arranged to execute a logical product operation of a moving object signal between two pixels adjacent in the vertical direction, but the present invention is not limited to this. For example, two or more line memory circuits (such as shift registers) may be arranged vertically, and an AND operation may be performed between each output of these line memory circuits and the serial output of the shift register 9. In such a configuration, the logical product operation can be performed over a wider range, so that errors in motion detection can be more reliably reduced.

In the second embodiment, the AND operation of the moving object signal is executed only on the high luminance side of the image signal. However, the present invention is not limited to this. For example, an AND operation of a moving object signal may be executed on the low luminance side of the image signal. With such a configuration, it is possible to selectively reduce motion detection errors due to random noise. Next, another embodiment will be described.

(Third Embodiment) The third embodiment is an embodiment corresponding to the first, second and sixth to tenth aspects of the present invention. FIG. 7 is a diagram illustrating a circuit configuration according to the third embodiment. The features of the configuration according to the third embodiment are as follows.

First, the serial output of the shift register 9 is supplied to "one input of the AND circuit 33" and "data input of the frame memory 34", respectively. The data output of the frame memory 34 is supplied to the other input of the AND circuit 33. The output of the AND circuit 33 is output to the outside as a moving object signal.

[0092] Regarding other components, the first
Since the configuration requirements are the same as those of the embodiment (FIG. 1), the same reference numerals are given to FIG. 7 and the description is omitted here. (Correspondence relationship between the present invention and the third embodiment) Here, regarding the correspondence relationship between the inventions according to the first and tenth aspects and the third embodiment, the light receiving section corresponds to the photodiode PD, and the vertical readout is performed. The line corresponds to the vertical readout line 2, and the vertical transfer circuit is “vertical scanning circuit 3, amplifying element QA,
The OS switch QX, the charge transfer MOS switch QT, and the signal charge reset MOS switch QP, the comparison circuit corresponds to the different value detection circuit 6, the horizontal transfer circuit corresponds to the shift register 9, and the logical operation is performed. The circuit corresponds to the frame memory 34 and the AND circuit 33.

As for the correspondence between the invention described in claim 2 and the third embodiment, the image signal output circuit includes the difference processing circuit 5, the horizontal readout line 7, and the horizontal scanning circuit 8 which are connected to the image signal of the current frame. Function to selectively transfer data horizontally. " Regarding the correspondence between the invention described in claim 6 and the third embodiment, the frame memory circuit corresponds to the frame memory 34, and the time axis AND circuit corresponds to the AND circuit 33.

As for the correspondence between the invention described in claim 7 and the third embodiment, the pixel output holding section includes an amplifying element Q
A, the MOS switch QT and the MOS switch QP, the connection / separation unit corresponds to the vertical transfer MOS switch QX, and the vertical transfer control means reads the pixel output of two frames of the vertical scanning circuit 3 in a time-division manner. Function ". Regarding the correspondence between the inventions according to claims 8 and 9 and the third embodiment, the amplifying element corresponds to the amplifying element QA,
The transfer circuit corresponds to the MOS switch QT, and the reset circuit corresponds to the MOS switch QP.

(Operation of Third Embodiment) Next, the operation at the time of horizontal transfer in the third embodiment will be described. Note that the operation at the time of vertical transfer in the third embodiment is the same as that of the first embodiment.
Since this embodiment is the same as the embodiment (FIG. 3), the description is omitted here. FIG. 8 is a diagram showing the drive timing at the time of the horizontal transfer in the period t16.

First, at the timing of the period t16,
Transfer pulse φCK is sequentially applied to shift register 9. In synchronization with the falling of the transfer pulse φCK, the serial value output from the shift register 9 outputs
, The comparison results D1α to Dmα between the frames are sequentially output (such as D1α to D5α shown in FIG. 8). The comparison result between the frames is stored in the frame memory 3
4 is delayed by one frame. as a result,
From the data output of the frame memory 34, comparison results delayed by one frame are sequentially output (such as D1β to D5β shown in FIG. 8).

The AND circuit 33 takes a logical product of these comparison results and outputs the result as a moving object signal to the outside. By the operation described above, the frame memory 34 and the AN
The logical operation circuit including the D circuit 33 can eliminate an isolated point in which only one pixel has a high level in the time axis direction in the comparison result between frames. Therefore, it is possible to reduce erroneous detection of movement due to shot noise or minute movement of the background.

In the first to third embodiments described above,
Although a junction field-effect transistor is used as the amplifying element QA, the present invention is not particularly limited to this configuration.
Generally, an element having an amplifying function can be used as the amplifying element QA. For example, a MOS transistor, a bipolar transistor, or the like may be used as the amplifying element QA, or a functional element using a mixture of these elements may be used. Further, signal charges may be held in parasitic capacitances generated at the gates and bases of these amplifying elements, or capacitors and the like for holding signal charges may be provided at the gates and bases of these amplifying elements in an auxiliary manner. Good.

Further, in the first to third embodiments, the vertical transfer MOS switch Q is used as the connection / separation unit.
Although X is provided, it is not limited to this. For example, even if a capacitor for accumulating signal charges is provided at the gate or base of the amplification element, and the voltage at the other end of the capacitor is increased or decreased, the connection / disconnection between the amplification element and the vertical read line may be controlled. Good.

In the first to third embodiments described above,
Although the case where the signal charge generated in the photodiode PD is directly transferred to the control region of the amplifying element has been described, the present invention is not limited to this. For example, the signal charge may be temporarily transferred to the diffusion region and held, and then the potential of the diffusion region may be detected at the gate of the MOS transistor via the signal line. As an example of such a pixel, for example, a document “Acti
ve Pixel Sensors: AreCCD's Dinosaurs? '', Fossum E.
R., Proceeding of SPIE: Charge-Coupled Device and S
olid State Optical Sensors III, Vol. 1900, pp2-14 (199
There is one described in 3).

In the first to third embodiments described above,
The logical AND operation in the spatial direction or the time axis direction is performed on the moving object signal, but the present invention is not limited to this. In general, an operation for reducing a non-correlated noise component on a moving object signal may be performed. For example, a majority operation may be executed instead of the AND operation. Furthermore, in the first embodiment described above, the case where the unit pixels 1 are arranged in a two-dimensional matrix has been described. However, the present invention is also applicable to a line image sensor or the like arranged in a one-dimensional matrix. Of course, the same can be applied.

Further, in the above-described embodiment, the circuit configuration based on the positive logic is described, but the present invention is not limited to this configuration. Of course, part or all of the above-described circuit configuration may be a circuit configuration based on negative logic.

[0103]

According to the first aspect of the present invention, the "pixel output of the previous frame" and the "pixel output of the current frame" are output on the vertical read line in a time-division manner. . By comparing these pixel outputs, motion detection can be realized inside the solid-state imaging device.

Therefore, it is not necessary to particularly provide peripheral circuits such as an AD conversion circuit, an image memory, and an image processing circuit outside the solid-state imaging device, and the entire device can be reduced in size and cost. Further, according to the first aspect of the present invention, it is not necessary to route an image signal, which is an analog signal, to an external AD conversion circuit or the like, and there is little possibility of being affected by ambient noise.

Further, according to the first aspect of the present invention, an AD conversion circuit which is conventionally required outside the solid-state imaging device for motion detection becomes unnecessary. As a result, the dynamic range is not limited by the AD conversion circuit, and the motion can be detected in a wide dynamic range of the solid-state imaging device itself. According to the first aspect of the present invention, the pixel output of the previous frame and the pixel output of the current frame are directly compared for each vertical read line. Therefore, compared to a case where a difference between frames is obtained through AD conversion or the like, there is no displacement at the pixel positions to be compared. Therefore, there is very little possibility that a difference between frames occurs at an edge portion of the stationary body, and the motion can be detected with higher accuracy.

In addition, according to the first aspect of the present invention, a logical operation is performed on a comparison result of the comparison circuit to reduce an isolated region of a logical change. Therefore, in the solid-state imaging device, isolated regions due to shot noise and minute movement of the background are reduced, and it is possible to appropriately suppress unnecessary movement detection due to these. (Claim 2) In the invention according to claim 2, an image signal of a current frame or a previous frame is output by selectively outputting one of pixel outputs transferred on a vertical read line in a time-division manner. be able to.

In particular, such an image signal output operation is as follows.
Since the operation is performed without occupying the vertical read line, the operation on the motion detection side is not hindered. Therefore, in the motion detection solid-state imaging device according to the second aspect, it is possible to simultaneously output a moving object signal and an image signal. In particular, due to such simultaneous output of the image signal and the moving object signal, the variation of the image display using these two signals is remarkably increased, and the use of the solid-state imaging device for motion detection is significantly expanded.

(Claim 3) In the invention according to claim 3,
An output is switched between the output of the logic operation circuit and the comparison result of the comparison circuit in accordance with the signal level of the image signal. By such a switching operation, it is possible to appropriately reduce the error in motion detection in accordance with the signal level of the image signal. At the same time, the isolated area is not unnecessarily deleted according to the signal level of the image signal, so that it is possible to detect the movement of a small detection target as much as possible.

For example, when the output of the logical operation circuit is selectively output in the high luminance portion of the image signal, it is possible to selectively reduce the error in motion detection due to shot noise. In addition, by selectively outputting the output of the comparison circuit in the low-luminance portion of the image signal, it is possible to detect a “small motion of a small detection target” that is originally unrelated to shot noise.

For example, when the output of the logical operation circuit is selectively output in the low luminance portion of the image signal, it is possible to selectively reduce the error in motion detection due to random noise in the circuit system or the like. In addition, by selectively outputting the output of the comparison circuit in the high-luminance portion and the intermediate-luminance portion of the image signal, it becomes possible to detect "small motion of a small detection target" which is originally unrelated to random noise.

Further, for example, when the output of the logical operation circuit is selectively output in the low luminance portion and the high luminance portion of the image signal, it is possible to selectively reduce the motion detection error due to random noise and shot noise. Become. In addition, by outputting the output of the comparison circuit side in the intermediate luminance section, it is possible to detect "small motion of a small detection target" which is originally unrelated to random noise or shot noise.

The above-mentioned operations are all possible only in a configuration for simultaneously outputting a moving object signal and an image signal. (Claim 4) According to the invention described in claim 4, the logical product of the comparison results is obtained along the horizontal direction of the screen. Therefore, it is possible to eliminate an isolated point where a logical change occurs only for one pixel in the horizontal direction, and to reduce an isolated point of a logical change caused by shot noise or minute movement of the background.

(Claim 5) In the invention according to claim 5,
The logical product of the comparison results is taken along the vertical direction of the screen. Therefore, it is possible to eliminate an isolated point where a logical change occurs only for one pixel in the vertical direction, and to reduce an isolated point of a logical change caused by shot noise or minute movement of the background.

(Claim 6) In the invention according to claim 6,
The logical product of the comparison results is taken along the time axis direction. Therefore, it is possible to eliminate isolated points where a logical change occurs only in one pixel in the time axis direction, and to reduce isolated points of a logical change caused by shot noise or minute movement of the background.

(Claim 7) In the invention according to claim 7,
Since the pixel output holding unit is provided for each light receiving unit, the operation of accumulating the pixel output of the current frame and the operation of holding or outputting the pixel output of the previous frame in the light receiving unit can be performed simultaneously in parallel. Therefore, the pixel output for two frames is time-divisionally output to the vertical readout line, so that the light receiving accumulation period of the current frame is not limited. As a result, the level of pixel output increases, and erroneous motion detection due to noise or the like can be fundamentally reduced.

(Claims 8 and 9) Claim 8 or Claim 9
According to the invention described in (1), the pixel output from the light receiving unit is directly held in the control region of the amplification element, so that there is no need to provide a capacitor for holding the pixel output on the way. Further, there is no signal loss in the capacity distribution in the middle of the capacity, and the S / N
Can be improved.

Further, since the control region is initialized to a constant reset potential by the reset circuit, it is possible to prevent pixel outputs from being mixed between frames. as a result,
The S / N of the pixel output is improved, and erroneous motion detection due to noise or the like can be fundamentally reduced. (Claim 10) In the invention according to claim 10, the comparison circuit outputs a binary signal. Therefore, a general-purpose logic circuit may be configured as the logic operation circuit. In transferring the binary signal, a shift register circuit can be used. By using such a shift register circuit, it is possible to easily realize high speed and low noise in the horizontal transfer operation of the moving object signal.

In particular, since the noise margin during signal transfer is improved by binarizing a moving object signal, it is possible to fundamentally reduce erroneous detection of movement due to noise or the like.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a circuit configuration of a first embodiment.

FIG. 2 is a diagram illustrating a circuit configuration of an outlier detection circuit 6;

FIG. 3 is a diagram illustrating drive timing of vertical transfer according to the first embodiment.

FIG. 4 is a diagram illustrating driving timing of horizontal transfer according to the first embodiment.

FIG. 5 is a diagram illustrating a circuit configuration of a second embodiment.

FIG. 6 is a diagram illustrating driving timing of horizontal transfer according to a second embodiment.

FIG. 7 is a diagram illustrating a circuit configuration according to a third embodiment.

FIG. 8 is a diagram illustrating drive timing of horizontal transfer according to a third embodiment.

FIG. 9 is a diagram showing a conventional motion detection image processing apparatus 100.

[Description of Signs] 1 unit pixel 2 vertical read line 3 vertical scan circuit 4 current source 5 difference processing circuit 6 outlier detection circuit 7 horizontal read line 7a video amplifier 8 horizontal scan circuit 9 shift register 9a D flip-flop 9b AND circuit 10 Solid state imaging device for motion detection 21 Comparator 22 D flip-flop 23 AND circuit 23a D flip-flop 24 AND circuit 25 Shift register 26 D flip-flop 27 OR circuit 33 AND circuit 34 Frame memory QRSH MOS switch for reset PD photodiode QT For charge transfer MOS switch QA Amplifying element QP MOS switch for resetting signal charge QX MOS switch for vertical transfer CV Capacitor for holding dark signal QV MOS switch QH MO for horizontal transfer S switch CCA capacitor CCB capacitor QB3 MOS switch QB1 MOS switch NA NAND circuit INV1 Inverter

Claims (10)

[Claims] 1. A plurality of light receiving units arranged in a matrix and generating pixel outputs according to incident light; a plurality of vertical read lines provided for each column of the plurality of light receiving units; While sequentially selecting the specific row of the section, the pixel output of the previous frame held in the past from the light receiving unit of the specific row,
A vertical transfer circuit for sequentially outputting the pixel output of the current frame newly held from the light receiving unit of the specific row to the vertical readout line; provided for each of the vertical readout lines; A comparison circuit that compares the pixel output of the previous frame and the pixel output of the current frame transferred to the vertical transfer line; a horizontal transfer circuit that horizontally transfers a comparison result of the comparison circuit output for each of the vertical read lines; A solid-state imaging device for motion detection, comprising: a logical operation circuit that executes a logical operation for reducing an isolated region of a logical change with respect to the comparison result of (1). 2. The motion detection solid-state imaging device according to claim 1, wherein one of a pixel output of a previous frame and a pixel output of a current frame transferred time-divisionally via the vertical readout line is selectively selected. A solid-state imaging device for motion detection, comprising: an image signal output circuit for horizontally transferring the image signal. 3. The solid-state imaging device for motion detection according to claim 2, wherein: a level determining circuit that determines a level of an image signal output from the image signal output circuit; A solid state imaging device for motion detection, comprising: an output switching circuit that switches and outputs an output of the logical operation circuit and a comparison result of the comparison circuit. 4. The solid-state imaging device for motion detection according to claim 1, wherein the logical operation circuit stores the comparison result for each horizontally transferred pixel. A solid-state imaging device for motion detection, comprising: a memory circuit; and a horizontal AND circuit that performs an AND operation between the storage content of the bit memory circuit and the comparison result. 5. The solid-state imaging device for motion detection according to claim 1, wherein the logical operation circuit includes: a line memory circuit that stores the comparison result line by line; A solid-state imaging device for motion detection, comprising: a vertical AND circuit that performs a logical AND operation between the storage content of the line memory circuit and the comparison result. 6. The solid-state imaging device for motion detection according to claim 1, wherein the logical operation circuit includes a frame memory circuit that stores the comparison result for each screen. A solid-state imaging device for motion detection, comprising: a time-axis AND circuit that performs an AND operation between the storage content of the frame memory circuit and the comparison result. 7. The solid-state imaging device for motion detection according to claim 1, wherein the vertical transfer circuit is provided for each of the light receiving units, and outputs a pixel output from the light receiving unit. A pixel output holding unit for holding and outputting the held pixel output in a non-destructive manner; and a connection / separation provided for each of the pixel output holding units, for connecting / separating an output stage of the pixel output holding unit and the vertical readout line. After outputting the pixel output of the previous frame previously held in the pixel output holding unit of the specific row to the vertical readout line via the connection / separation unit, the light receiving unit newly outputs the pixel output to the pixel output holding unit. Vertical transfer control means for holding the pixel output of the current frame and outputting the held pixel output of the current frame to the vertical readout line via the connection / separation unit. Body imaging apparatus. 8. The motion detection solid-state imaging device according to claim 7, wherein the pixel output holding unit has a control area for holding a pixel output, and a pixel corresponding to the pixel output held in the control area. An amplification element that outputs an output, a transfer circuit that transfers a pixel output generated by the light receiving unit to a control area of the amplification element, and a reset circuit that resets a pixel output accumulated in the control area of the amplification element. A solid-state imaging device for motion detection, comprising: 9. The solid-state imaging device for motion detection according to claim 8, wherein the amplifying element is a junction-type field effect transistor, and the pixel output transferred via the transfer circuit is the junction-type field effect. A solid-state imaging device for motion detection, which is directly stored in a gate region of a transistor. 10. The method according to claim 1, wherein:
In the solid-state imaging device for motion detection according to the paragraph, the comparison circuit determines whether the pixel output of the current frame and the pixel output of the previous frame match within an allowable range, and determines whether the determination result is true or false. A solid-state imaging device for detecting motion.