JPH11177089A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: A method of manufacturing a semiconductor device capable of forming a self-aligned contact without etching a base by over-etching is provided. A dummy pattern (800) is formed on a base to be contacted before forming an interlayer insulating film (930), and after forming the interlayer insulating film (930), the dummy pattern (800) is removed. Then, a contact hole is formed, and a conductive film (110, 510) is formed in the contact hole. [Effect] Since the contact hole can be formed by removing the dummy pattern with a high etching selectivity, a problem such as over-etching does not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a self-aligned contact easily and with high precision by preventing excessive etching of a diffusion layer or the like formed on a silicon substrate. And a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art As is well known, a MOSFET (Metal Oxide Semiconductor) formed on a silicon single crystal substrate is known.
Field Effect Transistors) have improved performance by reducing device size using microfabrication. The performance improvement by miniaturization is called a scaling law (proportional reduction law). For example, the IEJ Journal of Solid State Circuit (IEEE Jo
unal of Solid State Circuit) Volume 9, page 256, 19
The one reported in 1974 is known. A study based on the scaling law revealed that the performance could be improved by miniaturizing the integrated device, but it became clear that the parasitic resistance was a major problem in the performance improvement.

In particular, in the case of a fine MOSFET, the underlying silicon substrate is excessively etched when the contact hole is formed, and the contact surface between the electrode and the silicon substrate is located at the junction between the diffusion layer having a low impurity concentration and the substrate. , Or reaches a portion below the junction position, thereby generating parasitic resistance. Such an obstacle becomes particularly remarkable when an SOI (Silicon on Insulator) substrate having a thin silicon layer is used. That is, in an SOI substrate having a thin silicon layer, the contact hole sometimes penetrates through the silicon layer and reaches an insulator layer located below the silicon layer.

In order to prevent such a failure, various new device structures and manufacturing methods have been proposed. Among them, a technique called a self-aligned contact is most widely known as a contact forming technique. This self-aligned contact is widely used for forming fine contacts in a highly integrated memory. For example, the 1993 International Electron Device Meeting,
Technology Digest (International Electron
Devices Meeting Technology Digest), page 441.

In the self-aligned contact, when a contact hole is formed in the interlayer insulating film, over-etching is prevented by forming the interlayer insulating film into a laminated structure. That is, an interlayer insulating film composed of a laminated film of a thin aluminum oxide film and a silicon oxide film is formed, and the etching after the silicon oxide film is etched is stopped by the lower aluminum oxide film. In this case, an aluminum oxide film having an etching rate lower than that of a silicon oxide film functions as an etching stopper film, and a diffusion layer or the like as a base is protected by the aluminum oxide film.
It will not be etched. Thereafter, the contact hole can be formed without affecting the base by gently removing the exposed thin aluminum oxide film. Instead of an aluminum oxide film, a silicon nitride film is also widely used as an etching stopper film.

[0006]

Conventionally, a contact hole is formed at a position deviated on a planar layout from a diffusion layer, a wiring layer, a gate electrode, or the like (hereinafter, such a displaced arrangement is referred to as a noticeable arrangement). In addition, since the base is also etched by the overetching, a contact hole is formed from the diffusion layer to the peripheral portion of the diffusion layer. If a metal wiring is formed in the contact hole, the bonding characteristics are deteriorated. Failures such as a short circuit of the wiring with a lower wiring occur.

In the above self-aligned contact, overetching is prevented by the etching stopper film.
Such a problem does not occur even in the case of a marked arrangement. However, this method is based on the premise that the etching selectivity between the stacked interlayer insulating films is large. However, in an actual process, it is difficult to use an insulating film having a large selectivity, so that the progress of etching is limited by etching. It is difficult to stop effectively by the stopper film,
There were problems such as short circuit. In addition, when an insulating film having a special composition is used to improve the etching selectivity, there is a problem in that element characteristics deteriorate due to contamination by impurities.

That is, in the above conventional self-alignment technique,
Although it is necessary to make the etching selectivity between the upper layer film and the etching stopper film sufficiently large, in the actual case, the selectivity is small, which has been a serious obstacle in practical use.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a method of manufacturing a semiconductor device capable of forming a self-aligned contact easily and with high accuracy.

[0010]

According to the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a lower insulating film on a main surface of a semiconductor substrate; and forming a dummy layer on the lower insulating film. Forming a dummy pattern by removing a portion of the dummy layer where a contact hole is to be formed and removing the other portion, and forming the upper insulating film surrounding the dummy pattern by the lower insulating film. And forming the dummy pattern on the exposed surface, and removing the dummy pattern.

That is, in the conventional method, a predetermined portion of an insulating film for forming a contact hole is etched on a base such as a diffusion layer to be contacted. Therefore, the above-described problem such as the diffusion layer being etched when the contact hole is formed has occurred.

However, in the present invention, a dummy pattern having a predetermined shape is formed in a portion where a contact hole is to be formed, and after surrounding the dummy pattern with an insulating film, the dummy pattern is removed to remove the contact hole. Is formed. The portion from which the dummy pattern has been removed becomes a contact hole, and this portion is filled with a conductive material to form a contact with the base. Therefore, according to the present invention, the etching of the insulating film for forming the contact pattern is not performed on the diffusion layer or the like, and the diffusion layer or the like is not etched.

The dummy pattern is formed by etching and patterning a predetermined portion of the dummy layer, and the contact hole is formed by etching and removing the dummy pattern. However, each of these steps is performed by providing a lower insulating film having a much lower etching rate than the dummy layer or the dummy pattern between the dummy layer or the dummy pattern and the base. Therefore, formation and removal of the dummy pattern can be performed without substantially affecting the base. In addition, since the lower insulating film is thin, the film is removed to expose the surface of the base, and even when the contact hole is formed, the base such as the high impurity concentration diffusion layer is hardly affected.

Further, in the present invention, since the dummy pattern is removed and does not remain in the contact hole, not only an insulator but also a conductor or a semiconductor can be used as the dummy pattern. Compared with the conventional self-aligned contact technology in which the insulating film having the composition described above is etched to form the contact hole, a material having a much wider range of material selection and a greater etching selectivity with the underlying film can be selected. it can. For example, it is very easy to remove the dummy pattern and form a contact hole by selecting polycrystalline silicon or the like which is easy to process and has high etching selectivity with silicon oxide.

When forming a MOSFET according to the present invention, a step of forming a gate insulating film on a semiconductor substrate;
Forming a gate electrode having a desired shape on the gate insulating film; and doping a predetermined portion of the semiconductor substrate with an impurity having a conductivity type opposite to that of the semiconductor substrate to form a high-concentration impurity diffusion layer. Forming a dummy layer on the lower insulating film, removing a predetermined portion of the dummy layer, and removing at least a portion of the dummy layer above the high-concentration impurity diffusion layer. Forming a dummy pattern located on the lower insulating film and exposing a surface of a predetermined portion of the lower insulating film; forming an upper insulating film on the exposed surface of the lower insulating film; and removing the dummy pattern. It can be easily formed by a method of manufacturing a semiconductor device, which includes a step of performing the following.

In this case, contact holes are formed to the source and drain, which are the high-concentration impurity diffusion layers of the MOSFET. However, since the contact holes are not formed by etching the insulating film, the underlying holes are not formed. The concentration diffusion layer is not overetched.

After the step of removing the dummy pattern, the exposed portion of the lower insulating film is removed to form a contact hole, and the conductive film electrically connected to the high-concentration impurity diffusion layer is removed. By forming the contact hole in the contact hole, a contact with respect to the high concentration impurity of the MOSFET is formed.

In forming a contact of the MOSFET, a gate protection insulating film is formed on the gate electrode, and a sidewall insulating film is formed on a side portion of the gate electrode and the gate protection insulating film. If it is formed, since the sidewall insulating film exists below the dummy layer, the underlayer is sufficiently protected by the sidewall insulating film.

If the dummy pattern is removed after reducing the thickness of the dummy pattern and the upper insulating film by a predetermined amount and flattening the upper surface, not only the formation of the contact hole is easy, but also the contact hole is easily formed. It is easy to flatten the upper surface of the insulating film around it and it is practically preferable.

If at least a part of the dummy pattern is formed so as to be located above the gate electrode, and at least a part of the gate electrode is exposed through the contact hole, it is possible to prevent the gate electrode from being exposed. A contact is formed.

Further, if the dummy pattern is formed at a position separated from the gate electrode, contacts to the source and the drain are formed.

If a part of the dummy pattern is formed so as to be located above the sidewall insulating film formed on the side of the gate electrode, the sidewall insulating film exists below the dummy layer. The underlayer is sufficiently protected by the sidewall insulating film.

If polycrystalline silicon is used as the dummy layer, a sufficiently high etching rate can be obtained for silicon oxide as a base insulating film, and the dummy pattern can be removed without overetching the base.

In practice, it is practical that the conductive film is composed of two conductive films, the lower film is a polycrystalline silicon film doped with impurities having the same conductivity type as that of the base, and the upper layer is a tungsten film. preferable. By doing so, the polycrystalline silicon film effectively increases the thickness of the underlying high impurity concentration diffusion layer, and the contact area between the tungsten film and the silicon film can be sufficiently increased.

A semiconductor device having the following structure is formed by these manufacturing methods. That is, as shown in FIG. 1, two layers of insulating films are disposed on the sides of the contacts formed on the source and drain of the MOSFET.
The thickness of the lower insulating film 920 is significantly smaller than that of the upper insulating film 930. This lower insulating film 920 is a dummy pattern 80.
This is a film that extends below 0 and acts as an etching stopper when removing the dummy pattern 800 and protects the underlying high impurity concentration diffusion layer. Therefore, the lower insulating film 920 is much thinner than the upper insulating film 930, and the film thickness of 1/10 or less is sufficient.

The two-layered insulating film can be formed on an element isolation insulating film formed on a semiconductor substrate, and is formed on the insulating film 910 when an SOI substrate is used as the substrate.

The metal layer in the contact hole is electrically connected to the high impurity concentration diffusion layer, and at least one side of the metal layer is
It can be formed in a self-aligned manner with the gate electrode of the MOSFET. Further, if the metal layer in the contact hole has a two-layer structure as described above, a practically preferable semiconductor device can be obtained.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to the formation of a contact with a predetermined portion of the surface of a substrate. Therefore, the present invention does not depend on the structure or conductivity type of the substrate itself. Silicon substrate, NMOS and PM
The same can be applied to an OS or the like.

As a material of the dummy pattern, polycrystalline silicon is most practical because a sufficiently high etching selectivity can be obtained between the dummy pattern and the lower insulating film. It is preferable to use a silicon oxide film for both the lower and upper insulating films.

After a dummy pattern having a predetermined shape is formed on a predetermined portion of the lower insulating film, an upper insulating film surrounding the dummy pattern is formed. After forming the dummy layer,
Prior to patterning to form a dummy pattern, the upper surface of the dummy layer may or may not be planarized. However, after forming the conductor layer in the contact hole, the upper surface is flattened and the thickness is reduced to a predetermined thickness. The process of flattening the upper surface and reducing the film thickness can be performed by a known CMP method. Also,
The step of forming the contact holes by removing the dummy pattern is sufficiently high by performing wet etching using hot phosphoric acid when a polycrystalline silicon film is used as the dummy pattern and a silicon oxide film is used as the lower insulating film. The dummy pattern can be selectively etched and removed at an etching selectivity.

[0031]

<Embodiment 1> This embodiment is an example in which the present invention is applied to the manufacture of a MOS transistor using an SOI wafer. FIG. 1 is a cross-sectional view showing the structure of the SOI-NMOS of the present embodiment, FIGS. 2 to 12 are process diagrams showing a manufacturing process of this NMOS, and FIGS. 13 and 14 are diagrams showing examples of typical plane arrangements. .

Hereinafter, the M having the planar arrangement shown in FIG.
The manufacturing process of the OSFET will be described. First, as shown in FIG. 2, a silicon support substrate 100 having a thickness of 300 nm
After forming an SOI wafer having a silicon oxide film 900 and a silicon film 120 having a thickness of 100 nm using a known method, the surface of the silicon film 120 is formed to a thickness of 10 n.
m to form a thin silicon oxide film (not shown),
A silicon nitride film 130 having a thickness of 100 nm was formed. The silicon nitride film 130, the thin silicon oxide film, and the silicon film 120 are formed by using a well-known photolithography technique.
Unnecessary portions of the silicon oxide film 900 were removed by well-known anisotropic etching to separate an active region.

After removing the resist film used as an etching mask and cleaning the surface, the silicon supporting substrate 10
The exposed surface of O was oxidized to form a silicon oxide film (not shown) having a thickness of 10 nm. After forming a 500 nm thick silicon oxide film 910 over the entire surface, a well-known CMP
(Chemical mechanical poli
(shing) using the silicon nitride film 130 as a stopper to planarize the silicon nitride film 1.
30 is removed, and as shown in FIG.
Is formed. Further, using a well-known ion implantation method, boron was doped at 10 ¹¹ cm ⁻² at an acceleration voltage of 20 keV, and the channel impurity concentration was set.

After removing the thin silicon oxide film on the surface,
After cleaning and oxidizing the surface, as shown in FIG.
A gate silicon oxide film 950 having a thickness of 5 nm was formed.
After a phosphorus-doped polycrystalline silicon film 150 having a thickness of 200 nm and a silicon oxide film 960 having a thickness of 200 nm are formed by lamination, they are patterned into a predetermined shape using a well-known photolithography technique and anisotropic etching method.
The gate of the SFET was formed.

After removing the resist film used as an etching mask and cleaning the surface, a silicon oxide film (not shown) having a thickness of 3 nm was formed using a well-known thermal oxidation method. Next, using the gate as a mask, arsenic was ion-implanted under the conditions of an acceleration voltage of 20 keV and a dose of 10 ¹⁵ cm ⁻² , and then a heat treatment was performed to form a diffusion layer (not shown) having a high impurity concentration. . In addition, thickness 1
After a 00 nm silicon oxide film is formed on the entire surface, well-known anisotropic etching is performed to form a silicon oxide film on the side walls of the gate electrode 150 and the silicon oxide film 960 thereon as shown in FIG. A side wall insulating film 970 was formed.

Next, as shown in FIG.
Is formed by laminating a silicon oxide film 975 and a polycrystalline silicon film 800 having a thickness of 600 nm.
The surface was flattened by the method.

As shown in FIG. 6, the polycrystalline silicon film 800 was patterned into a predetermined shape by known photolithography and anisotropic etching to form a dummy pattern 800. At this time, the polycrystalline silicon film 800
Since the portion located on the thick isolation insulating film 910 was etched, the polycrystalline silicon film 800 could be easily patterned without fear of the silicon film 120 being etched.

As shown in FIG. 7, after a silicon oxide film 930 having a thickness of 600 nm is formed on the entire surface, a well-known CMP
Polishing was performed to the height of the upper surface of the dummy pattern 800 by a method to flatten the surface.

As shown in FIG. 8, by wet etching using hot phosphoric acid at 160 to 180 ° C. as an etchant,
The dummy pattern 800 made of a polycrystalline silicon film was removed by etching using the silicon oxide film 975 as a base as an etching stopper. In the above wet etching, since the etching selectivity between polycrystalline silicon and silicon oxide was sufficiently high, the polycrystalline silicon film 800 could be selectively etched and removed.

The silicon oxide film 975 is anisotropically etched to leave only the portion formed on the side wall of the gate and the portion formed on the plane as shown in FIG. The surface of the silicon film 120 was exposed.
In this embodiment, the side surface insulating layer 970 is provided on the side surface of the gate.
Although the parasitic capacitance generated on the side surface of the gate is reduced by forming the silicon oxide film 975, the side surface insulating layer 970 may not be formed, and only the silicon oxide film 975 may be used.

Next, as shown in FIG. 10, a 50-nm-thick polycrystalline silicon film 110 doped with phosphorus and a 500-nm-thick tungsten film 510 are formed by laminating using a known method. Then, the surface was flattened by a well-known CMP method, and as shown in FIG. 11, a laminated structure of the polycrystalline silicon film 110 and the tungsten film 510 was formed inside the hole formed by removing the dummy pattern 800. . As is well known, since the contact resistance between the metal wiring layer and the diffusion layer is governed by the contact resistance between the metal wiring layer and silicon, it is practically important to increase the contact area. In the present embodiment, there is an advantage that the diffusion layer is effectively thickened by the polycrystalline silicon film 110 to reduce the resistance, and the contact area between the tungsten film 510 and the polycrystalline silicon film 110 can be increased.

In order to form a contact, the dummy pattern 800 may be completely removed and then a tungsten film may be formed. However, the dummy pattern 800 is not completely removed but is etched back to a predetermined height. Alternatively, the polycrystalline silicon used as the dummy pattern 800 may be used as the connection layer. Alternatively, the connection layer may be formed using only a metal film such as tungsten.

In the case of forming a CMOS, after forming an undoped polycrystalline silicon film, a mask made of a photoresist film or a silicon oxide film is formed.
By doping different portions of the undoped polycrystalline silicon film with n-type and p-type impurities, the n-type and p-type regions can be formed separately from each other. At this time, since the entire surface of the base is the polycrystalline silicon film 110, it is easy to form the n-type and p-type regions separately from each other.

When the tungsten film 510 is etched and flattened by the above-described CMP, the etching is stopped once when the surface of the insulating film 930 is exposed, and only the tungsten film 510 is etched, so that the surface of the gate can be etched. The tungsten film 510 can be accurately removed.
Further, another insulating film may be formed over the insulating film 930, and the uppermost insulating film may be used as an etching stopper for CMP. For example, when a silicon nitride film is formed over the silicon oxide film 930 and the silicon nitride film is used similarly as the insulating layer 960 over the gate electrode 150, the end point of CMP can be effectively controlled.

Next, as shown in FIG. 12, an interlayer insulating film 940 is formed, a contact hole is formed, and a connection layer 510 is formed.
After exposing a predetermined portion of the surface of the substrate, a wiring layer 600 was formed using a known method, and thereafter, a semiconductor device was formed using a normal silicon LSI forming method.

<Embodiment 2> This embodiment is an example of forming a contact to a diffusion layer and a gate electrode of a MOSFET according to the present invention, which will be described with reference to FIGS.

As shown in FIG. 15, a contact hole was formed on the diffusion layer using a dummy pattern, and a polycrystalline silicon film 110 was formed in the same manner as in the first embodiment. Next, as shown in FIG. 16, a contact hole to the gate electrode 150 is formed in the insulating film 960 on the gate electrode 150 and the polycrystalline silicon film 110 thereover by using a known photo-etching technique. A metal layer 510 was formed on the entire surface and processed in the same manner as in Example 1 to form a contact with the diffusion layer and the gate electrode 150. In this embodiment, since the gate electrode 150 is thicker than the diffusion layer, the patterning of the insulating film 960 thereon is easy.

<Embodiment 3> In this embodiment, a dummy pattern 8 is used.
This is an example in which a gate electrode contact is formed using 00, and will be described with reference to FIGS. First, as shown in FIG. 17, a silicon nitride film 960 was formed over the gate electrode 150, and a silicon nitride film 970 surrounding the gate electrode 150 and the silicon oxide film 960 was formed. Next, after forming a silicon nitride film 975 covering them, a dummy pattern 800 made of polycrystalline silicon was formed in the same manner as in the first embodiment.

As shown in FIG. 18, after an interlayer insulating film 930 made of a silicon oxide film is formed, the surface is flattened by CMP, the dummy pattern 800 is removed, and a contact hole is formed in the interlayer insulating film 930. Formed.

Using the silicon oxide film 930 as a mask, the exposed portions of the silicon nitride films 975, 960, and 970 were etched to form gate electrode contact holes in the portions where the dummy patterns were removed. In this case, since the etching selectivity between silicon oxide and silicon nitride is large, the silicon nitride films 975, 960,
The exposed portion of 970 was etched, but the progress of this etching was stopped by the silicon oxide films 900 and 930, and as shown in FIG.
, A contact hole having an obvious arrangement was formed.

In this embodiment, an example in which a contact to the gate electrode 150 is formed has been described. However, the same can be applied to a case where a contact between wirings in a multilayer wiring is formed.

<Embodiment 4> In each of the above embodiments, the dummy pattern 800 was patterned into a predetermined shape after the surface was flattened. In this embodiment, as shown in FIG. After the film 800 is formed on the entire surface, FIG.
As shown in FIG. 1, a dummy pattern 800 was formed by patterning a predetermined shape without flattening the surface. Even in this case, it was confirmed that good characteristics were obtained.

Embodiment 5 In each of the above embodiments, one dummy pattern was used, and the connection layer on the source and the drain was separated by self-alignment using a gate electrode.
In the present embodiment, as shown in FIGS. 22 and 23, two dummy patterns 800 independent of each other are used.
By using two dummy patterns 800 independent of each other, connection layers could be formed on the source and the drain without using the self-alignment technique using the gate. In the case of the third embodiment, when patterning the dummy pattern 800, the silicon nitride film 975 must be used as an etching stopper. In the case of the third embodiment, as shown in FIG. Since the silicon oxide film 960 and the sidewall insulating film 970 on 150 can be used as a thick etching stopper, the formation of the dummy pattern 800 is easy.

<Embodiment 6> This embodiment is an example in which a wiring layer is not formed on the connection layer 510. As shown in FIG. 24, in this embodiment, the connection layers 110 and 510 are
0, and no wiring layer is formed on the connection layers 110 and 510. However, since the connection layers 110 and 510 were buried, a low diffusion layer resistance could be realized.

<Embodiment 7> This embodiment is an example in which the present invention is applied to a memory which is a typical integrated semiconductor device using a MOSFET, and includes one transistor and one capacitor as a typical memory. FIG. 25 shows a planar arrangement of a DRAM cell, which is generally called a two-intersection arrangement. FIG.
5, reference numeral 120 denotes an active region, 150 denotes a word line,
650 indicates a bit line, respectively. FIG. 25 shows an example of connection using only the central active region. The dummy pattern 800 is formed at a position sandwiching the word line 150, and the bit line 65 is connected via a connection layer formed at this portion.
0 and a capacitor electrode (not shown).

<Embodiment 8> FIG. 26 is a diagram showing an equivalent circuit of a CMOS-SRAM cell known as a 6-transistor cell. FIG. 27 shows a typical plane layout for realizing this memory cell. Was. FIG. 27 shows active regions 124 and 125 and gate electrodes 155 and 15.
6, only the active region and the contact layer to the gate 156 in the cell are shown. The active region 125 is an NMOS region, and two NMOSs are formed in one active region 125 in order to access a memory cell and hold information. Further, the active region 124 is a PMOS region.

FIG. 28 shows the arrangement of the dummy patterns 800 for forming cells having such a layout.
In FIG. 28, the dummy pattern 800 is formed on the planar arrangement shown in FIG. As shown in FIG. 28, gates 155, 15 on active regions 124, 125
6 can be formed so as to be sandwiched between the dummy patterns 800.
By using the manufacturing method shown in the first embodiment, the gate 15
Dummy patterns 800 can be arranged so as to extend over 5,156.

<Embodiment 9> This embodiment is an example in which the layout of dummy patterns is changed so as to be suitable for fine processing. Memory cells often have the finest layout to increase storage capacity. Therefore, the layout of the dummy patterns can be appropriately changed so as to be suitable for fine processing. The present embodiment is an example of this, and FIG.
As shown in FIG. 8, all the dummy patterns 800 have a rectangular shape only, and the adjacent dummy patterns
The distances between zeros are all equal. Therefore, when forming the dummy pattern 800, grooves having the same width may be formed by etching.

Embodiment 10 This embodiment is an example in which a wiring layer for connecting different transistors to each other is formed. As shown in FIG. 30, the dummy pattern 810
NMOS formed in active region 124 and active region 12
5 is used to form a wiring layer that connects the PMOSs formed in 5.

<Embodiment 11> FIG. 31 shows an example of a layout of a dummy pattern when different memory cells are arranged. In FIG. 31, reference numeral 124 denotes an active region where a PMOS is formed, 125 denotes an active region where an NMOS is formed, and 800 and 810 denote dummy patterns, respectively.

In the memory cell array, since the gate electrodes are dense, the insulating layer 960 on the gate 150 can be used as a stopper layer in the CMP step for forming the dummy pattern 800 shown in FIG. This method can be used by providing an auxiliary gate other than the memory cell array. FIG. 32 shows an example of the arrangement, and FIG. 33 shows a cross-sectional structure. In FIG. 32, a gate 150 (shaded portion) is formed so as to surround the periphery of the element. Therefore, the gate electrode 150 is formed on the entire surface other than the periphery of the active region, and the height of the insulating film 960 formed thereon is, as shown in FIG.
Are equal. Therefore, in the CMP step after the formation of the dummy pattern 800 and the interlayer insulating film (not shown), the CMP can be stopped on the upper surface of the insulating film 960.

Further, as shown in plan view 34 and sectional view 35, dummy pattern 800 may be formed so as to extend between gates 150. FIG. 35 shows the case where the dummy pattern 800 is thicker than the total film thickness of the gate 150 and the insulating film 960. However, since the insulating film 960 functions as a stopper, the dummy pattern
0, the dummy pattern 8 is formed.
00 can be formed separately between each gate 150. Since the source and the drain are separated in advance, a short circuit can be avoided.

In these layouts, since the area other than the element region is covered with the conductive layer of the gate electrode, the interaction between the wiring layer placed thereon and the substrate can be shielded by the gate electrode. Therefore, it is possible to design a wiring layout that matches inductance and the like. In addition, since power can be supplied to the dummy gate in the same manner as the gate electrode of each element, different power can be supplied to each of the elements by dividing it into a plurality of chips in the chip.

[0064]

As is apparent from the above description, according to the present invention, not only is it unnecessary to etch the insulating film, but also it is possible to form a dummy pattern on a thick etching stopper. Therefore, unlike the conventional formation of a self-aligned contact, the base is not etched by overetching, and a self-aligned contact having excellent characteristics can be easily formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a process chart for explaining Example 1 of the present invention.

FIG. 3 is a process chart for explaining Example 1 of the present invention.

FIG. 4 is a process chart for explaining Example 1 of the present invention.

FIG. 5 is a process chart for explaining Example 1 of the present invention.

FIG. 6 is a process chart for explaining Example 1 of the present invention.

FIG. 7 is a process chart for explaining Example 1 of the present invention.

FIG. 8 is a process chart for explaining Example 1 of the present invention.

FIG. 9 is a process chart for explaining Example 1 of the present invention.

FIG. 10 is a process chart for explaining Example 1 of the present invention.

FIG. 11 is a process chart for explaining Example 1 of the present invention.

FIG. 12 is a process chart for explaining Example 1 of the present invention.

FIG. 13 is a plan layout diagram for explaining the first embodiment of the present invention.

FIG. 14 is a plan layout view for explaining the first embodiment of the present invention.

FIG. 15 is a sectional view for explaining a second embodiment of the present invention.

FIG. 16 is a sectional view for explaining a second embodiment of the present invention.

FIG. 17 is a process chart for explaining Example 3 of the present invention.

FIG. 18 is a process chart for explaining Example 3 of the present invention.

FIG. 19 is a process chart for explaining Example 3 of the present invention.

FIG. 20 is a process chart for explaining Example 4 of the present invention.

FIG. 21 is a process chart for explaining Example 4 of the present invention.

FIG. 22 is a process chart for explaining Example 5 of the present invention.

FIG. 23 is a process chart for explaining Example 5 of the present invention.

FIG. 24 is a sectional view for explaining Embodiment 6 of the present invention.

FIG. 25 is a plan layout view for explaining Embodiment 7 of the present invention.

FIG. 26 is an equivalent circuit diagram for explaining Embodiment 8 of the present invention.

FIG. 27 is a plan layout view for explaining Embodiment 8 of the present invention.

FIG. 28 is a plan layout view for explaining Embodiment 8 of the present invention.

FIG. 29 is a plan layout view for explaining Embodiment 9 of the present invention.

FIG. 30 is a plan view illustrating a tenth embodiment of the present invention.

FIG. 31 is a plan view illustrating a tenth embodiment of the present invention.

FIG. 32 is a plan layout view for explaining an eleventh embodiment of the present invention.

FIG. 33 is a sectional view for explaining Embodiment 11 of the present invention;

FIG. 34 is a plan layout view for explaining Embodiment 11 of the present invention.

FIG. 35 is a cross-sectional view illustrating Embodiment 11 of the present invention.

[Explanation of symbols]

100: support substrate, 110: connection layer, 120, 124,
125 ... active region, 130 ... silicon nitride film, 150,
155, 156: gate electrode, 200, 300: high concentration impurity diffusion layer, 510: connection layer, 600: metal wiring, 8
00, 810: dummy pattern, 900, 910, 92
0, 930, 960... 975... Silicon oxide film, 940
... an interlayer insulating film, 950 ... a gate insulating film, 970 ... a side wall insulating film.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/092 H01L 27/10 381 21/8242 29/78 613A 27/108 616K 21/8244 627C 27/11 29/786

Claims (11)

[Claims] A step of forming a lower insulating film on a main surface of a semiconductor substrate; forming a dummy layer on the lower insulating film; leaving a portion of the dummy layer where a contact hole is to be formed; Removing the other portion to form a dummy pattern, and forming an upper insulating film surrounding the dummy pattern on the exposed surface of the lower insulating film;
A method of manufacturing a semiconductor device, comprising a step of removing the dummy pattern. A step of forming a gate insulating film on the semiconductor substrate; a step of forming a gate electrode having a desired shape on the gate insulating film; Forming a high-concentration impurity diffusion layer by doping an impurity having a conductivity type of, a step of forming a lower insulating film over the entire surface, and forming a dummy layer on the lower insulating film; Removing a portion to form a dummy pattern at least partially located above the high-concentration impurity diffusion layer and exposing a surface of a predetermined portion of the lower insulating film; A step of forming an upper insulating film on the surface and a step of removing the dummy pattern. 3. A step of forming a contact hole by removing an exposed portion of the lower insulating film after the step of removing the dummy pattern, and a step of forming a conductive hole electrically connected to the high concentration impurity diffusion layer. 3. The method according to claim 2, further comprising the step of forming a conductive film in the contact hole. 4. The step of forming the dummy layer is performed after forming a gate protection insulating film on the gate electrode and a sidewall insulating film on side portions of the gate electrode and the gate protection insulating film. 4. The method of manufacturing a semiconductor device according to claim 2, wherein 5. The method according to claim 1, wherein the step of removing the dummy pattern is performed after the thickness of the dummy pattern and the upper insulating film is reduced by a predetermined amount and the upper surface is flattened. A method for manufacturing a semiconductor device according to any one of the above. 6. The semiconductor device according to claim 1, wherein at least a part of said dummy pattern is formed above said gate electrode, and at least a part of said gate electrode is exposed through said contact hole. 6. The method for manufacturing a semiconductor device according to any one of 2 to 5. 7. The method according to claim 2, wherein the dummy pattern is formed at a position separated from the gate electrode. 8. The semiconductor device according to claim 2, wherein a part of said dummy pattern is formed above a sidewall insulating film formed on a side portion of said gate electrode. A method for manufacturing a semiconductor device according to claim 1. 9. The method according to claim 1, wherein said dummy layer is made of polycrystalline silicon. 10. The method of manufacturing a semiconductor device according to claim 1, wherein said conductive film comprises two conductive films. 11. The semiconductor device according to claim 10, wherein said conductive film comprises a polycrystalline silicon film doped with an impurity having the same conductivity type as said high-concentration impurity diffusion layer and a tungsten film formed thereon. 13. The method for manufacturing a semiconductor device according to item 5.