JPH11177085A - Semiconductor device - Google Patents

Abstract

[PROBLEMS] To suppress an increase in parasitic resistance due to wiring even if a resistance rise occurs in a thin line portion of a metal silicide layer due to heat treatment or the like during a process of a semiconductor device. In a semiconductor device, a linear gate electrode is formed on a semiconductor substrate, and a source / drain diffusion layer is formed on a surface layer of the semiconductor substrate on both sides of the gate electrode. The metal silicide layer 8 covers the entire surface of the diffusion layer 10 while being insulated from the gate electrode 7.
Is formed on the semiconductor substrate 3 so as to cover at least the gate electrode 7 and the metal silicide layer 8.
Are formed. A groove 13 is formed in the insulating film 12 on the metal silicide layer 8 so as to extend along the length direction of the gate electrode 7 and reach the metal silicide layer 8, and a buried conductive layer 14 is buried in the groove 13. It has become.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a metal silicide layer is formed on a surface of a diffusion layer of a semiconductor substrate.

[0002]

2. Description of the Related Art In recent years, a semiconductor device in which a memory element and a logic element are mixedly mounted on the same chip has been developed for the purpose of reducing the cost, reducing the power consumption, and increasing the speed of an information processing system. In particular, when applying semiconductor devices to three-dimensional graphics, etc., a memory device with a wide bandwidth is required for high-speed data transfer, and this is achieved by mixing large-capacity memory devices with high-speed logic devices. Achieved.

In a logic element, a parasitic resistance and a parasitic capacitance are factors that hinder speeding up. Therefore, in order to reduce the parasitic resistance and the parasitic capacitance, as shown in FIG. 7A, the source / drain diffusion layer 52 formed on the surface of the semiconductor substrate 51 and the gate electrode 53 formed on the semiconductor substrate 57 are formed. above, for example, titanium silicide (TiSi _x) layer, cobalt silicide (CoSi _x) layer or the like of the metal silicide layer 54 was formed in a self-aligned manner, so-called salicide (self-aligned silicide) structure is employed. Due to the formation of salicide, the resistance value of the diffusion layer 52 is several Ω / □.
To a degree.

[0004]

However, a dynamic access random memory (DRA) is added to this logic element.
When a memory element such as M) is mixedly mounted, a high-temperature process for forming a memory cell after forming a metal silicide layer is added. For example, a capacitor insulating film of a capacitor of a memory element is formed of silicon oxide (S
For example, when a so-called NO film which is a composite film of an iO ₂ ) film and a silicon nitride (SiN) film is formed. As a result, the metal silicide layer having low heat resistance aggregates to increase the resistance, thereby deteriorating the performance of the logic element. The increase in resistance due to the heat treatment is particularly remarkable in the thin line portion of the metal silicide layer.

Recently, for example, by adding about 5% of tungsten (W) to titanium (Ti), 800
A process has been developed to obtain a high heat-resistant salicide with no increase in resistance up to about ℃ (IEDM Tech.Dig., (19
96) K. Fujii et al., P. 451). However, when the above-described capacitor insulating film of the NO film is used for the memory cell of the DRAM, heat resistance that can withstand a heat treatment process at a higher temperature is required, which may cause an increase in the resistance of the metal silicide layer. .

Further, the range of the heat resistant temperature of the metal silicide layer
Tantalum oxide (TaO) _Five) And bismuth su
BST composed of trontium, titanium and titanium oxide
Use of high dielectric film such as
Considering lowering the formation temperature of memory cells
Have been. However, the formation method and processing of the capacitor electrode
There is a problem in this, etc., and it is not yet a practical stage. Salisai
To reduce contact resistance
The impurity concentration at the interface between the metal silicide layer and the diffusion layer
In addition, when forming salicide, metal silicide
It is known that resistance increases in the thin line portions of the layer.

On the other hand, after forming the DRAM, FIG.
As shown in FIG. 3, a buried conductive layer (BMD) made of a conductive material is formed on the insulating film 55 on the diffusion layer 52 along the gate electrode 53 and connected to the diffusion layer 52.
The present inventors have reported a technique for forming a diffusion layer 52 by forming a ionic layer 56 and lowering the resistance of the diffusion layer 52 by backing the diffusion layer 52 with such a buried conductive layer 56 (Symp. on VLSI Tech. (1997). ) M. Tsukamoto et al., P.23
). As a conductive material constituting the buried conductive layer 56,
For example, W is used.

However, since the buried conductive layer 56 is not formed by a self-alignment process,
3 and a distance from the field insulating film 57. As a result, the contact area between the semiconductor substrate 51 and the buried conductive layer 56 at the position of the diffusion layer 52 is reduced, the contact resistance between them is increased, and the distance between the transistor and the buried conductive layer 56 is increased. Accordingly, there arises a problem that the parasitic resistance of the transistor due to the wiring increases.

As described above, even if the resistance rises at the fine line portion of the metal silicide layer due to the heat treatment during the process of the semiconductor device or the increase in the impurity concentration at the interface between the metal silicide layer and the diffusion layer, the wiring is not affected. Development of a semiconductor device capable of suppressing an increase in parasitic resistance has been keenly desired.

[0010]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention has a linear gate electrode formed on a semiconductor substrate, and a diffusion layer formed on the surface of the semiconductor substrate on both sides of the gate electrode. Are formed. Further, a metal silicide layer is formed over the entire surface of the diffusion layer while being insulated from the gate electrode, and an insulating film is formed on the semiconductor substrate so as to cover at least the gate electrode and the metal silicide layer. A groove is formed in the insulating film on the metal silicide layer along the length direction of the gate electrode and at a depth reaching the metal silicide layer, and a buried conductive layer is buried in the groove.

In the present invention, the buried conductive layer is formed in the insulating film on the metal silicide layer along the length direction of the gate electrode and buried in a groove formed to a depth reaching the metal silicide layer. Therefore, the metal silicide layer is formed on the metal silicide layer while being electrically connected to the metal silicide layer. Therefore, the buried conductive layer is
The buried conductive layer was formed of a material having a very low resistance to the diffusion layer because it was connected to the semiconductor substrate at the diffusion layer position via the metal silicide layer and was provided with the diffusion layer being backed. If so, it becomes a so-called BMD that reduces the resistance of the diffusion layer.

In the present invention, since such a buried conductive layer is provided on the semiconductor substrate at the position of the diffusion layer via the metal silicide layer, an interface between the metal silicide layer and the diffusion layer is formed by a high temperature process later. Even if the resistance increases in the thin line portion of the metal silicide layer due to the increase in the impurity concentration, the buried conductive layer reduces the resistance of the diffusion layer. Therefore, parasitic resistance of the semiconductor device due to wiring formed in the semiconductor device is reduced. Further, since the metal silicide layer is formed over the entire region of the diffusion layer, the contact area of the buried conductive layer with respect to the semiconductor substrate is increased as compared with a conventional semiconductor device in which a BMD is formed directly on the semiconductor substrate at the position of the diffusion layer. It will be. As a result, the contact resistance between the semiconductor substrate and the buried conductive layer is reduced.

[0013]

Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings. FIG. 1 is a sectional side view of a main part showing a first embodiment of the present invention,
The NMOSFET portion when the present invention is applied to a complementary MOS transistor (CMOSFET) composed of an S type field effect transistor (hereinafter, referred to as NMOSFET) and a P channel MOS type field effect transistor (hereinafter, PMOSFET) is shown. Things. NMOSF
Since the ET and the PMOSFET have substantially the same configuration except that they have different conductivity types, the first embodiment will be described using the NMOSFET as an example and the description of the PMOSFET will be omitted.

As shown in FIG. 1, the NM of the semiconductor device 1
In the OSFET 2 portion, a field oxide film 4 is formed on a semiconductor substrate 3 made of a silicon (Si) substrate to electrically separate a formation region of the NMOSFET 2 from other formation regions. Further, an NMOS channel region 5 is formed in a region of the semiconductor substrate 3 where the NMOSFET 2 is formed. Further, the semiconductor substrate 3 in the formation region of the NMOSFET 2
An N ⁺ -type gate electrode 7 is formed thereon via a gate oxide film 6 having a thickness of, for example, about 5 nm.

The N ⁺ -type gate electrode 7 is, for example, 200 nm in which arsenic (As), which is an N-type impurity, is introduced at a high concentration.
It consists of a polysilicon (Poly-Si) film with a thickness of about
A line is formed continuously with the gate electrode of the PMOSFET. This on the gate electrode 7, for example, a metal silicide layer 8 consisting of TiSi _x layer is formed. The metal silicide layer 8 is not limited to the TiSi _x layer, other, CoSi _x layer, a tungsten silicide (WSi _x) layer, composed of nickel silicide (NiSi _x) layer refractory metal silicide layer such as such It is also possible.

On the side wall of the gate electrode 7, for example, SiO ₂
Is formed. Further, on the surface layer of the semiconductor substrate 3 on both sides of the gate electrode 7 and immediately below the sidewall 9, an N-type LDD (Lightly Doped Draid) is provided.
n) A region 10 is formed. Further sidewall 9
An N-type source / drain diffusion layer 11 serving as a diffusion layer of the present invention is formed continuously from the LDD region 10 on the outer surface of the semiconductor substrate 3 on the outer side. This diffusion layer 11
In order to reduce contact resistance, impurities are introduced at a high concentration.

The same metal silicide layer 8 as that on the gate electrode 7 is formed over the entire surface of the diffusion layer 11. The metal silicide layer 8 is formed, for example, by selectively silicifying Si of the semiconductor substrate 3 and Poly-Si of the gate electrode 7, and is insulated from the gate electrode 7 by the sidewall 9. It is provided in. On the other hand, the PMOSFET formation region has the same configuration as the NMOSFET 2 except that the conductivity type of the channel region and the like is different.

On the semiconductor substrate 3, an insulating film 12 having a flattened surface is formed so as to cover at least the gate electrode 7 and the metal silicide layer 8. The insulating film 12
For example, it is formed of a film whose surface can be flattened at a low temperature that does not cause the metal silicide layer 8 to aggregate. For example, it is made of a film that can be planarized by a chemical mechanical polishing (CMP) method, a film that can be planarized by reflow at a low temperature that does not cause the metal silicide layer 8 to aggregate, and the like. The former film includes, for example, an impurity-free SiO ₂ film (hereinafter, referred to as an NSG film) formed by a chemical vapor deposition method (CVD method), and the latter film includes, for example, boron-containing film.
A phosphosilicate glass (BPSG) film is mentioned.

The insulating film 12 on the metal silicide layer 8 includes
Metal silicide layer 8 along the length direction of gate electrode 7
The groove 13 is formed at a depth reaching. The groove 13 is at least twice as long as its width, for example, is formed to have a length of 1 μm or more. A buried conductive layer 14 for reducing the resistance of the diffusion layer 11 is buried in the groove 13. Therefore, the buried conductive layer 14 is formed in a line shape having a length twice or more the width thereof, for example, a length of 1 μm or more like the wiring.

As the conductive material forming the buried conductive layer 14, any material can be used as long as it has a very low resistance to the diffusion layer 11. Examples of such a conductive material include W and aluminum (A
1), an alloy layer of copper (Cu) and Al—Cu, and a silicide layer. For example, when W is used, a buried conductive layer satisfactorily buried in the groove 13 by a CVD method having good burying characteristics. 14 can be obtained.

The buried conductive layer 14 is formed on the gate electrode 7.
Is a line-shaped one embedded in the groove 13 along the length direction. Since the groove 13 is formed in the insulating film 12 on the metal silicide layer 8 to a depth reaching the metal silicide layer 8, the groove 13 is formed on the metal silicide layer 8 in a state electrically connected to the metal silicide layer 8. Is formed. Therefore, the low-resistance buried conductive layer 14 is a so-called BMD that is connected to the semiconductor substrate 3 at the position of the diffusion layer 11 via the metal silicide layer 8 and backs the diffusion layer 11.

Although not shown, an interlayer insulating film is formed on the insulating film 12, a contact portion is formed on the interlayer insulating film, and a wiring made of, for example, Al is formed on the interlayer insulating film to form a semiconductor made of a CMOSFET. Apparatus 1
Is configured.

Next, a method of manufacturing the above-described semiconductor device 1 will be described with reference to FIGS. 2 (a) to 2 (c) and FIGS. 3 (c) and 3 (d). Here, description will be made based on the process of forming the NMOSFET 2 portion, and description of the process of forming the PMOSFET portion will be omitted.

In manufacturing the semiconductor device 1, first, as shown in FIG.
A field oxide film 4 is formed on the semiconductor substrate 3 by wet oxidation at 0 ° C. Next, ion implantation for forming a P-well region, ion implantation for forming a buried layer for preventing punch-through of a transistor, and ion implantation for adjusting Vth are performed on the semiconductor substrate 3 in a region where an NMOSFET is to be formed. Are performed to form the NMOS channel region 5.

Subsequently, a gate oxide is formed on the exposed surface of the semiconductor substrate 3, that is, the NMOS channel region 5, by pyrogenic oxidation using a mixed gas of hydrogen and oxygen at an ambient temperature of about 850 ° C. The film 6 is formed to a thickness of, for example, about 5 nm. Thereafter, a CVD method under reduced pressure (hereinafter, referred to as an LP-CVD method)
Thus, on the field oxide film 4 and the gate oxide film 6
A Poly-Si film (not shown) is deposited thereon. here,
For example, a poly-Si film having a thickness of about 200 nm is formed by an LP-CVD method using silane (SiH ₄ ) gas as a source gas and a deposition temperature of about 620 ° C.

Next, a resist mask (not shown) is formed on the Poly-Si film by lithography (resist coating, exposure, development, baking, etc.). Subsequently, the Poly-Si film is processed into a pattern of the gate electrode 7 by performing anisotropic etching using the resist mask. The anisotropic etching at this time is performed by, for example, ECR (Electron Cyclotron Resonance) etching using chlorine (Cl ₂ ) gas and oxygen (O ₂ ) gas. After that, the resist mask is removed.

Subsequently, As ⁺ ions are implanted into the semiconductor substrate 3 to form an N-type LDD region 10 as shown in FIG. This ion implantation is performed, for example, under the conditions where the ion energy is 20 keV and the dose is 5 × 10 ¹³ / cm ² . Further, the semiconductor substrate 3 is formed by the LP-CVD method.
An SiO ₂ film is deposited on the entire surface, and thereafter, the SiO ₂ film is etched back by anisotropic etching to form sidewalls 9 on the side walls of the gate electrode 7. Then, As ^+, for example, in the semiconductor substrate 3, introducing ion energy 20 keV, a dose of 5 × 10 ion-implanted with ¹⁵ / cm ² and the conditions, the N-type impurity at a high concentration in the surface layer of the semiconductor substrate 3 The source / drain diffusion layer 11 is formed. At this time, As is also introduced into the gate electrode 7 at a high concentration.

Subsequently, for example, rapid thermal annealing (rapid thermal annealing at about 1000 ° C. for about 10 seconds) is performed.
Through the aling; RTA), the impurity or the like which has been ion-implanted earlier is activated, and the NMOSFET 2 is obtained. Also PMOSFE
T is also formed in the same manner as described above except that impurities of a conductivity type different from that of the NMOSFET 2 are used, whereby a CMOSFET structure can be obtained.

Thereafter, a Ti film (not shown) is deposited on the entire surface of the semiconductor substrate 3 to a thickness of, for example, about 20 nm to 30 nm by, for example, a sputtering method. Subsequently, for example, by RTA at 650 ° C. for 30 seconds, Ti
A membrane and a diffusion layer 11 surface layer of Si causes silicidation reaction, the Poly-Si and Ti film on the gate electrode 7 is silicidation reaction to form a TiSi _x layer. Then, sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ )
The unreacted Ti film on the field oxide film 4 and the side wall 9 is removed by the mixed chemical solution. Thereafter, annealing is performed, for example, at about 800 ° C. for about 30 seconds to cause a phase transition of the TiSi _x layer, and a low resistance is formed on the surface layer of the diffusion layer 11 and on the gate electrode 7 as shown in FIG. A metal silicide layer 8 made of a TiSi _x layer is obtained.

Next, as shown in FIG. 3D, an insulating film 12 is deposited on the entire surface of the semiconductor substrate 3 by, for example, a CVD method, and then the surface of the insulating film 12 is planarized. As a method of flattening, there is a CMP method, but a method such as reflow of the BPSG film may be adopted as long as the temperature is within a range where the metal silicide layer 8 does not aggregate.

Next, the insulating film 12 is formed by a lithography technique.
A resist pattern (not shown) is formed thereon, and anisotropic etching is performed using the resist pattern as a mask to form a groove 13 along the length direction of the gate electrode 7 in the insulating film 12 on the diffusion layer 11. . At this time, the groove 13 is formed such that the surface of the metal silicide layer 8 on the diffusion layer 11 is exposed from the bottom of the groove 13. The anisotropic etching is performed using, for example, a fluorocarbon-based gas.

After the resist pattern used for forming the groove 13 is removed, as shown in FIG.
By a method, a conductive material film 14a made of, for example, a W film is deposited on the insulating film 12 so as to fill the trench 13. Then, the conductive material film 14a is exposed until the surface of the insulating film 12 is exposed.
Is etched back to obtain the buried conductive layer 14 of W shown in FIG. Thereafter, although not shown, an interlayer insulating film is formed on the insulating film 12, a contact portion is formed using a wiring material such as Al for the interlayer insulating film, and a wiring is formed on the interlayer insulating film. Through the above steps, the semiconductor device 1 including the CMOSFET of the first embodiment is completed.

In the semiconductor device 1 manufactured as described above, since the diffusion layer 11 into which impurities are introduced at a high concentration is formed for the purpose of reducing the contact resistance, the resistance of the metal silicide layer 8 becomes thinner. The so-called thin line effect which rises in the portion is easily generated. However, the diffusion layer 11
Since the buried conductive layer 14 serving as a BMD is formed on the metal silicide layer 8 formed on the surface layer of the above, the resistance of the diffusion layer 11 is reduced. Also, the buried conductive layer 14
Is made of W having much lower resistance than the diffusion layer 11,
The resistance of the buried conductive layer 14 can also be reduced. Therefore, NMOSFET2 and PMOSFET by wiring
Can be reduced.

The semiconductor substrate 3 and the buried conductive layer 14
Is formed over the entire region of the diffusion layer 11, the buried conductive layer for the semiconductor substrate 3 is compared with the conventional semiconductor device in which the BMD is formed directly on the semiconductor substrate at the position of the diffusion layer. 14 has an increased contact area. Further, since a high concentration of impurities is introduced into the diffusion layer 11, the specific resistivity (ρc) of the diffusion layer 11 is also reduced. As a result, the contact resistance between the semiconductor substrate 3 and the buried conductive layer 14 can be reduced. Note that the contact resistance between buried conductive layer 14 and metal silicide layer 8 is sufficiently lower than the contact resistance between metal silicide layer 8 and semiconductor substrate 3. Therefore, according to the first embodiment, the semiconductor device 1 that operates at high speed can be realized.

Next, a second embodiment of the semiconductor device according to the present invention will be described with reference to a sectional view of a main part shown in FIG. In FIG. 4, the same components as those in the first embodiment are denoted by the same reference numerals.

The semiconductor device 20 of the second embodiment has, on its surface, a first region, that is, a formation region (hereinafter referred to as a logic region) 20a of the logic element 33 and a second region formed at a position avoiding the logic region 20a. DRA which is two areas
M34 memory cell region 20b. The logic area 20a is constituted by, for example, a CMOSFET. Since the high-speed performance is required, the metal silicide layer 8 is formed on the surface of the diffusion layer 11 of the NMOSFET 2 and the PMOSFET (not shown) of the CMOSFET, and the buried conductive layer 14 is formed on the metal silicide layer 8. Have. In the following description of the logic region 20a, the description will be made based on the portion of the NMOSFET 2, and the description of the portion of the PMOSFET will be omitted.

On the other hand, each cell of the memory cell region 20b is constituted by, for example, the NMOSFET 2 and the capacitor 27. Since this is a region where low leakage current characteristics are required, the metal silicide layer 8 is not formed on the surface of the diffusion layer 11 of the NMOSFET 2 and the buried conductive layer 14 is not provided.

That is, a field oxide film 4 is formed on the semiconductor substrate 3 in the logic region 20a and the memory cell region 20b, and each N separated by the field oxide film 4 in the logic region 20a and the memory cell region 20b.
The semiconductor substrate 3 in the formation region of the MOSFET 2 has an NMO
An S channel region 5 is formed. In addition, each NMOS
On the semiconductor substrate 3 in the region where the FET 2 is formed, a gate electrode 21 is formed via the gate oxide film 6.
The gate electrode 21 has a thickness of, for example, about 100 nm.
and ly-Si layer 21a, of 100nm thickness of about WSi _x
The film 21b and the offset oxide film 21c made of an NSG film having a thickness of about 150 nm are formed by laminating in this order. This gate electrode 21 is formed in a line shape.

The side wall 9 is formed on the side wall of the gate electrode 21. The surface layer of the semiconductor substrate 3 on both sides of the gate electrode 21 and immediately below the sidewall 9 has N
The LDD region 10 is formed. Further, in the surface layer of the semiconductor substrate 3 outside the side wall 9, an N-type source / drain diffusion layer 11 into which impurities are introduced at a high concentration for the purpose of reducing contact resistance is provided in the LDD region 10.
And is formed continuously.

[0040] Then, the surface of the diffusion layer 11 in the logic region 20a, over the diffusion layer 11 throughout, for example, a metal silicide layer 8 consisting of TiSi _x layer is formed. The metal silicide layer 8 is formed, for example, by selectively silicifying Si of the semiconductor substrate 3. On the other hand, PM in the logic area 20a
The OSFET formation region is configured similarly to the NMOSFET 2 except that the conductivity type of the channel region and the like is different.

On the semiconductor substrate 3 in the memory cell region 20b, an SiO ₂ film 22 having a thickness of, for example, about 10 nm is formed so as to cover the gate electrode 21 and the side wall 9. Then, on the semiconductor substrate 3 in the logic region 20a and the memory cell region 20b, the gate electrode 21,
A first interlayer insulating film 23 is formed so as to cover the side wall 9, the metal silicide layer 8, the SiO ₂ film 22 and the like. On the first interlayer insulating film 23 in the memory cell region 20b, a bit line 24 connected to the diffusion layer 11 via a contact portion (not shown) is provided. This bit line 24
Is, for example, a W- polycide layer formed by laminating a WSi _x layer 24b on the Poly-Si layer 24a.

The second interlayer insulating film 2 is formed on the first interlayer insulating film 23 in the logic region 20a and the memory cell region 20b.
5 are formed. In the first interlayer insulating film 23 and the second interlayer insulating film 25 in the memory cell region 20b, a contact hole 26a having a depth reaching the diffusion layer 11 is formed. A contact portion 26 connected to the layer 11 is provided. On the second interlayer insulating film 25 in the memory cell region 20b, a capacitor 27 of the DRAM 34 connected to the diffusion layer 11 via the contact portion 26 is provided.

The capacitor 27 is of, for example, a stack type. In FIG. 4, as an example, a node electrode 27a formed on the second interlayer insulating film 25 in a bottomed cylindrical shape,
The capacitor 27 includes a capacitor insulating film 27b formed along the surface of the node electrode 27a and a plate electrode 27c formed on the surface of the capacitor insulating film 27b. The node electrode 27a and the plate electrode 27c are formed of, for example, a Poly-Si film into which impurities are introduced, and the capacitor insulating film 27b is formed of, for example, an NO film in which a SiO ₂ film and a SiN film are stacked. Note that the capacitor insulating film 27b may be formed of another dielectric film, or may be formed of one of an SiO ₂ film and a SiN film.

Further, on the second interlayer insulating film 25 in the logic region 20a and the memory cell region 20b, a third interlayer insulating film 28 whose surface is planarized so as to cover the capacitor 27 in the memory cell region 20b. Is formed. The third interlayer insulating film 28 is formed of, for example, an NSG film or a BPSG film whose surface can be flattened at a relatively low temperature without causing the metal silicide layer 8 to aggregate. The first interlayer insulating film 23, the second interlayer insulating film 25, and the third interlayer insulating film 28 correspond to the insulating film of the present invention.

Then, the third in the logic area 20a
The gate electrode 2 is formed on the metal silicide layer 8 in the interlayer insulating film 28, the second interlayer insulating film 25, and the first interlayer insulating film 23.
A groove 13 is formed at a depth along the length direction 1 and reaching the metal silicide layer 8. The diffusion layer 1 is provided in the groove 13.
The embedded conductive layer 14 made of, for example, W for reducing the resistance of the semiconductor device 1 is buried. This buried conductive layer 14
Is a so-called BMD that is connected to the semiconductor substrate 3 at the position of the diffusion layer 11 via the metal silicide layer 8 and backs the diffusion layer 11, as in the first embodiment described above.

A fourth interlayer insulating film 29 is formed on the third interlayer insulating film 28 in the logic region 20a and the memory cell region 20b so as to cover the buried conductive layer 14 in the logic region 20a. Logic area 2
In the fourth interlayer insulating film 29a at 0a, a contact hole 30a having a depth reaching the buried conductive layer 14 is formed. In the contact hole 30a, a conductive material made of W is buried, for example. Layer 1
4 are formed.

A contact hole 31a having a depth reaching the plate electrode 27c of the capacitor 27 is formed in the fourth interlayer insulating film 29 and the third interlayer insulating film 28 in the peripheral portion of the memory cell region 20b. A conductive material made of, for example, W is buried in 31a to form a W-plug 31 connected to the plate electrode 27c. Then, on the fourth interlayer insulating film 29, W-
In a state of being connected to the plugs 30 and 31 and a state of forming a CMOSFET circuit in the logic region 20a, a wiring 32 made of, for example, Al is formed, and the logic element 3 is formed.
3 and a memory cell of the DRAM 34 are mounted together.

Next, a method of manufacturing the semiconductor device 20 will be described with reference to FIGS. 5 (a) to 5 (d) and FIGS. 6 (e) and 6 (f). Here, description will be made based on the process of forming the NMOSFET 2 portion, and description of the process of forming the PMOSFET portion will be omitted. 5 and 6, the right side of the drawing is shown as a logic area 20a, and the left side is shown as a memory cell area 20b.

In manufacturing the semiconductor device 20,
First, as shown in FIG. 2A, the LOCOS method,
A field oxide film 4 is formed on the semiconductor substrate 3 by wet oxidation at 50 ° C. Next, ion implantation for forming a P-well region and ion implantation for forming a buried layer for preventing punch-through of a transistor are performed on the semiconductor substrate 3 at positions where NMOSFETs in the logic region 20a and the memory cell region 20b are to be formed. And an ion implantation for adjusting Vth is performed to form an NMOS channel region 5.

Subsequently, a gate oxide is formed on the exposed surface of the semiconductor substrate 3, ie, the NMOS channel region 5, by pyrogenic oxidation using a mixed gas of hydrogen and oxygen at an ambient temperature of about 850 ° C. The film 6 is formed to a thickness of, for example, about 5 nm.

After that, phosphorus-doped Poly-Si
The layer 21a is deposited. Here, for example, the amorphous Si (a-Si) layer 21d is formed by a LP-CVD method using SiH ₄ gas and phosphine (PH ₃ ) gas as source gases at a deposition temperature of about 550 ° C.
It is formed to a thickness of about nm. Then, for example, tungsten hexafluoride (WF ₆ ) and dichlorosilane (SiCl ₂ H ₂ ) are used as a source gas, and the deposition temperature is set to 5
By the LP-CVD method under the condition of about 80 ° C., W
Si _x film 21b and is deposited to a thickness of about 100 nm (not shown). On further WSi _x film 21b, for example, deposition temperature 4
An offset oxide film 21c made of an NSG film is deposited to a thickness of about 150 nm by a CVD method at about 20 ° C. (not shown).

Next, a resist mask (not shown) patterned by lithography is formed on the NSG film 21c, and the NSG film 21c is subjected to anisotropic etching using the resist mask to form a pattern of the gate electrode 21. Process into The anisotropic etching at this time is performed by, for example, reactive ion etching using a fluorocarbon gas. Subsequently, for example, by performing ECR etching using Cl ₂ gas and O ₂ gas, WS
i _x film 21b and a-Si layer 21d is processed into a pattern of the gate electrode 21 shown in FIG. 4 (hereinafter, referred pattern obtained is processed to the gate electrode pattern 211). After that, the resist mask is removed.

Subsequently, As ⁺ ions are implanted into the semiconductor substrate 3 under the conditions that the ion energy is 20 keV and the dose is 5 × 10 ¹³ / cm ² , for example, as shown in FIG.
An N-type LDD region 10 is formed as shown in FIG. Further L
A SiO ₂ film is deposited on the entire surface of the semiconductor substrate 3 by the P-CVD method, and thereafter, the SiO ₂ film is etched back by anisotropic etching to form the gate electrode pattern 211.
Side walls 9 are formed on the side walls of the. Next, As ⁺ is applied to the semiconductor substrate 3, for example, by ion energy of 20 ke.
V and ions are implanted under the conditions of a dose of 5 × 10 ¹⁵ / cm ² to form a source / drain diffusion layer 11 in which N-type impurities are introduced at a high concentration in the surface layer of the semiconductor substrate 3.

Subsequently, for example, the impurity or the like which has been ion-implanted previously is activated by RTA at about 1000 ° C. for about 10 seconds, and the logic area 20 a and the memory cell area 20 are activated.
b, an NMOSFET 2 is formed. Also, for the PMOSFET in the logic region 20a, the NMOSFET2
Except for using an impurity of a different conductivity type from that of the first embodiment, a CMOSFET structure can be obtained. Note that the RTA causes crystallization of the a-Si layer 21d of the pattern of the gate electrode 21 so that Poly-Si
It becomes the layer 21a. As a result, the Poly-Si layer 21a, WS
i _x layer 21b, and a gate electrode 21 consisting of offset oxide film 21c is obtained.

Next, the logic area is formed, for example, by the CVD method.
Area 20a and memory cell area 20b on semiconductor substrate 3
To a thickness of about 10 nm while covering the gate electrode 21.
iO _TwoAfter depositing the film 22, by lithography technique
Form a patterned resist mask (not shown)
You. Then anisotropic etching using a resist mask
By doing so, the logic area as shown in FIG.
20a only SiO_TwoThe film 22 is removed.

Thereafter, a Ti film (not shown) is deposited to a thickness of, for example, about 30 nm on the entire surface of the semiconductor substrate 3 by, for example, a sputtering method. Then, for example, 650
The Ti film and the Si of the surface layer of the diffusion layer 11 are silicided by RTA at 30 ° C. for 30 seconds to form a TiSi _x
Form a layer. Then, H ₂ SO ₄ and on H ₂ O ₂ field oxide film 4 by mixing chemical solution, on the side walls 9, SiO ₂ formed only in the memory cell region 20b
After removing the unreacted Ti film on the film 22, for example, 800
Annealing at about 30 ° C. for about 30 seconds.
i Si _x layer was phase transition to form a metal silicide layer 8 made of low resistance TiSi _x layer only on the surface of the diffusion layer 11 in the logic region 20a.

Next, as shown in FIG. 5D, a first interlayer insulating film 23 is deposited on the semiconductor substrate 3 in the logic region 20a and the memory cell region 20b by, for example, the CVD method. First interlayer insulating film 2
3 and a contact portion (not shown) communicating with the diffusion layer 11 is formed in the SiO ₂ film 22. Then, in a state to be connected to the contact portion on the first interlayer insulating film 23 in the memory cell area 20b, for example to form a bit line 24 made of Poly-Si layer 24a and the WSi _x layer 24b W- polycide layer. Further, a second interlayer insulating film 25 is formed on the first interlayer insulating film 23 in the logic region 20a and the memory cell region 20b so as to cover the bit line 24.

Next, the first in the memory cell region 20b
The diffusion layer 1 is formed on the interlayer insulating film 23 and the second interlayer insulating film 25.
A contact hole 26a having a depth reaching 1 is formed, and a contact portion 26 connected to the diffusion layer 11 is provided by burying a conductive material in the contact hole 26a. Then, on the second interlayer insulating film 25 in the memory cell region 20b, for example, a node electrode 27a is formed of a Poly-Si film containing impurities, and an NO film in which a SiO ₂ film and a SiN film are stacked on the surface of the node electrode 27a is used. The capacitor insulating film 27b is formed by using this. Further, a plate electrode 27c is formed of a poly-Si film containing impurities on the surface of the capacitor insulating film 27b, and includes a node electrode 27a, a capacitor insulating film 27b, and a plate electrode 27c, and is connected to the diffusion layer 11 via the contact portion 26. The capacitor 27 is obtained.

Further, a third interlayer insulating film 28 is formed on the second interlayer insulating film 25 in the logic region 20a and the memory cell region 20b so as to cover the capacitor 27, and the surface is flattened. As described above, the third interlayer insulating film 28
For example, NSG which can planarize the surface at a relatively low temperature without aggregating the metal silicide layer 8
Using a film, a BPSG film, or the like, the surface of the forming material film is planarized by a CMP method, reflow, or the like.

Next, a resist pattern (not shown) is formed on the third interlayer insulating film 28 by a lithography technique,
Anisotropic etching is performed using this resist pattern as a mask. As a result, as shown in FIG. 6E, the third interlayer insulating film 2 on the metal silicide layer 8 in the logic region 20a is formed.
8, the second interlayer insulating film 25 and the first interlayer insulating film 23
A groove 13 is formed along the length direction of the gate electrode 7. At this time, the groove 13 is formed such that the surface of the metal silicide layer 8 is exposed from the bottom of the groove 13. The anisotropic etching is performed using, for example, a fluorocarbon-based gas.

After the resist pattern used to form the groove 13 is removed, a conductive material film made of a W film (not shown) is formed on the third interlayer insulating film 28 by, for example, a CVD method so as to fill the groove 13. Is deposited. Then, by etching back the entire surface of the conductive material film until the surface of the third interlayer insulating film 28 is exposed, the diffusion layer 1 is formed in the logic region 20a.
A buried conductive layer 14 of W connected to the semiconductor substrate 3 at one position via the metal silicide layer 8 is obtained.

Next, as shown in FIG. 6F, a fourth interlayer insulating film 29 is formed on the third interlayer insulating film 28 in the logic region 20a and the memory cell region 20b. Subsequently, formation of a dummy pattern (not shown) in the logic region 20a and C
By flattening the surface of the fourth interlayer insulating film 29 by the MP method, the logic region 20a and the memory cell region 2 are flattened.
0b (global step) is reduced.

Next, a resist pattern (not shown) is formed on the fourth interlayer insulating film 29 by a lithography technique, and anisotropic etching is performed using the resist pattern as a mask. As a result, a contact hole 30a is opened so as to reach the buried conductive layer 14 in the fourth interlayer insulating film 29 in the logic region 20a, and the fourth interlayer insulating film 29 and the third interlayer insulating film in the peripheral portion of the memory cell region 20b. 28, the plate electrode 2 of the capacitor 27;
A contact hole 31a is opened so as to reach 7c. The above-described anisotropic etching is performed using, for example, a fluorocarbon-based gas.

After removing the resist pattern, for example,
A conductive material film (not shown) made of a W film is deposited on the fourth interlayer insulating film 29 in a state of filling the contact holes 30a and the contact holes 31a by CVD. Then, the W-plug 30 connected to the buried conductive layer 14 in the logic region 20a is obtained by etching back the entire surface of the conductive material film until the surface of the fourth interlayer insulating film 29 is exposed. At the same time, the memory cell region 20b
Then, a W-plug 31 connected to the plate electrode 27c is obtained.

Thereafter, a wiring 32 (see FIG. 4) for connecting to the contact portions 30 and 31 is formed of, for example, Al on the fourth interlayer insulating film 29 in the logic region 20a and the memory cell region 20b by the existing wiring technology. Thus, a CMOSFET circuit in the logic area 20a is obtained. Through the above steps, the semiconductor device 20 according to the second embodiment including the logic region 20a and the memory cell region 20b of the DRAM 34 is manufactured.

In the semiconductor device 20 manufactured as described above, the capacitor insulating film 27b of the capacitor 27 of the DRAM 34 is formed of a NO film formed by a high-temperature process. Therefore, when forming the capacitor 27 in the memory cell region 20b, the metal silicide layer 8 already formed on the semiconductor substrate 3 in the logic region 20a is formed.
Is exposed to a high temperature, so that the resistance tends to increase in the thin line portion of the metal silicide layer 8.

However, in the logic region 20a, since the buried conductive layer 14 serving as BMD is formed on the metal silicide layer 8 formed on the surface layer of the diffusion layer 11, the buried conductive layer 14 Resistance has been reduced. Further, since the buried conductive layer 14 is made of W having much lower resistance than the diffusion layer 11, the resistance of the buried conductive layer 14 can be reduced. Therefore, the NMOSFET 2 and the PMOSF in the logic region 20a
The parasitic resistance of ET can be reduced.

The semiconductor substrate 3 and the buried conductive layer 14
Is formed over the entire region of the diffusion layer 11, so that the contact area of the buried conductive layer 14 with respect to the semiconductor substrate 3 is increased as compared with the related art, as in the first embodiment. . Further, since a high concentration of impurities is introduced into the diffusion layer 11, the specific resistivity (ρc) of the diffusion layer 11 is also reduced. As a result, the contact resistance between the semiconductor substrate 3 and the buried conductive layer 14 in the logic region 20a can be reduced. The contact resistance between the buried conductive layer 14 and the metal silicide layer 8 is determined by the metal silicide layer 8 and the semiconductor substrate 3.
Sufficiently lower than the contact resistance between Therefore, according to the second embodiment, it is possible to realize the semiconductor device 20 in which the logic element 33 operating at a high speed and the memory cell of the DRAM 34 are mixed.

Conventionally, in a semiconductor device in which a DRAM memory cell having a stacked capacitor and a logic element are mixedly mounted, a step between the position of a plate electrode at the periphery of the memory cell and the position of a diffusion layer of the logic element is reduced. It is very large. Therefore, in the contact hole formed in the interlayer insulating film covering the capacitor, the one reaching the upper surface of the plate electrode of the capacitor is shallow, and the one reaching the diffusion layer of the logic element is deep. Therefore, since it is difficult to form these contact holes under the same conditions, conventionally, they are separately formed.

However, in the semiconductor device 20 of the second embodiment, the second interlayer insulating film 25 in the memory cell region 20b
Although the stacked capacitor 27 is provided thereon, the third interlayer insulating film 28, the second interlayer insulating film 25, and the first interlayer insulating film 23 formed above the capacitor 27 The connected buried conductive layer 14 is formed. Therefore, the diffusion layer 11 in the logic region 20a
Is pulled up to the upper surface of the buried conductive layer 14 (the upper surface of the third interlayer insulating film 28). The height difference between the upper surface position of the buried conductive layer 14 and the upper surface position of the plate electrode 27c in the periphery of the capacitor 27 in the memory cell region 20b is very small. Therefore, the semiconductor device 20 has a reduced level difference between the logic region 20a and the memory cell region 20b.

Therefore, the depth of W-plug 30 connected to buried conductive layer 14 formed in logic region 20a and the depth of W-plug 31 connected to plate electrode 27c formed in memory cell region 20b are determined. Can be made substantially equal. As a result, the formation of the contact holes 30a and 31a for obtaining the W-plugs 30 and 31 can be performed in the same step, and the fine processing of the contact holes 30a and 31a can be easily performed. The number can be reduced and higher integration can be achieved.

Since the NO film is used for the capacitor insulating film 27c, the capacitor insulating film 27c can be formed stably on the surface of the three-dimensional node electrode 27a.
Therefore, a highly reliable semiconductor device 20 including the highly integrated DRAM 34 can be obtained.

[0073]

As described above, in the semiconductor device according to the present invention, since the buried conductive layer, which is a BMD, is provided on the semiconductor substrate at the diffusion layer position via the metal silicide layer, the fine line of the metal silicide layer is formed. Even if the resistance increases in a portion, the resistance of the diffusion layer can be reduced by the buried conductive layer, and the parasitic resistance can be reduced. In addition, since the metal silicide layer is formed over the entire diffusion layer, the contact area of the buried conductive layer with respect to the semiconductor substrate is increased, so that the contact resistance between the semiconductor substrate and the buried conductive layer is reduced. it can. Therefore, a semiconductor device which operates at high speed can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional side view of a main part showing a first embodiment of a semiconductor device according to the present invention.

FIGS. 2A to 2C are main-part side sectional views showing a method of manufacturing the semiconductor device of the first embodiment in the order of steps (part 1);

FIGS. 3D and 3E are main-part side sectional views showing a method of manufacturing the semiconductor device of the first embodiment in the order of steps (part 2);

FIG. 4 is a side sectional view showing a main part of a second embodiment of the semiconductor device according to the present invention;

FIGS. 5A to 5D are cross-sectional views of a main part showing a method of manufacturing a semiconductor device according to a second embodiment in the order of steps (part 1).

FIGS. 6 (e) and 6 (f) are cross-sectional views of essential parts showing a method of manufacturing a semiconductor device according to the second embodiment in the order of steps (part 2).

FIG. 7A is a cross-sectional view of a main part for explaining a conventional salicide structure, and FIG. 7B is a cross-sectional view of a main part for explaining a BMD.

[Explanation of symbols]

1, 20 semiconductor device, 3 semiconductor substrate, 7, 21 gate electrode, 8 metal silicide layer, 11 diffusion layer, 12
... insulating film, 13 ... groove, 14 ... buried conductive layer, 20a ...
Logic region (first region), 20b ... memory cell region (second region), 23 ... first interlayer insulating film, 25 ... second interlayer insulating film, 27 ... capacitor, 27b ... capacitor insulating film, 28 ... third interlayer Insulating film, 34 ... DRAM

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/108 H01L 27/10 681F 21/8242

Claims (8)

[Claims] A linear gate electrode formed on a semiconductor substrate; a diffusion layer formed on a surface of the semiconductor substrate on both sides of the gate electrode; and the diffusion layer insulated from the gate electrode. A metal silicide layer formed over the entire surface layer of; an insulating film formed on the semiconductor substrate so as to cover at least the gate electrode and the metal silicide layer; and the insulating film on the metal silicide layer. A semiconductor device comprising: a groove formed along a length direction of the gate electrode and reaching a depth reaching the metal silicide layer; and a buried conductive layer buried in the groove. 2. The semiconductor substrate according to claim 1, wherein
2. The semiconductor device according to claim 1, further comprising a first region provided with the metal silicide layer, and a second region formed at a position avoiding the first region. 3. The semiconductor device according to claim 2, wherein said second region comprises a memory cell region of a dynamic access random memory. 4. The dynamic access random memory capacitor according to claim 3, wherein the capacitor insulating film is formed of a silicon oxide film, a silicon nitride film, or a composite film of a silicon oxide film and a silicon nitride film. 13. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein said buried conductive layer is made of tungsten. 6. The semiconductor device according to claim 2, wherein said buried conductive layer is made of tungsten. 7. The semiconductor device according to claim 3, wherein said buried conductive layer is made of tungsten. 8. The semiconductor device according to claim 4, wherein said buried conductive layer is made of tungsten.