JPH11176150A - Memory controller and image formation apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use an auxiliary power supply exclusively to hold data (an electric charge) in a memory even when the main power supply of the memory is turned off by a short break or the like and to suppress the power consumption of the auxiliary power supply. SOLUTION: An image formation apparatus is provided with an image acquisition means 1 which reads an image in an original, with a DRAM 2 which stores image data Din to be read by the image acquisition means 1 and which requires a refresh operation, with a memory controller 10 which controls the data write operation and the data read operation of the DRAM 2 and with an image reproduction means 3 which reproduces an image on the basis of image data Dout which is read by the memory controller 10. The memory controller 10 is provided with a backup battery 11, with a voltage detection circuit 12 which detects a power-supply voltage VCC to be supplied to the DRAM 2 from at least a main power supply 4 and with a DRAM control circuit 13 which controls the backup operation of the DRAM 2 on the basis of a voltage detection signal S1 by the voltage detection circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device and an image forming apparatus suitable for use in a digital copying machine for temporarily storing image data obtained from a document image in a memory and performing image processing and the like.

More specifically, when a memory requiring a refresh operation is provided at regular intervals, and when the main power of the memory is turned off due to an instantaneous interruption or the like, data is rewritten in this memory, By switching the power supply of the memory from the main power supply to the auxiliary power supply, the auxiliary power supply can be used exclusively for retaining data (charge) of the memory, and the power consumption of the auxiliary power supply can be suppressed. is there.

[0003]

2. Description of the Related Art Recently, digital copiers for forming an image based on image data obtained from a document image have been increasingly used. In this type of copying machine, an image of a document is read by a CCD image pickup device or the like, and image data of the document is temporarily stored in a memory. The image data stored in the memory is subjected to image processing such as reduction, enlargement, and rotation of the image in response to a request from the user. Thus, the image of the original can be copied onto a predetermined transfer sheet based on the image data on which the image processing has been performed.

In this type of digital copying machine, a large-capacity memory is required to temporarily store image data of a document. An SRAM or DRAM is suitable for this memory. Since the SRAM is constituted by a flip-flop circuit, data can be stably held as long as power is supplied. However, SRAM is expensive.

For this reason, a digital copying machine often uses a DRAM whose bit unit price is easy. A DRAM is composed of, for example, a capacitor that holds data (charge) and a MOS transistor that charges and discharges the charge with respect to the capacitor. The electric charge charged in this capacitor is held for about 10 ms when the MOS transistor is turned off, but is discharged beyond that. Therefore, in order to retain data, an operation of replenishing charges (rewriting data) at regular intervals is required. This operation is called refresh. Therefore, when the main power supply of the memory is momentarily interrupted, data cannot be held continuously.

That is, when the main power supply of the memory is cut off, a power supply switching operation for switching to a backup battery as an auxiliary power supply and a refresh operation for rewriting data are required.

[0007]

In order to perform the power switching operation and the refresh operation, a memory control device is provided in the conventional image forming apparatus. For example, when the main power of the memory is cut off, the memory controller is switched to a backup battery. Later, a memory refresh operation is performed.

Therefore, the power for performing the refresh operation of the memory and the power used for fixing the row address strobe signal and the column address strobe signal at a fixed period of potential must be supplied from the backup battery. No.

For this reason, a backup battery cannot be used exclusively for retaining data (charge) in the memory. As a result, the power consumption of a backup battery (hereinafter also referred to as an auxiliary power supply) increases, and thus there is a problem that a large-capacity auxiliary power supply must be provided.

Therefore, the present invention solves such a conventional problem. Even when the main power supply of the memory is turned off due to an instantaneous interruption or the like, an auxiliary power supply is exclusively used for retaining data (charge) of the memory. It is an object of the present invention to provide a memory control device and an image forming apparatus that can use the memory control device and suppress the useless power consumption.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus for controlling a memory which requires a refresh operation for holding data, which detects an auxiliary power supply and at least a voltage supplied from the main power supply to the memory. Detecting means, and control means for controlling data writing and reading of the memory based on the voltage detection information by the detecting means. When the main power supply of the memory is detected to be turned off, the control means The problem is solved by a memory control device characterized in that the power supply of the memory is switched from the main power supply to the auxiliary power supply after rewriting data.

According to the memory control device of the present invention, for example, when the main power supply is cut off while image data is being stored, the main power supply is actually switched from the time when the main power supply of the memory is cut off. Until the time when the power is switched to the auxiliary power, data can be rewritten (self-refresh operation) in the memory by using the remaining charge of the electrolytic capacitor or the like provided in the main power.

At the same time, the time at which the main power supply is actually switched to the auxiliary power supply can be delayed from the time at which the main power supply of the memory is cut off. Therefore, since the auxiliary power supply can be used exclusively for holding data (charge) in the memory, consumption of the auxiliary power supply can be suppressed.

Thus, even when the main power is turned off due to a sudden momentary interruption or the like, data can be backed up by an auxiliary power having a small facility capacity.
Therefore, this memory control device can be applied to a DRAM backup circuit and the like.

An image forming apparatus according to the present invention includes an image acquisition unit for reading an image of a document, a memory that requires a refresh operation for storing image data read by the image acquisition unit, and data writing and reading control of the memory. Memory control means for performing image processing based on image data read by the memory control means. The memory control means controls an auxiliary power supply and at least a voltage supplied from the main power supply to the memory. It has a voltage detection circuit for detecting, and a backup control circuit for performing backup control of the memory based on the voltage detection information by the voltage detection circuit.

According to the image forming apparatus of the present invention, since the above-described memory control device is applied, for example, when the voltage detection circuit detects that the main power supply of the memory has been cut off, the data is re-stored in the memory. After writing, the power supply of the memory can be switched from the main power supply to the auxiliary power supply.

Therefore, an operation of shifting to data retention in the memory can be performed by utilizing the remaining charge of the electrolytic capacitor or the like provided in the main power supply. At the same time, since the auxiliary power supply can be used exclusively for holding the charge of the memory, the power consumption of the auxiliary power supply can be suppressed.

Thus, even if the main power supply is cut off due to a sudden momentary interruption or the like, image data can be backed up by an auxiliary power supply having a small facility capacity. This prevents the loss of valuable image data read for image editing processing and the like. Therefore, re-reading of the document can be avoided, so that office efficiency can be improved and the document can be prevented from being stained.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a memory control device and an image forming apparatus according to the present invention will be described with reference to the drawings.

(1) First Embodiment FIG. 1 is a block diagram showing a configuration of an image forming apparatus 100 to which a memory control device 10 as a first embodiment is applied.

In this embodiment, a memory that requires a refresh operation is provided. When the main power of the memory is turned off due to an instantaneous interruption or the like, data is rewritten and then the power of the memory is turned off. By switching from the main power supply to the auxiliary power supply, the auxiliary power supply can be used exclusively for holding data (charge), and unnecessary power consumption can be suppressed.

The image forming apparatus 100 is provided with an image acquiring means 1 shown in FIG. 1, and outputs image data Din after reading an image of a document. This image acquisition means 1 has a DRAM (D
dynamic-Random Access Memory) 2 is connected, and the image data Din read by the image acquisition unit 1 is temporarily stored. The image reproducing means 3 is connected to the output stage of the DRAM 2, and the image data Dou read out from the DRAM 2.
An image is formed based on t.

A memory control device 10 is connected to the DRAM 2 to write data into the DRAM 2 and to store data in the DRAM 2.
Reading of data from the RAM 2 is controlled, and D
The backup control of the RAM 2 is performed. The memory control device 10 includes a backup battery 11 as an auxiliary power source,
It has a voltage detection circuit 12 as voltage detection means, a DRAM control circuit 13 as a backup control circuit, and a power supply switching circuit 14.

The main power supply 4 of the DRAM 2 is connected to one input stage of the power supply switching circuit 14. The output voltage of the main power supply 4 is about 5V. Thousands to tens of thousands of μF for main power supply 4
A relatively large capacitance C is connected. A backup battery 11 is connected to the other input stage of the power supply switching circuit 14, and a minimum voltage required for holding data in the DRAM 2 is supplied. Although depending on the memory capacity of the DRAM 2, the backup battery 11 has a Ni-Cd of about 3 V and about 90 mAh.
A battery (secondary battery) is used.

A power switch SW is connected to an input stage of the main power supply 4, and a voltage detection circuit 12 is connected to an output stage thereof. When the power switch SW is turned on, the main power supply 4
From the power supply voltage VCC to the DRAM 2
After detecting this voltage, the voltage detection signal S1 is output from the voltage detection circuit 12. A DRAM control circuit 13 is connected to an output stage of the voltage detection circuit 12, and in this example, write / read control of the DRAM 2 and backup control thereof are performed based on the voltage detection signal S1.

The DRAM control circuit 13 is provided with a timing generation circuit 31 shown in FIG. 2, for example, a refresh request signal S3, a self-refresh request signal S4, a write request signal S5 and a read request signal S3 from a microcomputer 5 as a higher-level control means. Based on the request signal S6, the voltage detection signal S1 from the voltage detection circuit 12, and the clock signal CLK, the access prohibition signal S7 and the dummy access setting signal S
8. Write enable signal WE and address control signal S
10 etc. are generated.

The refresh request signal S3 is a signal for requesting the DRAM 2 to perform a refresh operation from the microcomputer 5 during a normal operation or the like. The self-refresh request signal S4 is a signal for requesting the DRAM 2 to perform a self-refresh before shifting to a normal operation or at the time of a momentary interruption. The write request signal S5 is a signal for requesting the DRAM 2 to write data from the microcomputer 5 for normal operation, and the read request signal S6 is a signal for requesting the DRAM 2 to read data similarly.

A refresh control unit 32 is provided in the timing generation circuit 31. Refresh control unit 3
2 has a one-shot timer 21, a dummy access counter 22, and a refresh counter 23 shown in FIG.

Before shifting to the normal operation, the one-shot timer 21 generates an access prohibition signal S7 based on the clock signal CLK, the self-refresh request signal S4 and the voltage detection signal S1. This clock signal CLK is DRA
This is a reference signal for controlling the timing of M2. The access prohibition signal S7 is output to the write / read control circuit 33 and the dummy access counter 22. This signal S7 prohibits any access to the DRAM 2 before the transition to the normal operation.

The dummy access counter 22 generates a dummy access setting signal S8 based on the clock signal CLK and the access prohibition signal S7. This signal S8 is output to the refresh counter 23 and the write / read control circuit 33. A dummy access cycle is set by this signal S8, and the DRAM 2 is refreshed.

In the dummy access cycle of this example, the row address strobe signal (hereinafter referred to as RA
The period of the RAS signal and the CAS signal during the refresh operation is set shorter than the period of the S signal) and the period of the column address strobe signal (hereinafter referred to as the CAS signal).

The refresh counter 23 generates an initialization end signal S9 based on the clock signal CLK and the dummy access setting signal S8. This signal S9 is output to the microcomputer 5. It can be recognized from this signal S9 that the dummy access cycle has been completed.

Returning to FIG. 2, a write / read control circuit 33 is connected to the output stage of the timing generation circuit 31, and generates a RAS signal and a CAS signal based on the access inhibition signal S7 and the dummy access setting signal S8. The RAS signal and the CAS signal are output to the DRAM 2.

A first two-input NAND circuit (hereinafter, referred to as a NAND circuit) 35 is connected to the output stage of the write / read control circuit 33, and a self-operating circuit after taking the NAND of the RAS signal and the CAS signal. Refresh status signal S11 is generated. An output stage of the NAND circuit 35 has a second two-input NAND circuit (hereinafter referred to as NAND).
The power supply switching signal S2 is obtained by taking the NAND of the self-refresh status signal S11 and the inverted voltage detection signal S1 bar (the upper line is omitted). The inverted voltage detection signal S1 bar is obtained by inverting the voltage detection signal S1 by the inverter 36. This signal S2 is output to the power supply switching circuit 14.

In addition to these signals S2, RAS and CAS, the timing generator 31 generates a clock signal CLK,
Based on the write request signal S5 and the read request signal S6, the write enable signal WE and the address generation signal S10
Etc. are generated. When this signal WE is output to the DRAM 2, writing of data to the DRAM 2 is permitted.

An address generator 34 is connected to the output stage of the timing generator 31, and an address control signal S
The dummy address Add ′ and the address Add for specifying the storage location of the image data Din are generated based on 10. For example, before the transition to the normal operation, the address control signal S1
When a dummy address Add ′ necessary for a dummy access cycle is generated by 0, this address Add ′ is output to the DRAM 2. Address Add during normal operation
May be supported by the micro computer 5 in some cases.

Next, the operations of the image forming apparatus 100 to which the memory control device 10 is applied at the time of power-on, normal operation, and power-off will be described with reference to FIGS.

Operation at Power-On FIG. 4 is a time chart showing an operation example (at power-on) of the image forming apparatus 100 according to the present embodiment. In this example, when the power switch SW shown in FIG.
AM2 is backed up by the backup battery 11. When the power switch SW is turned on in FIG. 4A, the main power 4
Supplied to

The power supply voltage VCC shown in FIG. 4C is raised by the main power supply 4, so that the power supply voltage VCC is detected by the voltage detection circuit 12. Therefore, for example, when a voltage exceeding a certain threshold voltage Vth is detected, the voltage detection circuit 12 raises the voltage detection signal S1 shown in FIG. 4D.

This high-level voltage detection signal S1 is D
When output to the RAM control circuit 13, the DRAM control circuit 13 receives the low-level RAS signal shown in FIG. 4L and the low-level CAS signal shown in FIG.
The high level self-refresh status signal S11 shown in FIG. 4F is raised by the D circuit 35. In the NAND 37 to which the high-level signal S11 and the inverted voltage detection signal S1 bar are input, the power supply switching signal S2 shown in FIG. 4G rises.

When this high-level signal S2 is output to the power supply switching circuit 14,
The battery is switched from the backup battery 11 to the main power supply 4. Accordingly, the power supply of the DRAM 2 switches from the voltage VBB shown in FIG. 4H to VCC. Thereafter, the self-refresh request signal S4 shown in FIG.
4 is output to the DRAM control circuit 13. This signal S4
Is input to the write / read control circuit 33. In the timing generation circuit 31, the access prohibition signal S7 shown in FIG. At the same time, a dummy access setting signal S8 shown in FIG.

The number of data rewrites (dummy access cycle) n = 1 defined in advance by this signal S8
Regarding 024 times, for example, a method of charging electric charges at a rate of once every 200 ns is adopted.
4, n-3, n-2, n-1, and n are set, and the RAS signal shown in FIG. 4L and the CAS signal shown in FIG. 4M are generated in the write / read control circuit 33 based on the set times. The RAS signal and the CAS signal are applied to the DRAM 2
4N and the write enable signal WE shown in FIG.
Is also output to the DRAM 2.

Thus, the self-refresh operation before the shift to the normal operation is performed. When the data writing of the specified number of times is completed and the initialization of the DRAM 2 is completed,
In FIG. 4K, the initialization end signal S9 rises. This high
Since the level signal S9 is notified to the micro computer 5, the micro computer 5 confirming the end of the initialization is
Outputs a write request signal S5 to the DRAM control circuit 13. Based on the write request signal S5, the DRAM 2
Is written with the image data Din.

In this embodiment, when the DRAM 2 is initialized, the RAS signal and the CAS signal during the refresh operation are compared with the periods of the RAS signal and the CAS signal during the normal operation.
Since the signal period is set shorter, the initialization time (warm-up time) of the DRAM 2 can be reduced as compared with the conventional method. Incidentally, the conventional method employs a method of charging electric charges at a rate of once every 15 μs with respect to the number of data writings n = 1024, so that the warm-up time is long. Therefore, the start-up of the image forming apparatus 100 according to the present embodiment can be hastened.

As a result, the initialization time of the DRAM 2 can be shortened, for example, when the power supply is restarted after the AC power supply is momentarily interrupted, so that the image forming apparatus 100 can be returned to the early stage.

FIG. 5 is a time chart showing an operation example (during normal operation) of the image forming apparatus 100 according to the present embodiment. In this example, since the power switch SW shown in FIG. 1 has already been turned on, the DRAM 2 is being driven by the main power supply 4. In this case, the voltage detection signal S1 shown in FIG. 5A is fixed at a high level, the self-refresh status signal S11 shown in FIG. 5B is fixed at a high level, and the power supply switching signal S2 shown in FIG. 5C is fixed at a high level. , The self refresh request signal S4 shown in FIG. 5G is also fixed at a high level.

For example, the DRA from the microcomputer 5
When the write request signal S5 shown in FIG. 5D is input to the M control circuit 13, the write / read control circuit 33 of the DRAM control circuit 13 outputs the RAS signal shown in FIG. 5H based on the clock signal CLK and the address Add shown in FIG. 5K. The CAS signal shown in FIG. 5I is generated. The RAS signal and the CAS signal are output to the DRAM 2 together with the write enable signal WE shown in FIG. As a result, the image data Din shown in FIG.

Further, the DRA is transmitted from the micro computer 5.
When the read request signal S6 shown in FIG. 5E is input to the M control circuit 13, the write / read control circuit 33 generates the RAS signal shown in FIG. 5H and the CAS signal shown in FIG. 5I based on the clock signal CLK and the address Add. ,
Based on the RAS signal and the CAS signal, the DRAM 2
The image data Dout shown in FIG.

After that, the DR is sent from the micro computer 5.
When the refresh request signal S3 shown in FIG. 5F is input to the AM control circuit 13, the write / read control circuit 33 generates the RAS signal shown in FIG. 5H and the CAS signal shown in FIG. 5I based on the clock signal CLK and the address Add. , Based on the RAS signal and the CAS signal,
The refresh operation of the RAM 2 is performed.

As a result, the refreshed image data Dout is transferred to the D based on the read request signal S6 shown in FIG. 5E.
It can be read from the RAM 2.

FIG. 6 is a time chart showing an operation example (when power is turned off) of image forming apparatus 100 according to the present embodiment. In this example, it is assumed that while the image data Din is being read into the DRAM 2, for example, the main power supply 4 is turned off due to a momentary interruption of the commercial power supply 100V, or the power switch SW is normally turned off. In either case, DRA
When the voltage detection circuit 12 detects that the main power supply 4 of M2 has been cut off, the DRAM control circuit 13
AM2 is rewritten with data, and then
The power source 2 is switched from the main power source 4 to the backup battery 11.

That is, the power switch SW shown in FIG.
Is on, as described in normal operation,
2 is driven by the main power supply 4. Then, at time tx in FIG. 6A, the power switch SW is turned off or
When the power is turned off due to an instantaneous interruption or the like, AC10 in FIG.
0 V is not supplied to the main power supply 4.

By this power-off, the power supply voltage VCC starts to gradually decrease as shown in FIG. 6C. The power supply voltage VCC gradually decreases as the capacitance C connected to the output of the main power supply 4 increases. On the other hand, when it is detected that the power supply voltage VCC has dropped below the threshold voltage Vth, the voltage detection circuit 12 causes the voltage detection signal S1 shown in FIG. 6D to fall. This low level voltage detection signal S1 is DR
It is output to the AM control circuit 13.

On the other hand, when the power is turned off, the self refresh request signal S4 shown in FIG. 6E and the initialization end signal S9 shown in FIG. 6K from the micro computer 5 fall. This low-level self-refresh request signal S
6 is output to the DRAM control circuit 13 operated by the capacitance C of the main power supply 4, the timing generation circuit 31 receiving this signal S4 outputs the access prohibition signal S7 shown in FIG. You. At the same time, a dummy access setting signal S8 shown in FIG.

By the signal S8, the RAS signal shown in FIG. 6L and the CAS signal shown in FIG. 6M fall from the high level to the low level in the write / read control circuit 33. The RAS signal and the CAS signal are output to the DRAM 2. Thus, a self-refresh operation before switching from the main power supply 4 to the backup battery 11 is performed.

In the DRAM control circuit 13, the self-refresh status signal S11 shown in FIG. 6F falls by the NAND circuit 35 to which the low-level RAS signal shown in FIG. 6L and the low-level CAS signal shown in FIG. 6M are input. . In the NAND 37 to which the low-level signal S11 and the inverted voltage detection signal S1 bar are input,
The power supply switching signal S2 shown in FIG. 6G falls.

This low-level power supply switching signal S2
Is output from the main power supply 4 to the backup battery 1 by the power supply switching circuit 14.
Switched to 1. Therefore, the power supply of the DRAM 2 is switched from the voltage VCC shown in FIG.

As described above, according to the image forming apparatus 100 to which the memory control device 10 according to the present embodiment is applied,
A backup battery 11, a voltage detection circuit 12, a DRAM control circuit 13, and a power supply switching circuit 14 are provided. When the main power supply 4 of the DRAM 2 is cut off by the voltage detection circuit 12, data is rewritten to the DRAM 2. Later, the power supply of the DRAM 2 is switched from the main power supply 4 to the backup battery 11.

Therefore, from the time tx when the main power supply 4 of the DRAM 2 is cut off, the backup power supply 1
T (= t1−t) until time t1 when switching to T1
x), the electrolytic capacitor C provided in the main power supply 4
Data can be rewritten (self-refresh operation) in the DRAM 2 by using the remaining charges such as the above.

At the same time, the time t1 when the main power supply 4 is switched to the backup battery 11 can be delayed from the time tx when the main power supply 4 of the DRAM 2 is cut off. Therefore, since the backup battery 11 can be used exclusively for holding data (charge) in the DRAM 2, the consumption of the backup battery 11 can be suppressed.

Thus, even when the main power supply 4 is cut off due to a sudden momentary interruption or the like, the image data Din can be backed up by the backup battery 11 having a small facility capacity. As a result, it is possible to prevent the loss of the valuable image data Din read for the image editing processing or the like. Therefore, re-reading of the document can be avoided, so that office efficiency can be improved and the document can be prevented from being stained.

(2) Second Embodiment FIG. 7 is a block diagram showing the configuration of an image forming apparatus 200 to which the memory control device 10 according to the second embodiment is applied. In this example, a monitoring unit is provided to monitor the image acquiring unit 1 or the image reproducing unit 3, and these image acquiring units 1 are provided.
However, when reading is performed for a certain period of time or when the image reproducing unit 3 stops the image reproducing process for a certain period of time, the DRAM 2 is shifted to a sleep mode so that power consumption can be reduced. The components having the same names and the same symbols as those in the first embodiment have the same functions, and the description thereof will be omitted.

The image forming apparatus 200 is provided with an operation check sensor 6 as a monitoring means shown in FIG. 7. For example, when the image acquiring means 1 stops reading for a predetermined time, an image processing monitoring signal S15 is generated. . In this example, a hardware sensor for detecting whether the drive unit of the transfer paper transport system has stopped or detecting whether the scanner drive system such as a CCD image pickup device has stopped has been assumed.

Of course, if the image data Din
The image data D is not written to M2, or the image data D
It may be configured to monitor by software program whether out has not been read and generate the image processing monitoring signal S15 based on this. In any case, the image processing monitoring signal S15 is output from the sensor 6 to the microcomputer 5. Then, the image processing monitoring signal S
15, the image forming apparatus 200 shifts to the low power consumption mode by the control of the microcomputer 5.

FIG. 8 is a time chart showing the operation of the image forming apparatus 200 in the low power consumption mode. In this example, when the power switch SW shown in FIG. 1 is turned on, low power consumption occurs when data is not written to the DRAM 2 for a certain time or data is not read for a certain time. The mode shifts to the power mode. Also in this case, the DRAM 2 is driven by the main power supply 4, the voltage detection signal S1 shown in FIG. 8B is fixed at a high level, and the self-refresh status signal S1 shown in FIG.
11 is fixed at a high level, and the power supply switching signal S2 shown in FIG. 8D is also fixed at a high level.

However, the write request signal S5 shown in FIG.
When a certain time has elapsed after the input of the image processing monitor signal and the image processing monitor signal S15 is activated by the operation check sensor 6, the high-level image process monitor signal S1 shown in FIG.
5 is output to the microcomputer 5. In the microcomputer 5, the self-refresh request signal S4 falls from a high level to a low level based on the image processing monitoring signal S15. When the low-level self-refresh request signal S4 is output to the DRAM control circuit 13, the DRAM control circuit 13 causes the DRAM 2 to shift to the low power consumption mode based on the self-refresh request signal S4.

In this mode, since the main power supply 4 is not turned off, the DRAM 2 and the DRAM control circuit 13 are operated by the main power supply 4. That is, in the timing generation circuit 31 to which the self-refresh request signal S4 is input, as shown in FIG.
Is output to the write / read control circuit 33. At the same time, the dummy access setting signal S8 shown in FIG.
Is output to

The RAS signal shown in FIG. 8I and the CAS signal shown in FIG. 8J fall from the high level to the low level in the write / read control circuit 33 by the signal S8. The RAS signal and the CAS signal are output to the DRAM 2.

At this time, in the DRAM control circuit 13, the self-refresh status signal S11 shown in FIG. 8F is kept rising by the NAND circuit 35 to which the low-level RAS signal and CAS signal are inputted. In the NAND circuit 37 to which the high-level signal S11 and the inverted voltage detection signal S1 are input, the power supply switching signal S2 shown in FIG. 8D remains at the high level.

As a result, the power supply of the DRAM 2 is
The self-refresh operation in the low power consumption mode is performed without switching from the backup battery 11 to the backup battery 11. In this mode, the DRAM control circuit 13
The RAS signal and the CAS signal of AM2 are controlled so as to be fixed at a constant potential. With this control, the charge replenishment cycle becomes significantly longer than in the normal operation. When the replenishment cycle is longer than in the normal operation, the power consumption in the DRAM 2 is significantly reduced as compared with the normal operation. Thereafter, when the image processing monitoring signal S15 falls, the low power consumption mode (hereinafter also referred to as sleep mode) is released,
The self-refreshed image data Dout can be read.

As described above, according to the present embodiment, the operation monitoring sensor 6 for monitoring the image acquiring means 1 is provided, and when the image acquiring means 1 stops reading the image for a certain period of time, the micro computer 5, an image processing monitor signal S15 is output. Therefore,
The image forming apparatus 2 in which the DRAM 2 can be shifted to a so-called sleep mode and no original image is supplied
00 can be reduced.

In this embodiment, the operation check sensor 6
Although the case where the image acquisition unit 1 is monitored has been described above, the present invention is not limited to this, and the image reproduction unit 3 may be monitored. This also provides the same effect.

(3) Embodiment of Image Forming Apparatus FIG. 9 is a block diagram showing an example of the overall configuration of a digital copying machine 300 to which the image forming apparatus 100 according to the present embodiment is applied. In this example, a copying machine 300 capable of copying images on the front and back (both sides) of a document on the front and back of a transfer sheet 30 will be described.

The copying machine 300 has a data bus 8 shown in FIG. 9, and is provided with image data Din / Dout, a refresh request signal S3, a self-refresh request signal S4,
Control signals such as a write request signal S5, a read request signal S6, and an initialization end signal S9 are transferred. This data bus 8
Is connected to an operation unit 7, and the number of copies, enlargement and reduction ratios, and copy sheets (A3, A4, A4R, B4, B5, B5
R) and the like can be selected and designated.

As the image acquiring means 1 shown in FIG. 1, an automatic document feeder (ADF) 40, an image reading section 50 and an image signal processing section 15 shown in FIG. 9 are provided. The automatic document feeder 40 is electrically connected to the data bus 8 and is automatically fed so that images on both sides of the document can be read by an instruction from the operation unit 7.

The data bus 8 includes an image signal processing unit 15
The image reading unit 50 is connected via the. The image reading section 50 reads the image of the document, and outputs the image acquisition signal Sin to the image signal processing section 15. The image signal processing unit 15 converts the image acquisition signal Sin into digital data, and converts the image data Din through the data bus 8 into the DR.
It is temporarily stored in AM2. This DRAM 2 is controlled by the memory control device 10 described above.

The image reproducing means 3 shown in FIG. 1 includes a recorded image processing section 16, an image writing section 60, and an image forming section 70. The recording image processing unit 16 is connected to the data bus 8 described above, and performs, for example, image processing such as enlargement, rotation, and editing in order to record (image reproduction) the image data Dout read from the DRAM 2.

An image writing section 60 having an optical drive system is connected to the output stage of the recording image processing section 16, and an electrostatic latent image of a document is formed on a photosensitive drum by the optical drive system. The image forming unit 7 is located below the image writing unit 60.
0 is provided, and the toner image after the electrostatic latent image on the photosensitive drum is developed and transferred to the transfer paper is fixed. The image forming unit 70 will be described in detail with reference to FIG.

Further, the microcomputer 5 is connected to the above-mentioned data bus 8, and the input and output of the image acquisition unit 1, the image reproduction unit 3, the operation unit 7, and the memory control device 10 are centrally controlled. For example, the microcomputer 5 includes a mode analysis unit 81, a management data holding unit 82, an ADF control unit 8
3, a reading control unit 84, a recording control unit 85, and a finisher control unit 86.
1. Management data holding unit 82 and control units 83 to 86
Are connected to the data bus 8.

The mode analysis unit 81 determines the operation mode analyzed from the selection and designation operation from the operation unit 7. The management data holding unit 82 holds management data necessary for image reading control and recording control based on the operation mode. The ADF controller 86 controls the input / output of the automatic document feeder 40 based on the operation mode.
In 4, the input / output of the image reading unit 50 is controlled based on the analysis result of the mode analysis unit 81. The recording control unit 85 receives the analysis result of the mode analysis unit 81, and
The finisher control unit 86 controls the input and output of the finisher unit 90 in response to the analysis result of the mode analysis unit 81.

FIG. 10 is a diagram showing an example of a cross-sectional configuration of the copying machine 300. The above-described automatic document feeder 40 has a document placing portion 41, rollers 42a, 42b, rollers 43, a reversing roller 44, a reversing portion 45, and a discharge tray 46 shown in FIG.

The image reading section 50 includes a first platen glass 51, a second platen glass 52, a light source 53,
It has mirrors 54, 55, 56, an imaging optical system 57, a CCD imaging device 58, and an optical drive system (not shown). The image forming unit 70 includes a photosensitive drum 71, a charging unit 72, and a developing unit 7.
3, a transfer section 74, a separation section 75, a cleaning section 76, a transport mechanism 77, and a fixing section 78.

For example, a plurality of originals 20 are placed on the original placing portion 41 with the surface of the first page of the original facing upward. When the rollers 42 a and 42 b are driven under the control of the ADF control unit 83, the first sheet of the original 20 fed out via the rollers 42 a and 42 b is conveyed via the rollers 43.

At this time, light is emitted from the light source 53 of the image reading unit 50 to the image surface of the document 20 according to a control command from the reading control unit 84. The reflected light is guided by mirrors 54, 55 and 56, and the reflected light is taken into the CCD image pickup device 58 via the imaging optical system 57. Thereby, the original 2 is placed on the light receiving surface of the CCD image pickup device 58.
0 image is formed.

Here, the original 20 is placed on the platen glass 51.
When the original 20 is placed on the original placing portion 41 with the reading surface of the document facing downward, the optical drive system scans the image reading portion 50 along the platen glass 51 to thereby capture the CCD image. It is taken into the device 58.

Then, the read image acquisition signal Sin of the document 20 is transferred from the CCD image pickup device 58 to the image signal processing section 15 shown in FIG. In the image signal processing unit 15, the image data Din obtained by converting the image acquisition signal Sin into digital data is temporarily stored in the DRAM 2 through the data bus 8.

The DRAM 2 is controlled by the memory control device 10 described above. Therefore, even if the main power is turned off due to an instantaneous interruption or the like, the image data Din can be backed up, so that valuable image data Din read for image editing processing can be prevented from being lost. In the operation mode in which the document 20 is automatically fed, the document 20 rotates around the roller 43. In this case, the image of the document is read by the image reading unit 50 with the light source 53 and the mirror 54 fixed below the second platen glass 52.

Then, when the first page of the original 20 is read, the roller 43 is again turned through the reversing roller 44 this time.
Is performed, the image on the back side of the document is read by the image reading unit 50, and the image acquisition signal Sin is output to the image signal processing unit 15.

The original 20 whose front and rear images have been read in this way is again inverted by the reversing roller 44 and stacked on the paper output tray 46 with the front surface facing downward. At the same time, after the image acquisition signal Sin read by the image reading unit 50 is converted into digital image data Din by the image signal processing unit 15, the DRAM shown in FIG.
2 is stored.

On the other hand, the transfer paper 30 is fed out from the paper feed cassette 30a or 30b on which the transfer paper 30 is stacked and fed to the image forming unit 70. The transfer paper 30 comes closer to the photosensitive drum 71 after synchronization is established by the registration roller 61 at the entrance.

In this state, the image data Dout read from the DRAM 2 is output to the image writing section 60 after being subjected to image processing by the recording image processing section 16. The image data Dout is read from the recording image processing unit 16 first from the back surface of each document 20. In the image writing section 60, a laser beam corresponding to the image data Dout is emitted from the laser diode onto the photosensitive drum 71, so that an electrostatic latent image of the document 20 is formed on the photosensitive drum 71. After the electrostatic latent image is developed by the developing unit 73, the photosensitive drum 71
A toner image is formed thereon.

This toner image is transferred to the transfer paper 30 by a transfer section 74 provided below the photosensitive drum 71. At this time, the transfer paper 30 is attracted to the photosensitive drum 71. Then, the transfer paper 3 adsorbed on the photosensitive drum 71
0 is separated from the photosensitive drum 71 by the separation unit 75. Thereafter, the transfer paper 3 separated from the photosensitive drum 71
0 is sent to the fixing unit 78 via the transport mechanism 77, and the toner image is fixed by heat and pressure. As a result, an image of the back surface of the document (second page image) is formed on the transfer paper 30.

The transfer paper 30 on which the toner image has been fixed is conveyed downward through a guide 91 and sent to a reversing unit 93. Next, the transfer paper 30 sent to the reversing unit 93 is again fed upward by the reversing roller 92, and is again transferred to the image forming unit 70 through the reversing conveyance path 94 provided on the sheet cassette 30a. You.

In the image forming section 70 where the image formation on the back side of the original 20 has been completed, the toner remaining on the photosensitive drum 71 is removed by the cleaning section 76, and the apparatus stands by to cope with the next image formation. .

In this state, the transfer paper 30 is sent to the image forming unit 70 via the registration roller 61 with the surface of the transfer paper 30 (the surface on which no image is formed) facing upward. In the image forming unit 70, an electrostatic latent image on the surface of the document is formed on the photosensitive drum 71, and the electrostatic latent image is developed by the developing unit 73, so that a toner image on the surface of the document is formed on the photosensitive drum 71. You.

Since this toner image is transferred to the transfer paper 30 by the transfer section 74, an electrostatic latent image of the first page is formed on the surface thereof. Transfer paper 3 adsorbed on photoconductor drum 71
0 is separated from the photosensitive drum 71 by the separation unit 75 and then sent to the fixing unit 78 via the transport mechanism 77.
The toner image is fixed by heat and pressure. This allows
An image (first page image) of the document surface can be formed on the transfer paper 30.

Thereafter, the transfer paper 30 on which image formation is completed on the back and front surfaces of the transfer paper 30 is discharged to the outside as it is in the finisher unit 90 in accordance with the output form (operation instruction such as a sorter function). Alternatively, the sheet is reversed again by the reversing section 93 and discharged outside the apparatus by the discharge roller 95. Thus, the images on the front and back (both sides) of the document 20 can be copied on the front and back of the transfer paper 30.

As described above, according to the digital copying machine 300 to which the image forming apparatus 100 is applied, the DRAM 2 which is backed up by the memory control device 10 is provided.

Therefore, even when the main power is turned off due to a momentary interruption or the like, the image data Din in the DRAM 2 can be backed up, so that the image editing processing (enlargement, reduction,
Precious image data Din read for double-sided copying) can be prevented from being lost. This makes it possible to provide the digital copying machine 300 having high reliability and high image editing function.

[0100]

As described above, according to the memory control device of the present invention, the control means for performing data write and read control based on the information on the voltage supplied from the main power supply to the memory is provided. When it is detected that the main power supply has been cut off, the data is rewritten in the memory, and then the power supply of the memory is switched from the main power supply to the auxiliary power supply.

With this configuration, even when the main power supply is turned off due to an instantaneous interruption or the like, the self-refresh operation of the memory can be performed by utilizing the remaining charge of the electrolytic capacitor or the like provided in the main power supply. it can. At the same time, the auxiliary power supply can be used exclusively for holding the data (charge) of the memory, so that the consumption of the auxiliary power supply can be suppressed. Therefore, this memory control device can be applied to a DRAM backup circuit and the like.

Further, according to the image forming apparatus of the present invention, since the above-mentioned memory control device is applied, even if the main power supply is cut off due to a sudden momentary interruption or the like, a small amount of auxiliary capacity can be provided. Image data can be backed up by a power supply. This prevents the loss of valuable image data read for image editing processing and the like.
Therefore, re-reading of the document can be avoided, so that office efficiency can be improved and the document can be prevented from being stained.

The present invention is very suitable when applied to a digital copying machine which temporarily stores image data obtained from a document image in a memory and performs image editing processing and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an image forming apparatus 100 to which a memory control device 10 according to a first embodiment is applied.

FIG. 2 is a diagram showing an example of an internal configuration of a DRAM control circuit 13;

FIG. 3 is a diagram showing an example of an internal configuration of a refresh control unit 32 of the timing generation circuit 31.

FIG. 4 is an operation time chart illustrating an operation example (when power is turned on) of the image forming apparatus 100.

FIG. 5 is an operation time chart illustrating an operation example (during normal operation) of the image forming apparatus 100.

FIG. 6 is an operation time chart illustrating an operation example (when the power is off) of the image forming apparatus 100.

FIG. 7 is a block diagram illustrating a configuration example of an image forming apparatus 200 according to a second embodiment.

FIG. 8 is an operation time chart illustrating an operation example of the image forming apparatus 200 in the low power consumption mode.

FIG. 9 is an overall block diagram illustrating a configuration example of a digital copying machine 300 to which the image forming apparatus 100 according to the present embodiment is applied.

FIG. 10 is a diagram illustrating a configuration example of a cross section of the digital copying machine 300;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image acquisition means 2 DRAM 3 Image reproduction means 4 Main power supply 6 Operation check sensor 7 Operation unit 10 Memory control device 11 Backup battery 12 Voltage detection circuit 13 DRAM control circuit 14 Power supply switching circuit 31 Timing generation circuit 32 Refresh control unit 33 Write / read Control circuit 34 Address generation unit 35, 37 Two-input NAND circuit 70 Image forming unit 100, 200 Image forming apparatus

Claims (6)

[Claims] 1. An apparatus for controlling a memory that requires a refresh operation for holding data, comprising: an auxiliary power supply; a detecting means for detecting at least a voltage supplied from a main power supply to the memory; Control means for performing data write and read control of the memory based on voltage detection information, wherein the control means rewrites data to the memory when it is detected that main power of the memory is cut off. And after switching the power supply of the memory from a main power supply to an auxiliary power supply. 2. An image acquisition unit for reading an image of a document, a memory that requires a refresh operation for storing image data read by the image acquisition unit, and a memory control unit that controls data writing and reading of the memory. An image reproducing unit that reproduces an image based on the image data read by the memory control unit, wherein the memory control unit detects an auxiliary power supply and at least a voltage supplied from the main power supply to the memory. An image forming apparatus comprising: a voltage detection circuit; and a backup control circuit that performs backup control of the memory based on voltage detection information from the voltage detection circuit. 3. When a backup control circuit for the memory is provided, the backup control circuit rewrites data to the memory when it is detected that the main power supply of the memory is cut off. 3. The image forming apparatus according to claim 2, wherein a power supply of said memory is switched from a main power supply to an auxiliary power supply. 4. A backup control circuit for the memory, wherein the backup control circuit performs a refresh operation after a main power supply of the memory is turned on and before the memory is shifted to a normal operation. When the cycle of the row address strobe signal and the column address strobe signal during the refresh operation is set shorter than the cycle of the row address strobe signal and the column address strobe signal during the normal operation of the memory. The image forming apparatus according to claim 2, wherein the image forming apparatus is configured to perform the operation. 5. When the memory, the image acquisition unit, and the memory control unit are provided, a monitoring unit that monitors the image acquisition unit is provided, and the image acquisition unit stops reading processing for a predetermined time. 3. The image forming apparatus according to claim 2, wherein said memory control means fixes a row address strobe signal and a column address strobe signal of said memory at a constant potential. 6. When the memory, the image reproducing unit, and the memory control unit are provided, a monitoring unit that monitors the image reproducing unit is provided, and the image reproducing unit stops the image reproducing process for a predetermined time. 3. The image forming apparatus according to claim 2, wherein said memory control means fixes a row address strobe signal and a column address strobe signal of said memory at a constant potential.