JPH11163316A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a stable field-effect transistor having two-stepped recessed structure formed onto an InP substrate and displaying stable device performance and particularly low contact resistance, and a manufacture having excellent controllability of the field-effect transistor. SOLUTION: A field-effect transistor is manufactured in such a manner that a channel layer 103, electron supply layers 104, 105, an undoped InAlAs Schottky layer 106, an n-type InAlAs first cap layer 107 and an n-type InGaAs second cap layer 108, are formed successively onto an InP substrate 101, etching is made to reach the layer just as deep as the surface of the above-mentioned Schottky layer from the surface of the second cap layer. Or a part of the above- mentioned Schottky layer is removed and a second recessed opening 111 is formed in a specified shape, and the opening 110 of a first recess is formed in a specified shape by side-etching the second cap layer by using an etchant having a selection ratio of InGaAs to InAlAs of 30 or more.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor operating in a microwave / millimeter wave region,
In particular, it relates to a field effect transistor having a two-stage recess structure.

[0002]

2. Description of the Related Art In recent years, attention has been paid to ternary and quaternary mixed crystal semiconductors such as InGaAs and InGaAsP. Among them, InGaAs lattice-matched to an InP substrate is not only an optical device but also various field effect transistor materials. In particular, field-effect transistors using a two-dimensional electron gas at a heterointerface with InP or InAlAs have been actively studied.

[0003] The reason why InGaAs is also considered promising as an electron transport device is that, compared to GaAs or the like, the peak value of the electron drift velocity is large, and the mobility of the electron in a low electric field is large. thing,
Easy contact with ohmic electrodes, low contact resistance, greater overshoot of electron velocity, less noise due to valley scattering,
One of the major reasons is that the interface characteristics with the insulator are relatively good, and that the above-described two-dimensional electron gas device can be realized.

At present, a field effect transistor using a two-dimensional electron gas at the InAlAs / InGaAs interface is regarded as a promising high-performance microwave / millimeter-wave device, and research and development are being carried out in various fields. In particular, its effectiveness as a low-noise element has been confirmed at the experimental level.
Ee Microwave and Guided Wave Letters, Volume 1, Issue 7, 114-11
6, 1991 (IEEE MICROWAVE AND GUIDED WAVE L
ETTERS, VOL.1, NO.5, P.114-116, 1991)
H. Duh et al.) Reported that at room temperature,
Noise figure at 4 GHz 1.2 dB, associated gain 7.2
dB has been reached. These are lattice-matched systems on InP substrates, ie, In _0.52 Al _0.48 As / I.
A device is manufactured using a material system in which n _0.53 Ga _0.47 As and the In composition are specified. In this system, In _0.53 Ga _0.47 As
Although a two-dimensional electron gas is formed in the layer, in order to further improve the characteristics, for example, IEE Electron Device Letters, Vol. 10, No. 3, 114-
116 pages, 1989 (IEEE ELECTRON
DEVICE LETTERS, VOL. 10, N
O. 3, p. 114-116, 1989), the In composition of the InGaAs layer portion as a channel is set to a value larger than 0.53, and the device characteristics are adjusted. Attempts have been made to improve it.

Now, such InAlAs / InGaAs
In s-based heterojunction FETs, InGaAs is generally widely used as a two-dimensional electron gas channel. However, since the band gap is small at about 0.75 eV as compared with GaAs, and collision ionization is large, the breakdown voltage of the device is high. It is smaller than a GaAs heterojunction FET. In order to obtain stable device operation, increasing the withstand voltage of the device is a major issue, and approaches such as devising the epi layer of the device are being made.On the other hand, attempts to optimize the shape near the gate by expanding the gate recess, etc. Widely used.

When a high-concentration cap layer is used, the recess edge of the cap layer is made as large as possible from the gate electrode, so that
The electric field generated by the voltage applied to the gate is alleviated to reduce the collision ionization rate of channel electrons. This also reduces the parasitic capacitance between the gate and cap layers and also contributes to an increase in device power gain. However, this leads to an increase in source resistance on the source electrode side, and thus has a trade-off relationship with deterioration of characteristics.

In general, InAlAs semiconductors have a problem of surface instability such as influence of surface oxidation. An electron trap that captures electrons may occur on the surface of the recess near the gate, depending on the semiconductor material. In shown earlier
In an AlAs / InGaAs based heterojunction FET, InA
Although lAs is widely used as a Schottky layer of a gate electrode, InAlAs lattice-matched with an InP substrate
Since the l-composition contains about 50%, surface instability often becomes a problem, such as a high surface trap density due to oxidation or the like.

As an attempt to prevent the surface instability from being reflected in the device characteristics, a two-step recess structure is known. In this method, a cap layer is formed by etching in a relatively wide recess, and a second narrower recess is formed in the recess.
And a gate is formed in the second recess. The Schottky semiconductor surface beside the gate is located above the gate electrode formation position. In this way, even if there is surface instability due to an electron trap or the like existing on the semiconductor surface, device operation characteristics are not affected.

FIG. 14 shows an example of a conventional two-stage recess structure. This structure has an undoped InAlAs as a buffer layer on a semi-insulating InP substrate 201.
Layer 202, an undoped InGaAs layer 203 as a channel layer, an undoped InAlAs layer 204 and an n-type impurity-doped InAlAs layer 205 (undoped InAAs) as an electron supply layer for supplying carriers to the channel layer.
The lAs layer 204 may be considered as a spacer layer. ), An undoped InAlAs layer 206 as a Schottky layer, an n-type impurity-doped InGaAs layer 207 as a cap layer for making contact with an electrode, and a first recess 209 is further formed with a cap layer (n-type impurity-doped InGaAs). Layer 207), and a second recess 210 is provided in the first recess with a portion of the Schottky layer removed. A gate electrode 208a is formed on the surface of the Schottky layer exposed at the bottom of the second recess opening, and a source electrode and a drain electrode are formed on the cap layer (n-type impurity-doped InGaAs layer 207).

When a non-alloy ohmic contact which does not form an alloy with a semiconductor layer is formed by using a metal material as a material of a source electrode and a drain electrode in such a conventional structure, an I-type electrode generally used as a cap layer is used.
nGaAs and In typically used as a Schottky layer
There is a problem that the contact resistance is high because the conduction band discontinuity between AlAs is large.

On the other hand, the FE on the conventional GaAs substrate
In T, in order to lower the contact resistance, an alloy-type ohmic electrode that is alloyed using AuGe and Ni as materials of the source electrode and the drain electrode is widely used.

However, a heterojunction FET in which an AuGe-Ni alloy type ohmic electrode is formed on an InP substrate.
If you try to apply to
Symposium 1994 Proceedings, 261 pages (K. Onda et al., MTT Symp
osium Proceedings, p. 261-
264, 1994), for example, in an accelerated test at about 300 ° C., alloying further proceeds and the resistance increases. That is, there is a problem that reliability is lacking under actual use conditions.

On the other hand, IEE Electron Device Letters, vol. 13, p. 325, 19
In 1992, a heterojunction type F having a single recess structure
The ET shows that a non-alloy ohmic contact can be obtained by forming a cap layer in which an n-type InAlAs layer and an n-type InGaAs layer are stacked on an undoped InAlAs Schottky layer. However, non-alloy ohmic contact in a two-step recess structure using an InP substrate has not been known at all.

Further, if this epi structure is applied to a two-stage recess structure by a usual method, an undoped I
forming a first recess that penetrates to the nAlAs Schottky layer, followed by forming a second recess having a smaller width in the first recess, and forming a gate electrode in the second recess; become. However, in this case, at the time of forming the first recess, the two-layer stack cap of InGaAs and InAlAs is removed at the same time, so that there is a problem that the sheet resistance immediately below the first recess increases.
In addition, since the undoped InAlAs Schottky layer is exposed at the bottom of the first recess, the potential shape gradually changes from the surface to the inside, so that there is a problem that the influence of the surface easily appears on the device operation.

By the way, as a method of manufacturing a two-stage recess type field effect transistor, a first recess having a wide opening at the first stage is conventionally formed by etching, and then the first recess is formed in the first recess. It was common to form a small second recess by etching. However, in this method, two steps of exposure, development, and etching using a photoresist are required, and there is a problem that the steps are complicated.

[0016]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a two-step recess structure formed on an InP substrate and exhibiting stable device performance. An object is to provide a stable field-effect transistor having low resistance.

Another object of the present invention is to provide a manufacturing method for manufacturing such a high-performance two-stage recess type field effect transistor with good controllability.

[0018]

According to the present invention, a channel layer made of an undoped semiconductor is provided on an InP substrate, and an n-type impurity is doped over the entire area or locally in the thickness direction to supply carriers to the channel layer. Electron supply layer, an undoped InAlAs Schottky layer, an n-type InAlAs first cap layer provided in contact with the Schottky layer, and an n-type I-type layer provided in contact with the first cap layer.
an nGaAs second cap layer, a first recess opening provided through the second cap layer, and a surface of the Schottky layer passing through the first cap layer inside the first recess opening. Or a second recess opening provided by removing a part of the Schottky layer, and a gate electrode formed on the surface of the Schottky layer exposed at the bottom of the second recess opening. And a field-effect transistor including a source electrode and a drain electrode formed on both sides of the first recess opening on the second cap layer.

In this field effect transistor, a step of forming a channel layer made of an undoped semiconductor on an InP substrate, and a step of doping an n-type impurity in the entire thickness direction or locally in order to supply carriers to the channel layer. Forming a doped electron supply layer and undoped InAlAs
A step of forming a Schottky layer, a step of forming an n-type InAlAs first cap layer over the entire surface of the Schottky layer, and a step of forming an n-type InG over the entire surface of the first cap layer.
forming a second cap layer, and etching from the surface of the second cap layer, penetrating the second cap layer and the first cap layer, and reaching the surface of the Schottky layer; Removing the portion to form a second recess opening in a predetermined shape; and subsequently, side etching the second cap layer with an etching solution having a selectivity between InGaAs and InAlAs of 30 or more to obtain a predetermined shape. Forming an opening of the first recess.

Such a manufacturing method can be applied to a field-effect transistor having a conventional structure. That is, in this manufacturing method, a step of forming a channel layer made of an undoped semiconductor on an InP substrate, and an n-type impurity that is entirely or locally doped in the thickness direction to supply carriers to the channel layer. A step of forming an electron supply layer, a step of forming an undoped InAlAs Schottky layer, and a step of forming n-type In over the entire surface of the Schottky layer.
Forming a GaAs cap layer, and forming the n-type InG
forming a second recess opening in a predetermined shape by removing a part of the Schottky layer through the n-type InGaAs cap layer by etching from the surface of the aAs cap layer; and subsequently, selecting the InGaAs and InAlAs. The n-type InGaAs using an etching solution having 30 or more
forming an opening of the first recess in a predetermined shape by side-etching the s-cap layer.

In the present invention, since the resistance between the n-type InGaAs second cap layer and the undoped InAlAs Schottky layer is reduced by providing the n-type InAlAs first cap layer, a non-alloy ohmic electrode is used. However, a low contact resistance can be obtained.

The bottom of the first recess is formed of n-type InA.
Since the first As cap layer is formed, the potential shape when viewed from the surface in the depth direction of the inside is n-type InAlAs.
It changes sharply in the first cap layer, and undoped InAlA
It is almost horizontal in the s-Schottky layer. That is, since the influence of the surface is hard to reach the inside, particularly stable device operation can be obtained.

As described above, the field-effect transistor of the present invention has a two-stage gate recess shape, and the gate-semiconductor contact is provided in a portion etched deeper than the semiconductor surface beside the gate. Variations in device characteristics due to surface instability are suppressed.

Further, in the manufacturing method of the present invention, after exposing the gate contact surface, the first recess width is determined by selectively etching the n-type InGaAs second cap layer which is the outermost surface layer. Therefore, the first recess opening can be manufactured with good controllability, and at the same time, the manufacturing process can be simplified and the manufacturing cost can be reduced. This manufacturing method can also be applied to a conventional device structure in which an n-type InAlAs layer is not used as a part of a cap layer immediately below InGaAs as the outermost surface layer.

[0025]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

[Embodiment 1] FIG. 1 is a sectional view of a main part of an example of a field-effect transistor according to the present invention.

The epi structure of this field effect transistor is as follows:
On the semi-insulating InP substrate 101, 50
An undoped InAlAs layer 102 having a thickness of 0 nm and an undoped InGaAs layer 10 having a thickness of 20 nm as a channel layer.
3. 5 nm thick undoped InAlA as electron supply layer
s layer 104 and a 15 nm thick InAlAs layer 105 (undoped InA) with silicon added to 3 × 10 ¹⁸ cm ^−3.
The lAs layer 104 can also be called a spacer layer. ),
20 nm thick undoped InAl as Schottky layer
As layer 106, 3 × 10 ¹⁸ cm ⁻³ as first cap layer
20 nm thick InAlAs layer 1 doped with silicon
07, a 20 nm-thick InGaAs layer 108 in which silicon is added to 3 × 10 ¹⁸ cm ⁻³ as a second cap layer is laminated in this order.

The ohmic electrodes 109b and 109c are formed on the uppermost second cap layer InGaAs layer 108 by Ti /
It is formed by a Pt / Au laminated structure, and is not subjected to heat treatment. A first recess 110 is formed between the ohmic electrodes 109b and 109c. The depth of the first recess is determined by the undoped I
It reaches the surface of the nAlAs layer 107, and its recess width is 2 μm. In the first recess 110, a second recess 111 is further formed. The depth of the second recess is undoped InA, which is the Schottky layer.
It reaches halfway in the lAs layer 106, and its recess width is 1.1 μm.

The gate electrode 109 is formed in the second recess.
a is formed. Ti / Pt /
Au having a gate length of 1 μm in which Au is stacked in this order is used. Further, the device surface is covered with a SiN film 112 deposited by a plasma CVD method.

The initial characteristics of this field effect transistor are as follows:
The transconductance was as high as 600 mS / mm, the Schottky barrier height was 0.5 eV, and the gate reverse breakdown voltage was 11 V.

Next, a method of manufacturing the field effect transistor shown in this embodiment will be described with reference to FIGS.

(A) As shown in FIG. 2, a semi-insulating InP substrate 101 is formed by a molecular beam epitaxy method.
On top, a 500 nm thick undoped In as a buffer layer
AlAs layer 102, undoped InGaAs layer 103 of 20 nm thickness as channel layer, 5 nm as electron supply layer
Thick undoped InAlAs layer 104 and 3 × 10 ¹⁸ cm
InAlAs layer 105 having a thickness of 15 nm in which silicon is added to ^-3 (the undoped InAlAs layer 104 can also be referred to as a spacer layer), and 20 n as a Schottky layer
m-thick undoped InAlAs layer 106, 20 to which 3 × 10 ¹⁸ cm ⁻³ of silicon is added as a first cap layer
An InAlAs layer 107 with a thickness of nm and a InGaAs layer 108 with a thickness of 20 nm with silicon added to 3 × 10 ¹⁸ cm ⁻³ as a second cap layer were laminated in this order.

Although not shown, the photoresist was patterned into a predetermined mesa pattern on the epi-wafer by applying a photoresist, exposing and developing. Subsequently, mesa etching was performed by solution etching to form a mesa shape. The etching depth reaches the middle of the impurity-free InAlAs layer 102. For the etching, a mixture of phosphoric acid, hydrogen peroxide and water was used.

(B) Next, as shown in FIG. 3, a photoresist 121 was formed on the epi-wafer by applying a photoresist, exposing and developing, so as to form a pattern in which a portion for forming an ohmic electrode was opened.

(C) As shown in FIG. 4, as the ohmic metal 125, Ti, Pt, and Au are each 50 nm thick.
Evaporation was performed to a thickness of 50 nm and 200 nm.

(D) As shown in FIG. 5, by lifting off the photoresist, a laminated metal pattern is formed at the ohmic electrode forming position, and the ohmic electrodes 109b and 109c are formed in a predetermined shape.

(E) Subsequently, as shown in FIG. 6, after a photoresist 122 is coated on the wafer, an opening corresponding to the second recess shape is formed in the photoresist 122 by exposure and development (FIG. 6). The resist pattern is not shown.) The gate opening by this pattern is 1 μm
It is. The opening pattern matches the center of the opening substantially at the center between the ohmic electrodes.

(F) As shown in FIG. 7, a gate recess, that is, a second recess was formed on this pattern by solution etching. Here, an opening pattern corresponding to the second recess is provided in the photoresist, and an opening pattern is prepared on the ohmic electrode at the same time, so that a current value flowing between the ohmic electrodes can be monitored. The etching solution used for the main etching can etch both the first cap layer and the second cap layer. For example, a mixed solution of phosphoric acid, hydrogen peroxide and water is used. Etching is performed by solution etching until a desired amount of current flows between the ohmic electrodes, and the first recess etching is completed. In this device design, the undoped InAlA in which the second recess depth is the Schottky layer
It was set in the middle of the s layer 106. In this case, the etching may be stopped so that the bottom surface of the second recess becomes the surface of the Schottky layer.

(G) Next, as shown in FIG.
Using an etchant capable of selectively etching only nGaAs, the impurity-doped InGaAs layer 108 serving as the second cap layer in the portion exposed to the side surface of the second recess opening formed in (f) is selectively side-etched. I do. At this time, a mixed solution of citric acid, hydrogen peroxide solution (31%) and water (100 g: 100 m
ammonia water was added to the mixture to adjust the pH to 6.
The one adjusted to be 0 was used.

At this time, the etching solution that can be used is not limited to the above-mentioned one, and InGaAs can be used as an etching solution.
Any etchant that can selectively etch nAlAs may be used, and an etchant that usually has a selectivity between InGaAs and InAlAs of 30 or more, preferably 50 or more, and more preferably 100 or more is used.

As such an etching solution, a solution containing an organic acid soluble in water, particularly a di- or tricarboxylic acid having 2 to 10 carbon atoms is preferable. Among these, succinic acid, citric acid, adipic acid and malonic acid are particularly preferred.

The etching solution contains an oxidizing agent, and the above-mentioned hydrogen peroxide is preferable as the oxidizing agent because it is relatively stable as a solution and has no danger in preparing the etching solution.

In the above example, ammonia water was used as the pH adjuster, but the present invention is not limited to this.

In this step, the first recess width is determined. In this example, the side etching is performed until the first recess width becomes 2 μm.

(H) Then, as shown in FIG. 9, when a gate metal 123 is deposited on the surface of the photoresist 122, a part thereof is deposited on the bottom of the second recess from the opening of the photoresist.

(I) As shown in FIG. 10, the photoresist 122 was lifted off to form the gate electrode 109. Here, Ti, Pt, and Au as the gate electrode metals were stacked to a thickness of 50 nm, 50 nm, and 500 nm, respectively.

(J) As shown in FIG. 11, after forming the gate electrode, for example, an SiN film 112 was formed on the entire surface by a plasma CVD method at a film forming temperature of 330 ° C.

(K) As shown in FIG. 12, an opening pattern is formed on a part of each electrode again by applying, exposing and developing a photoresist 127, and patterning is performed so that the electrodes can be electrically connected. Is etched using buffered hydrofluoric acid using as a mask, thereby removing the SiN film in the opening pattern portion where the external contact is made.

(L) Thereafter, the photoresist 127 was removed to complete a field effect transistor as shown in FIG.

In the field-effect transistor manufactured by such a manufacturing method, since the first recess width is formed with good controllability, a particularly large kink (a phenomenon in which a variation point is observed in current-voltage characteristics; No instability, etc.) was observed, and stable device characteristics without optical response were exhibited.

[Second Embodiment] The method of manufacturing a two-step recess using the selective etching of InGaAs and InAlAs as described in the first embodiment is only used for a novel structure as shown in the first embodiment. Instead, it can be used as a method for manufacturing a conventionally used two-step recess type field effect transistor as shown in FIG. Hereinafter, the manufacturing method will be described.

(A) As shown in FIG. 15, a semi-insulating InP substrate 201 is formed by molecular beam epitaxy.
On top, a 500 nm thick undoped In as a buffer layer
AlAs layer 202, undoped InGaAs layer 203 of 20 nm thickness as channel layer, 5 nm as electron supply layer
Thick undoped InAlAs layer 204 and 3 × 10 ¹⁸ cm
15 nm thick InAlAs layer 205 obtained by adding silicon to ^-3 , an undoped InAlAs layer 206 having a thickness of 20 nm as a Schottky layer, and 3 × 10 ¹⁸ c as a cap layer
20 nm thick InGaAs with silicon added to m ^-3
The layers 207 were laminated in this order.

Next, although not shown, it was processed into a mesa shape in the same manner as in the first embodiment.

(B) Next, as shown in FIG. 16, a photoresist 221 was formed on the epiwafer by applying a photoresist, exposing and developing, so as to form a pattern in which an opening for forming an ohmic electrode was opened.

(C) As shown in FIG. 17, Au, Ge, and Ni are each used as the ohmic electrode metal for 100 n.
m, 50 nm, and 50 nm in thickness.

(D) As shown in FIG. 18, the photoresist was lifted off to form a laminated metal pattern at the ohmic electrode formation position. Subsequently, heat treatment was performed at 400 ° C. in a hydrogen atmosphere, and the electrodes were alloyed to form a source electrode 208b and a drain electrode 208c.

(E) Subsequently, as shown in FIG. 19, after applying a photoresist 222 on the wafer, an opening corresponding to the second recessed shape is formed in the photoresist 222 by exposure and development (FIG. 19). The resist pattern is not shown.) The gate opening by this pattern is 1 μm
It is. The opening pattern matches the center of the opening substantially at the center between the ohmic electrodes.

(F) As shown in FIG. 20, a gate recess, that is, a second recess was formed on this pattern by solution etching in the same manner as in the first embodiment. In the present device design, the etching was terminated such that the second recess depth was halfway in the undoped InAlAs layer 206 as the Schottky layer.

(G) As shown in FIG. 21, subsequently, using an etching solution capable of selectively etching only InGaAs, a portion of the cap exposed at the side surface of the second recess opening formed in (f) is subsequently formed. Impurity doped In layer
The GaAs layer 207 is selectively side-etched. As the etchant used for this etching, the etchant described in Embodiment 1 can be used. In this example, side etching was performed until the first recess width became 2 μm.

(H) to (l) As shown in FIGS. 22 to 26, after that, as in the first embodiment, (h) after depositing the gate electrode metal 223 (FIG. 22), (i) photo The resist 222 is lifted off to form a gate electrode 208a (FIG. 23), (j) a SiN protective film 211 is formed on the surface (FIG. 24), and (k) an external contact portion of the ohmic electrode using a photoresist 227. SiN protective film 2
11 was removed (FIG. 25), and (l) the photoresist 227 was finally removed to complete the field effect transistor of FIG.

In the field effect transistor manufactured as described above, the ohmic electrodes 208b and 208c are Au
Ge, Ni, and Au are alloyed by the heat treatment, and the alloy layer reaches the undoped InGaAs layer 203 as the channel layer. The depth of the first recess 209 after completion reaches the surface of the undoped InAlAs layer 206 as a Schottky layer, and the recess width is 2 μm.
Second recess 210 formed in first recess 209
Of undoped InAlAs, which is a Schottky layer
It reaches halfway in the layer 206, and the recess width is 1.1 μm.
m.

The initial characteristics of this field effect transistor are as follows:
The transconductance is 500 mS / mm, the Schottky barrier height is 0.5 eV, and the gate reverse breakdown voltage is 10 V
Met. As described above, the field effect transistor of this embodiment is inferior in the initial characteristics of the transconductance and the gate reverse breakdown voltage to those of the first embodiment, but by using such a manufacturing method, the first recess is formed. Since the width was formed with good controllability, no particularly large kink was observed, and the device exhibited stable device characteristics without light response.

In the conventional manufacturing method, when forming a two-stage recess, two individual recess forming steps and a gate forming step are required, which complicates the process. According to the method, only one exposure, development, and etching process using a photoresist is required, so that the process can be simplified and the cost can be reduced.

Although the above embodiments have been described using specific materials and specific values, the thickness and doping concentration of each layer need not be the values shown here. A structure in which the InAlAs layer is subjected to planar doping of Si or the like may be used. Although silicon is used here as the donor impurity, the material is not particularly limited to silicon as long as it is a material that enables n-type doping, and another material such as sulfur or selenium can be used.

In the present invention, the term “undoped” means that no impurity is intentionally added to a semiconductor or an impurity is added at a sufficiently low concentration. It is 1 × 10 ¹⁶ cm ⁻³ or less.

The material constituting the gate electrode to which the electric field is applied is not limited to the Ti / Pt / Au laminated structure, but may be the Mo / Ti / Pt / Au laminated structure, WSi, W, T
i / Al laminated structure, Pt / Ti / Pt / Au laminated structure,
It is possible to use single layers or laminations of various metals such as Al.

As for the ohmic electrode material, the first embodiment uses Ti / P as a non-alloy type ohmic electrode material.
On the other hand, in the second embodiment, AuGe / Ni is used as a heat-treated alloy type ohmic electrode material.
However, in applying the manufacturing method of the present invention, either an alloy type or a non-alloy type ohmic electrode may be used. The non-alloy type ohmic electrode is not limited to the Ti / Pt / Au laminated structure, but may be an electrode material used for the above-described normal gate electrode.

[0068]

According to the present invention, it is possible to provide a stable field-effect transistor having a two-stage recess structure formed on an InP substrate and exhibiting stable device performance, particularly having a low contact resistance and being stable. That is, in the field-effect transistor of the present invention, since most of the InAlAs surface beside the gate is present at a position higher than the gate-semiconductor contact position, the instability of the InAlAs surface does not affect the device operation. Further, since the surface layer is doped with n-type, a low contact resistance is provided even in a non-alloy ohmic electrode, so that the source resistance does not significantly deteriorate. Therefore, it can be used as a highly reliable and high-performance device in the microwave and millimeter wave regions.

Further, according to the manufacturing method of the present invention, such a high performance two-stage recess type field effect transistor can be manufactured with good controllability. Further, after the gate contact surface is exposed, the first recess width can be determined by selectively etching the n-type InGaAs second cap layer, which is the outermost surface layer, so that the first recess opening can be determined. Can be manufactured with good controllability, the manufacturing process can be simplified, and the manufacturing cost can be reduced.

The manufacturing method of the present invention uses the InGa of the outermost surface layer.
N-type InAlAs as a part of the cap layer directly under As
It is also applicable to conventional device structures that do not use layers.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part showing one example of a field-effect transistor of the present invention.

FIG. 2 is a view showing one step of a method for manufacturing the field-effect transistor of the present invention shown in FIGS. 2 to 13;

FIG. 3 is a view showing one step of a method for manufacturing the field effect transistor of the present invention shown in FIGS. 2 to 13;

FIG. 4 is a view showing one step of the method for manufacturing the field-effect transistor of the present invention shown in FIGS. 2 to 13;

FIG. 5 is a view showing one step of a method for manufacturing the field-effect transistor of the present invention shown in FIGS. 2 to 13;

FIG. 6 is a view showing one step of the method for manufacturing the field effect transistor of the present invention shown in FIGS. 2 to 13;

FIG. 7 is a view showing one step of a method for manufacturing the field-effect transistor of the present invention shown in FIGS. 2 to 13;

FIG. 8 is a view showing one step of the method for manufacturing the field-effect transistor of the present invention shown in FIGS. 2 to 13;

FIG. 9 is a view showing one step of a method of manufacturing the field effect transistor of the present invention shown in FIGS. 2 to 13;

FIG. 10 is a view showing one step of a method of manufacturing the field effect transistor of the present invention shown in FIGS. 2 to 13;

FIG. 11 is a view showing one step of a method for manufacturing the field-effect transistor of the present invention shown in FIGS. 2 to 13;

FIG. 12 is a view showing one step of a method of manufacturing the field effect transistor of the present invention shown in FIGS. 2 to 13;

FIG. 13 is a view showing one step of a method of manufacturing the field effect transistor of the present invention shown in FIGS. 2 to 13;

FIG. 14 is a cross-sectional view of a main part showing one example of a conventional field-effect transistor.

FIG. 15 is a view showing one step of the method for manufacturing the field effect transistor of the present invention shown in FIGS. 15 to 26;

FIG. 16 is a view showing one step of a method of manufacturing the field effect transistor of the present invention shown in FIGS. 15 to 26;

FIG. 17 is a view showing one step of the method of manufacturing the field-effect transistor of the present invention shown in FIGS. 15 to 26;

FIG. 18 is a view showing one step of the method for manufacturing the field effect transistor of the present invention shown in FIGS. 15 to 26;

FIG. 19 is a view showing one step of the method for manufacturing the field-effect transistor of the present invention shown in FIGS. 15 to 26;

FIG. 20 is a view showing one step of the method for manufacturing the field effect transistor of the present invention shown in FIGS. 15 to 26;

FIG. 21 is a view showing one step of a method of manufacturing the field effect transistor of the present invention shown in FIGS. 15 to 26;

FIG. 22 is a diagram showing one step of the method for manufacturing the field effect transistor of the present invention shown in FIGS. 15 to 26;

FIG. 23 is a view illustrating one step of the method of manufacturing the field-effect transistor of the present invention shown in FIGS. 15 to 26;

FIG. 24 is a diagram showing one step of the method for manufacturing the field-effect transistor of the present invention shown in FIGS. 15 to 26;

FIG. 25 is a view showing one step of the method for manufacturing the field effect transistor of the present invention shown in FIGS. 15 to 26;

FIG. 26 is a view showing one step of the method for manufacturing the field effect transistor of the present invention shown in FIGS. 15 to 26;

DESCRIPTION OF SYMBOLS 101 semi-insulating InP substrate 102 undoped InAlAs layer (buffer layer) 103 undoped InGaAs layer (channel layer) 104 undoped InAlAs layer (part of electron supply layer) 105 n-type InAlAs layer (one of electron supply layer) Part) 106 undoped InAlAs layer (Schottky layer) 107 n-type InAlAs layer (first cap layer) 108 n-type InGaAs layer (second cap layer) 109a gate electrode 109b source electrode 109c drain electrode 110 first recess 111 second Recess 112 SiN protective film 121 photoresist 122 photoresist 123 gate metal 125 ohmic metal 127 photoresist 201 semi-insulating InP substrate 202 undoped InAlAs layer (buffer layer) 203 an InGaAs layer (channel layer) 204 Undoped InAlAs layer (part of electron supply layer) 205 n-type InAlAs layer (part of electron supply layer) 206 Undoped InAlAs layer (Schottky layer) 207 n-type InGaAs layer (cap layer) 208a Gate electrode 208b Source electrode 208c Drain electrode 209 First recess 210 Second recess 211 SiN protective film 221 Photoresist 222 Photoresist 223 Gate metal 225 Ohmic metal 227 Photoresist

Claims (12)

[Claims] An undoped channel layer is formed on an InP substrate. The channel layer is made of an undoped semiconductor. The electron supply layer is doped with an n-type impurity in the entire thickness direction or locally to supply carriers to the channel layer. InAlAs Schottky layer and n-type InAlA provided in contact with the Schottky layer
a first cap layer, and an n-type InGaAs provided in contact with the first cap layer.
a second cap layer, a first recess opening provided through the second cap layer, and a surface of the Schottky layer passing through the first cap layer inside the first recess opening. Or a second recess opening provided by removing a part of the Schottky layer, and a gate electrode formed on the surface of the Schottky layer exposed at the bottom of the second recess opening. A field effect transistor comprising a source electrode and a drain electrode formed on both sides of the first recess opening on the second cap layer. 2. The method according to claim 1, wherein the channel layer is undoped InGaAs.
2. The field effect transistor according to claim 1, wherein the field effect transistor is an s layer, and the electron supply layer is an InAlAs layer including at least one n-type layer. 3. The field effect transistor according to claim 2, further comprising an undoped InAlAs buffer layer between the InP substrate and the channel layer. 4. A step of forming a channel layer made of an undoped semiconductor on an InP substrate, and supplying an electron in which an n-type impurity is entirely or locally doped in a thickness direction to supply carriers to the channel layer. Forming an undoped InAlAs Schottky layer; forming an n-type InAlAs first layer over the entire surface of the Schottky layer.
Forming a cap layer; and forming an n-type InGaAs second over the entire surface of the first cap layer.
Forming a cap layer; and etching from the surface of the second cap layer to penetrate the second cap layer and the first cap layer to reach just the surface of the Schottky layer, or to remove a part of the Schottky layer Forming a second recess opening in a predetermined shape, and then selecting a selectivity between InGaAs and InAlAs of 3
Forming the opening of the first recess in a predetermined shape by side-etching the second cap layer using zero or more etching liquids. 5. A step of forming a channel layer made of an undoped semiconductor on an InP substrate, and an electron supply in which an n-type impurity is entirely or locally doped in a thickness direction to supply carriers to the channel layer. Forming an undoped InAlAs Schottky layer; forming an n-type InGaAs cap layer over the entire surface of the Schottky layer; etching the n-type InGaAs cap layer from the surface of the n-type InGaAs cap layer. Forming a second recess opening in a predetermined shape by removing a portion of the Schottky layer through the InGaAs cap layer, and subsequently, selecting a ratio of InGaAs and InAlAs of 3
Forming a first recess opening in a predetermined shape by side-etching the n-type InGaAs cap layer with 0 or more etchants. 6. The channel layer is made of undoped InGaAs.
The method according to claim 4, wherein the s layer is an s layer, and the electron supply layer is an InAlAs layer including at least one n-type layer. 7. The method according to claim 4, further comprising the step of forming an undoped InAlAs buffer layer between the InP substrate and the channel layer. 8. The method according to claim 4, wherein the etching solution is an etching solution containing an organic acid. 9. The method according to claim 8, wherein the organic acid is a di- or tricarboxylic acid having 2 to 10 carbon atoms. 10. The method according to claim 10, wherein the organic acid is succinic acid, citric acid,
The method for manufacturing a field effect transistor according to claim 9, wherein the method is at least one selected from the group consisting of adipic acid and malonic acid. 11. The method according to claim 8, wherein the etching solution further includes an oxidizing agent. 12. The method according to claim 11, wherein the oxidizing agent is hydrogen peroxide.