JPH11163251A - Semiconductor device - Google Patents

Abstract

(57) Abstract: When a large number of circuits on a first semiconductor element switch at the same time, so-called simultaneous switching noise generated in a power supply unit or noise called ground bounce is suppressed, and the second semiconductor element has A semiconductor device capable of preventing a malfunction is provided. A first semiconductor element and an electrode pad of the first semiconductor element are connected to each other through bumps.
A second semiconductor element 2 electrically connected to the
Power supply to the second semiconductor element 2
It is performed from an independent separate system without passing through. An external circuit independent of the circuit of the second semiconductor element 2 is provided in the second semiconductor element 2, and the feed line is connected to the first semiconductor element 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device applied to a multi-chip module in a mounting field for mounting electronic components.

[0002]

2. Description of the Related Art In recent years, electronic devices have been increasingly miniaturized, enhanced in function, increased in operating speed, and modularized. Further, among these multi-chip modules, there has been proposed a configuration in which another semiconductor element is mounted on a semiconductor element and mounted in one package. Hereinafter, such a multi-chip module will be referred to as a system module for convenience in order to distinguish it from a multi-chip module using a normal substrate.

Hereinafter, an example of a conventional system module will be described with reference to the drawings. FIG. 6 shows a cross-sectional configuration of a semiconductor element junction of a conventional system module. In FIG. 6, reference numeral 51 denotes a first semiconductor element. 52 is an electrode pad of the first semiconductor element 51, 53 is a barrier metal layer formed on the electrode pad 52, 54 is a passivation film on the first semiconductor element 51, 55 is a metal projection ( Reference numeral 56 denotes a second semiconductor element. 57 is an electrode pad of the second semiconductor element 56, 58 is a barrier metal layer formed on the electrode pad 57,
Reference numeral 59 denotes a passivation film on the second semiconductor element 56. Reference numeral 60 denotes an insulating resin. The semiconductor elements 51 and 56 are mounted via the bumps 55 by a flip chip mounting method.

[0004] FIG. 7 shows an example of a process of a joining process portion of chips of a conventional system module. As shown in FIG. 2A, a first semiconductor element 51 and a second semiconductor element
56 At least one of the layers is made of Ti, P
The barrier metal layers 53 and 58 of d, Au, etc. are formed. Next, as shown in FIG. 3B, a portion excluding at least one of the electrode pads 52 and 57 of the first and second semiconductor elements 51 and 56 is covered with a photoresist 61 by using a photolithography technique.
As shown in (c), at least one of the first and second semiconductor elements 51 and 56 is also plated with Pb and Sn on the electrode pads 52 and 57 by an electrolytic plating method or the like. As shown in (d), the photoresist 61 is removed, and the barrier metal is removed by using aqua regia, hydrofluoric acid or the like to form the bump 55. First, as in (e),
When the bumps 55 on the second semiconductor elements 51 and 56 are formed on each other or on one of them, for example, only on the first semiconductor element 51, the bumps 55 and the electrode pads of the second semiconductor element 56 are formed. 57 is positioned and pressurization and heating are performed by the pressurization tool 62. Finally, as shown in FIG.
Is injected into the first and second semiconductor elements 51 and 56, the resin 60 is cured, and the first semiconductor element 51 is placed on the second semiconductor element 56.
Complete the installation.

[0005]

However, in the above configuration, the first and second semiconductor elements 51 and 56 face each other, and the first semiconductor element 51 is placed on the second semiconductor element 56. In the mounted configuration, power is supplied to the first semiconductor element 51 via the second semiconductor element 56.
When a large number of circuits on the first semiconductor element 51 switch at the same time, so-called simultaneous switching noise is generated in the power supply unit.
Or noise called ground bounce occurs.
At this time, noise also occurs in the power supply line to the second semiconductor element 56, and the operation of the second semiconductor element 56 has a problem of malfunction.

In view of the above problems, the present invention suppresses so-called simultaneous switching noise generated in a power supply unit or noise called ground bounce when, for example, a large number of circuits on a first semiconductor element switch at the same time. It is another object of the present invention to provide a semiconductor device capable of preventing a malfunction of the second semiconductor element.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor element; and a second semiconductor element having an electrode pad electrically connected to the electrode pad via a metal protrusion. A first semiconductor element and a second semiconductor element, wherein power is supplied to one of the first semiconductor element and the second semiconductor element from another independent system without passing through the other.

According to the semiconductor device of the first aspect, the power supply system of the first and second semiconductor elements becomes independent. For example, when a large number of circuits on the first semiconductor element switch at the same time, the second semiconductor element It is possible to suppress so-called simultaneous switching noise or noise called ground bounce generated in a power supply portion of the element, and to prevent malfunction of the second semiconductor element.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the first semiconductor element is mounted on the second semiconductor element, and the second semiconductor element is provided on the second semiconductor element independently of the circuit on the second semiconductor element. And a power supply line for the first semiconductor element connected to an external circuit. According to the semiconductor device of the second aspect, the same effect as that of the first aspect is obtained. According to a third aspect of the present invention, in the first aspect, the first semiconductor element is mounted on the second semiconductor element, and a capacitor is provided between a power supply line near a power supply portion to the first semiconductor element and ground. It is.

According to the semiconductor device of the third aspect, for example, when a large number of circuits on the first semiconductor element switch at the same time, so-called simultaneous switching noise generated in the power supply unit or noise called ground bounce is generated by the pass capacitor. It is possible to escape, and it is possible to suppress these effects. According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the capacitor is a high dielectric constant thin film, and is provided on the second semiconductor element.

[0011] According to the semiconductor device of the fourth aspect, the third aspect is provided.
Has the same effect as.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. (First Embodiment) FIG. 1 is a plan view schematically showing a power supply portion when a system module according to a first embodiment of the present invention is viewed from directly above. FIG.
In the figure, 1 is a first semiconductor element, 2 is a second semiconductor element, 3 is a power supply section shown in a schematic diagram of the second semiconductor element 2, and 4 is a first semiconductor element via the second semiconductor element 2. A power supply line (power supply line) shown in a schematic diagram independent of the second semiconductor device 2 for supplying power to the semiconductor element 1,
FIG.

FIG. 2A is a schematic sectional view of the module shown in FIG. 6 is a bump which is a metal protrusion, 7 is an electrode pad connected to the bump 6 of the first semiconductor element 1,
Reference numeral 8 denotes an electrode pad connected to the bump 6 of the second semiconductor element, and 9 denotes an insulating resin. This semiconductor device includes a first semiconductor element 1 and an electrode pad 7 of the first semiconductor element 1.
And a second semiconductor element 2 electrically connected to the electrode pad 8 via the bump 6 so that power is supplied to one of the first semiconductor element 1 and the second semiconductor element 2 without passing through the other. It is carried out from a separate independent system. In this case, the first semiconductor element 1 is mounted on the second semiconductor element 2,
An external circuit independent of the circuit on the second semiconductor element 2 is provided on the semiconductor element 2, and the first semiconductor element 1 is connected to the feed line 4 of the external circuit.

FIG. 3 shows an example of a manufacturing process of the semiconductor element mounting portion of the system module according to the first embodiment. As shown in FIG. 1A, a bump 6 made of Ni core Au or the like is formed on an electrode pad 7 of the first semiconductor element 1 by electroless plating or the like (for example, almost pure Ni (purity of about 95%)).
Is formed, and a thin film (having a thickness of about 0.1 μm) of Au (having a purity of 95% or more) is formed on the surface of the Ni bump. Bump 6 is composed of Au only, Sn, P
b (lead-tin-based solder) or a solder bump made of In, Sn (indium-tin-based solder), or the like. Further, formation by a transfer bump method is also possible. The diameter of the bump 6 is 5 μm to 100 μm for the Ni core Au bump and Au bump, and 100 μm for the solder bump.
m is used. In addition, the bumps 6 can be formed on both the first semiconductor element 1 and the second semiconductor element 2, or can be formed only on the second semiconductor element 2. Next, as shown in (b), the bumps 6 on the first semiconductor element 1 corresponding to the electrode pads 8 of the second semiconductor element 2 are aligned. As shown in (c), the first and second semiconductor elements 1 and 2 are pressed using a pressurizing and heating tool 11 at a pressure of about 0.1 to 100 grams per bump, and at a temperature of about 250 to 450 ° C. Then, pressure and heat are applied at a temperature of Au to join the Au-Au alloy. Further, when Au is formed only on the surface of the electrode pad of one semiconductor element, and the electrode pad on the other semiconductor element facing the other element is not processed and a normal Al pad is used, Au-Al alloy bonding is performed. I do. In the case of solder alloy bonding, the first semiconductor element 1 is pressed and heated at a temperature of about 60 ° C. to about 250 ° C. and a pressure of about several grams from the weight of the first semiconductor element 1 so that the first semiconductor element 1 is Mount on top. At this time, in addition to alloy bonding, MBB (microbump bonding) using a bonding method via an insulating resin widely known as a COG method.
A flip chip method such as a method may be used. Next (d)
As described above, the insulating resin 9 is injected between the first semiconductor element 1 and the second semiconductor element 2 and cured.

As described above, at least one or more power supply lines 4 from the external circuit independent of the circuit on the second semiconductor element 2 to the first semiconductor element 1 are provided on the second semiconductor element 2. With the use of the structure having the above structure, the power supply systems of the first and second semiconductor elements 1 and 2 become independent, and when a large number of circuits on the first semiconductor element 1 switch simultaneously, a so-called simultaneous Switching noise or noise called ground bounce can be made irrelevant.

At this time, via holes 10 are formed in the first semiconductor element 1 without passing through the surface of the second semiconductor element 2 as shown in FIG. It is also possible to form on the element 1 and directly supply power to the first semiconductor element 1. The external circuit and the power supply line 4 may be one or more. (Second Embodiment) FIG. 4 shows a system module according to a second embodiment of the present invention,
1 is a plan view showing a planar structure that is seen from directly above the sample No. 1. In FIG. 4, reference numeral 31 denotes a first semiconductor element, 32 denotes a second semiconductor element, 33 denotes a power supply unit shown in a schematic view of the second semiconductor element 32 and the first semiconductor element 31, and 34 denotes a second semiconductor element. The power supply line 33a of the second semiconductor element 32 via the semiconductor element 32, that is, the power supply portion and the ground line 3
5 shows a capacitor inserted between the first and second capacitors. Capacitor 3
4 is STR (strontium titanate: SrTiO3)
Or the like, or a ceramic chip capacitor connected by soldering or the like. 36 denotes an external pad of the second semiconductor element 32. Reference numeral 37 denotes an insulating resin.

This semiconductor device comprises a first semiconductor element 31
Are mounted on the second semiconductor element 32 and have a capacitor 34 between the power supply line 33a near the power supply portion to the first semiconductor element 31 and the ground. FIG. 5 shows an example of a manufacturing process of the semiconductor element mounting portion of the system module according to the second embodiment.

As shown in FIG. 2A, a capacitor 34 made of a high dielectric constant thin film such as STR is formed between the power supply unit 33 and the ground line 35 on the second semiconductor element 32 by a sputtering method or the like. Is completed, a protective film 42 is formed. Next, as shown in (b), bumps 39 made of Ni core Au or the like are formed on the electrode pads 38 of the first semiconductor element 31 by using an electroless plating method or the like. The bump 39 is composed of only Au, Sn, Pb (lead-tin based solder), or In, Sn
(Indium-tin solder) or the like may be used. Further, formation by a transfer bump method is also possible. The diameter of the bump 39 is Ni core Au bump, Au
In the case of a bump, a bump having a thickness of 5 μm to 100 μm is used, and in the case of a solder bump, a bump having a thickness of about 100 μm is used. Also, bump 3
9 can be formed on both the first semiconductor element 31 and the second semiconductor element 32, or can be formed only on the second semiconductor element 32. Next (c)
As described above, the bump 39 on the first semiconductor element 31 corresponding to the electrode pad 40 of the second semiconductor element 32 is aligned. As shown in (d), the first and second semiconductor elements 31 and 32 are pressed by using the pressing and heating tool 41 at a pressure of about 0.1 to 100 grams per bump at 250 ° C.
And then heated at a temperature of about 450 ° C. to perform Au—Au alloy bonding or Au—Al alloy bonding. In the case of solder alloy joining, the first element is pressurized and heated at a temperature of about 60 ° C. to 250 ° C. and a pressure of about several grams from the weight of the semiconductor element 31.
Is mounted on the second semiconductor element 32. At this time, in addition to alloy bonding, MBB using a bonding method via an insulating resin widely known as a COG method is used.
A flip chip method such as a (micro bump bonding) method may be used. Next, as shown in (e), an insulating resin 37 is provided between the first semiconductor element 31 and the second semiconductor element 32.
And cure.

Although the STR and the like are formed on the second semiconductor element 32, they can also be formed on the first semiconductor element 31. In addition to the thin film capacitor 34 such as STR,
It is also possible to provide connection pads and mount chip capacitors and the like by soldering or the like. As described above, the first semiconductor element 31 is opposed to the second semiconductor element 32 and is electrically connected through the corresponding metal protrusions, and the first semiconductor element 31 is connected to the first semiconductor element 32 via the second semiconductor element 32. In the structure for supplying power to the element 31, a capacitor 34 made of a high dielectric constant thin film or the like is arranged between the power supply line on the second semiconductor element 32 and the ground in the vicinity of the power supply part to the first semiconductor element 31. By configuring the semiconductor device, when a large number of circuits on the first semiconductor element 31 switch simultaneously, so-called simultaneous switching noise generated in the power supply unit or noise called ground bounce can be released from the pass capacitor. Can be suppressed.

[0020]

According to the semiconductor device of the first aspect, first,
The power supply system of the second semiconductor element is independent. For example, when a large number of circuits on the first semiconductor element switch at the same time, so-called simultaneous switching noise or ground bounce generated in the power supply section of the second semiconductor element. Called noise can be suppressed, and malfunction of the second semiconductor element can be prevented.

According to the semiconductor device of the second aspect, the first aspect
Has the same effect as. According to the semiconductor device of claim 3,
For example, when a large number of circuits on the first semiconductor element switch at the same time, so-called simultaneous switching noise generated in the power supply unit or noise called ground bounce can be released from the pass capacitor, and these effects can be suppressed. It becomes possible.

According to the semiconductor device of claim 4, according to claim 3,
Has the same effect as.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a system module according to a first embodiment of the present invention.

FIGS. 2 (a) and (b) are cross-sectional schematic views.

FIG. 3 is a manufacturing process diagram of the system module according to the first embodiment.

FIG. 4 is a schematic plan view of a system module according to a second embodiment.

FIG. 5 is a manufacturing process diagram of a system module according to a second embodiment.

FIG. 6 is a cross-sectional view showing a semiconductor junction of a system module in a conventional example.

FIG. 7 is a manufacturing process diagram of a semiconductor junction of a system module in a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 1st semiconductor element 2 2nd semiconductor element 3 Power supply part of 2nd semiconductor element 4 Power supply line 5 External pad of 2nd semiconductor element 6 Bump 7 Electrode pad 8 Electrode pad 9 Insulating resin 31 1st semiconductor element Reference Signs List 32 second semiconductor element 33 power supply section of first semiconductor element and second semiconductor element 33a power supply line 34 capacitor 35 ground line 36 external pad of second semiconductor element 37 insulating resin

Claims (4)

[Claims] 1. A semiconductor device comprising: a first semiconductor element; and a second semiconductor element in which an electrode pad of the first semiconductor element is electrically connected to the electrode pad via a metal protrusion. And a power supply to one of the second semiconductor elements is performed from an independent and separate system without through the other. 2. A first semiconductor device is mounted on a second semiconductor device, and an external circuit independent of a circuit on the second semiconductor device is provided on the second semiconductor device. 2. The semiconductor device according to claim 1, wherein the first semiconductor element is connected to the power supply line. 3. The semiconductor device according to claim 1, wherein the first semiconductor element is mounted on the second semiconductor element, and a capacitor is provided between a power supply line near a power supply portion to the first semiconductor element and ground. 4. The capacitor is a thin film having a high dielectric constant.
4. The semiconductor device according to claim 3, wherein said semiconductor device is provided on said semiconductor element.