JPH11163207A5 - - Google Patents

Claims (14)

A substrate member for mounting semiconductor chips, which is formed by etching a first metal layer of a first circuit-forming material having a first metal layer and a second metal layer to form a columnar pattern for interlayer connection, and then pressing an insulating material layer onto the surface on which the columnar pattern is formed. A substrate member for mounting semiconductor chips, which is formed by etching the first metal layer of a first circuit-forming material having a first metal layer and a second metal layer to form a columnar pattern for interlayer connection, and then bringing a second circuit-forming material having a third metal layer and a fourth metal layer into pressure contact with the surface on which the columnar pattern is formed, via an insulating material layer, thereby electrically connecting the columnar pattern and the fourth metal layer. 3. A substrate member for mounting a semiconductor chip as described in claim 1 or 2, wherein the first circuit forming material further comprises a first intermediate metal layer between the first metal layer and the second metal layer, the first intermediate metal layer being selectively etchable with the first metal layer. 4. A substrate member for mounting a semiconductor chip as described in claim 2 or 3, wherein the second circuit forming material further comprises a second intermediate metal layer between the third metal layer and the fourth metal layer, which can be selectively etched from the third metal layer. 5. The semiconductor chip mounting substrate member according to claim 1, wherein the insulating material layer is a thermosetting resin. a step of etching the first metal layer of a first circuit-forming material having a first metal layer and a second metal layer to form a columnar pattern for interlayer connection;
a step of bringing the surface on which the columnar pattern is formed into pressure contact with a second circuit-forming material having a third metal layer and a fourth metal layer via an insulating material layer, thereby electrically connecting the columnar pattern and the fourth metal layer ; and a step of etching the second and third metal layers to form a predetermined wiring pattern.
A method for manufacturing a semiconductor chip mounting substrate comprising: 7. The method for manufacturing a semiconductor chip mounting substrate according to claim 6, wherein the first circuit forming material further comprises a first intermediate metal layer between the first metal layer and the second metal layer, the first intermediate metal layer being selectively etchable relative to the first metal layer. 8. The method for manufacturing a semiconductor chip mounting substrate according to claim 6 or 7, wherein the second circuit forming material further comprises a second intermediate metal layer between the third metal layer and the fourth metal layer, the second intermediate metal layer being selectively etchable relative to the third metal layer. 9. The method for manufacturing a semiconductor chip mounting substrate according to claim 6, wherein after the step of electrically connecting the columnar pattern and the fourth metal layer, a treatment for reducing electrical resistance between the columnar pattern and the fourth metal layer is performed. 10. The method for manufacturing a semiconductor chip mounting substrate according to claim 9, wherein the treatment for reducing electrical resistance is voltage application. 10. The method for manufacturing a semiconductor chip mounting substrate according to claim 9, wherein the treatment for reducing electrical resistance is ultrasonic application. Before the step of electrically connecting the columnar pattern and the fourth metal layer, 12. The method for producing a semiconductor chip mounting substrate according to claim 6, wherein at least one of the metals is subjected to an oxidation/reduction treatment. 13. The method for manufacturing a semiconductor chip mounting substrate according to claim 6, wherein the insulating material layer is a thermosetting resin. 14. A semiconductor device in which a wiring pattern formed by etching the second metal layer of a semiconductor chip mounting substrate manufactured by the method according to any one of claims 6 to 13 serves as an external connection terminal, a wiring pattern formed by etching the third metal layer serves as a semiconductor connection terminal, and semiconductor chip terminals are connected to the semiconductor connection terminals.