JPH11163205A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To prevent warpage of a substrate when a power FET is mounted. Reduce the vertical and horizontal deviation of stress caused by temperature cycling. A source, drain, and gate electrode fingers are formed in an active region on a semiconductor substrate, and a source pad, a drain pad, and a gate pad connected to each electrode finger are formed on a non-active region. . In the figure, 4
Although two independent FET units 8 are formed, slits 3a, 3b, and 3c are formed between the respective FET units. PHS2 is formed on the back surface of the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a high-power semiconductor device obtained by applying a plated heat sink (hereinafter, referred to as PHS) to an FET (field effect transistor) pellet.

[0002]

2. Description of the Related Art A high-output FET is composed of a plurality of elements F having the same configuration.
This is realized by connecting ETs in parallel. That is, as shown in FIG. 5, the source electrode fingers S extending from the source pad 4 and the drain electrode fingers D extending from the drain pad 5 are alternately arranged, and the gate electrode finger G extending from the gate bus bar 6a is arranged therebetween. ing. The gate bus bar 6a is connected to the gate pad 6. At the intersection between the source electrode finger S and the gate bus bar 6a, the gate bus bar 6a is formed on the source electrode finger via an insulating film such as a silicon oxide film or an air gap.

In order to increase the output of a high-output FET, it is necessary to increase the gate width. However, the length (gate width) of the gate electrode finger is required to avoid deterioration of high-frequency characteristics.
It is necessary to reduce the thickness to about 00 μm or less. Therefore, it is necessary to increase the number of gate electrode fingers to increase the total gate width. As a result, the pellet size becomes, for example, 0.8 × 4.0 mm ² , and the aspect ratio in the vertical and horizontal directions becomes 5 or more. High output F
In the ET, the thickness of the substrate is reduced (for example, 30 μm) in order to enhance heat dissipation, and a thick (for example, 20 to 30 μm) gold plating layer called PHS is formed on the back surface of the substrate. As the aspect ratio increases, the FET pellets are placed in a copper case (package).
GaAs and PH when soldered using uSn solder
GaAs due to the difference in thermal expansion coefficient between S (Au) and solder
The s-substrate is warped and fixed. Therefore, FE
The image recognition by the camera at the time of the wire bonding performed after the mounting of the T pellet becomes inaccurate. In addition, since the thermal stress generated in the GaAs substrate during actual use has a large deviation in the vertical and horizontal directions, the crystal is distorted, which causes deterioration of FET characteristics and cracks.

[0004] One way to address this type of problem is to use PHS
It has been proposed that a slit be provided. FIG.
(A), (b), and (c) are a top view, a front view, and a bottom view of a semiconductor device proposed in JP-A-7-288299. In the figure, the same reference numerals are given to the same parts as those in FIG. 5, and the duplicate description will be omitted. However, in this conventional example, four FET units 8 are provided in the FET chip 100. Is formed, and the FET
PHS2 is formed on the back side of the chip. In the PHS 2, narrow slits 12a, 12b, and 12c are alternately formed in the arrangement direction of the FET units 8 between the adjacent FET units 8.

[0005]

In the conventional example shown in FIG. 6, when the FET pellet is soldered in the case, the solder is filled in the slit of the PHS2. Therefore, the thermal stress applied to the GaAs substrate during actual use is almost the same as that in the case where no slit is formed in the PHS. Therefore, the measures for slitting the PHS prevent deterioration of FET characteristics and cracks due to thermal stress. No effect can be expected. In the conventional example of FIG.
In the region where the slit is formed, the semiconductor substrate (Ga
Since the mechanical strength must be ensured only by the (As substrate), the thickness of the GaAs substrate cannot be reduced below a certain value, and the thermal resistance cannot be sufficiently reduced. Therefore, an object of the present invention is to solve these problems of the conventional example. First, thermal stress generated in a GaAs substrate is reduced even if the aspect ratio of the pellet is increased. Is to make the second
Another object is to reduce the thickness of the substrate without reducing the mechanical strength.

[0006]

According to the present invention, there is provided, in accordance with the present invention, a long side and a short side, and a first main surface and a second main surface.
A plurality of units each having a plurality of elementary FETs connected in parallel are formed along a long side on a first main surface of a semiconductor substrate having a main surface, and a PHS is formed on a second main surface of the semiconductor substrate.
In the semiconductor device in which is formed, a slit that penetrates the semiconductor substrate is formed between each unit and is parallel to the short side and does not reach the long side, and the PHS is formed on the inner wall of the slit. A semiconductor device having a connected metal film is provided. Preferably, the slit is covered with a metal film constituting a source pad formed on the surface of the semiconductor substrate.

[Operation] In the semiconductor device according to the present invention, a slit is formed in the semiconductor substrate, but the slit does not cross the substrate and the substrate extends from the slit to the long side of the substrate. Since the front and back surfaces are covered with a metal film and PHS extending from the source pad,
By providing the slit, the mechanical strength does not decrease, and the mechanical strength necessary for mounting and assembling the FET chip can be secured.

Since the semiconductor substrate is substantially divided by the slit, the effective aspect ratio of the substrate can be reduced. Therefore, F
The warpage when the ET chip is mounted can be reduced, and the vertical and horizontal deviation of the thermal stress applied to the substrate after mounting can be reduced, so that the characteristic deterioration and the occurrence of cracks can be suppressed. In order to be able to enjoy such effects, it is preferable that the planar shape of the substrate divided by the slit is as close to a square as possible. According to the experimental results, the aspect ratio of the substrate between the slits and between the slit and the short side of the substrate is 2/3.
It is desirably at least 3/2 and preferably at most 0.85 and at most 1.2.

When a large stress is applied to the GaAs substrate by a temperature cycle or the like after mounting and assembling, the stress can be concentrated on the substrate portion between the slit and the long side of the substrate. Can be generated only when Therefore, it is possible to prevent cracks from being generated in the regions of the element active portions and the pad portions formed between the slits, and not to affect the operation and characteristics of the entire FET. It is preferable that the distance between the slit and the long side of the substrate is short in order to concentrate the generation of cracks in this region. In the prototype of the inventor, good results could be obtained by setting the ratio of slit length / substrate short side length = 0.6 to 0.8.

[0010]

Next, embodiments of the present invention will be described in detail with reference to the drawings. [First Embodiment] FIG. 1 is a diagram for explaining a first embodiment of the present invention, and FIG.
FIGS. 1B and 1C are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 1A, respectively. FIG. 1D is a bottom view of the FET chip 100. As shown in FIG. 1, a source pad 4, a drain pad 5, and a gate pad 6 are formed on a semiconductor substrate 1, and an active region 7 sandwiched between these pads has a source electrode connected to each pad. Many fingers, drain electrode fingers, and gate electrode fingers are formed. The FET chip 100 includes four independent FET units 8. Each FE
Between the T units 8, slits 3a, 3b, 3c that do not reach the long side of the substrate are formed in parallel with the short side of the substrate. The slits 3 a, 3 b, and 3 c are covered with an extension of the source pad 4. The back surface of the substrate and the side surface of the slit are covered with PHS2. PHS2
And the source pad 4 is made of gold (Au) or platinum (Pt)
It is preferably formed of a noble metal such as

The aspect ratio of the semiconductor substrate in the region defined by the slit is desirably not less than 2/3 and not more than 3/2, and the length of the slit / the length of the short side of the substrate is 0. 0.6 to 0.8 is desirable.
By doing so, when the FET chip 100 is mounted in the case, the warpage can be reduced and the vertical and horizontal deviation of the stress can be reduced.
In addition, it is possible to specify a crack generation location only in the extension of the slit while securing the mechanical strength of the substrate.

[Second Embodiment] FIG. 2 is a diagram for explaining a second embodiment of the present invention.
2A and 2B are a plan view and a bottom view of the FET chip 100, and FIG. 2C is a cross-sectional view taken along the line CC 'of FIG. 2A. In FIG. 2, the same parts as those in FIG. 1 showing the first embodiment are denoted by the same reference numerals, and the duplicate description will be omitted. 100, a slit 9a formed in
The shapes of 9b and 9c are different from those of the first embodiment. That is, in the present embodiment, the slit 9
The planar shapes of a, 9b, and 9c are long hexagons. A side notch 10 is formed on the side surface of the substrate at the intersection of the extension of the center line of each slit and the long side of the semiconductor substrate. By forming such a slit shape and further forming the side notch 10 on the extension of the slit, it is possible to more reliably limit the location of the crack when stress occurs to the area between the slit and the side notch. it can.
The planar shape of the slit may be not only a long hexagon but also a shape obtained by adding a semicircle to two short sides of a rectangle.

[0013]

Next, an embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a cross-sectional view in the order of steps along the line AA 'in FIG. A semi-insulating GaAs substrate having a length of 1.0 mm and a width of 4.0 mm was prepared as the semiconductor substrate 1 [FIG.
(A)], an active region 7 (finger forming region: a region excluding a slit peripheral portion from a region surrounded by a dashed line) is provided by selectively ion-implanting the surface portion thereof, An FET is formed by forming electrode fingers, and a source pad 4, a drain pad 5, and a gate pad 6 are formed on the non-active area. Thus, four FET units 8 are formed on the substrate. Each electrode pad is formed to a thickness of 10 μm by Au plating. The source pad is formed so as to cover the area where the slit is to be formed (FIG. 3B).

After the FET is formed, the back surface of the substrate is polished to reduce the substrate thickness to 30 μm. Subsequently, etching is performed selectively from the back side of the substrate to obtain a width of 0.3 mm and a length of 0.7 m.
m slits 3a, 3b, 3c are formed [FIG.
(C)]. Thereafter, PHS2 having a film thickness of 20 μm is formed by Au plating (FIG. 3D). The FET chip 100 thus formed has slits 3a, 3b,
It is not separated by 3c, but is continuously connected as a whole, and has sufficient strength for handling of the present chip.

The FET unit 8 is connected to the FET chip 1
When the stress is applied due to a temperature cycle or the like after mounting the FET chip 100 on a case or the like, the stress is applied between the slits at the slit forming portion. Since it is released, the stress applied to the element active portion and the pad portion is reduced. Further, in the substrate region between the slit and the long side of the substrate, stress is concentrated in this region, and the mechanical strength in this region is low. Therefore, as shown in FIGS. The crack 11 can be generated by specifying this region. Therefore, it is possible to reduce the influence of the stress due to the temperature cycle and the like that is applied to the active region 7, and to suppress the deterioration of the device characteristics of the FET and improve the reliability.

[0016]

As described above, the present invention relates to an FET
Since a plurality of FET units are formed on the chip and separated between them by slits, the warpage of the substrate that occurs at the time of mounting the FET chip can be suppressed. Further, the stress generated in the active region can be suppressed, and the portion where the stress acts is limited to the substrate region between the slit and the long side of the substrate, so that the occurrence of cracks can be limited to this region. Therefore, according to the present invention, it is possible to suppress the deterioration of the element characteristics and improve the reliability of the FET chip.

Further, since the slit can be formed without lowering the mechanical strength, the thickness of the semiconductor substrate can be reduced, and the thermal resistance of the FET chip can be reduced. Further, according to the present invention, since the source pad can be directly connected to the PHS via the slit, a secondary effect of reducing the source resistance can be expected.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view of an FET chip for describing a first embodiment and an example of the present invention.

FIG. 2 is an F for explaining a second embodiment of the present invention;
FIG. 2 is a plan view and a cross-sectional view of the ET chip.

FIG. 3 is a sectional view in the order of steps for explaining a manufacturing method according to one embodiment of the present invention.

FIG. 4 is a plan view for explaining effects of the present invention.

FIG. 5 is a plan view illustrating a configuration of a general high-output FET.

FIG. 6 is a top view, a front view, and a bottom view of a conventional example.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 PHS (plated heat sink) 3a, 3b, 3c, slit 4 source pad 5 drain pad 6 gate pad 6a gate bus bar 7 active area 8 FET unit 9a, 9b, 9c, slit 10 side notch 11 crack 100 FET Chip D Drain electrode finger G Gate electrode finger S Source electrode finger

Claims (6)

[Claims] 1. An FET unit comprising a plurality of elementary FETs connected in parallel on a first main surface of a semiconductor substrate having a long side and a short side and a first main surface and a second main surface. PHS is formed on the second main surface of the semiconductor substrate.
In the semiconductor device in which is formed, a slit penetrating the semiconductor substrate, which is parallel to the short side of the substrate and does not reach the long side of the substrate, is formed between each FET unit. A metal film connected to the PHS is formed on an inner wall of the semiconductor device. 2. The method according to claim 1, wherein an upper surface of the slit is covered with a metal film connected to a source electrode.
13. The semiconductor device according to claim 1. 3. The planar shape of the slit is one of a rectangle, a shape obtained by adding a semicircle to a short side of the rectangle, and a shape obtained by adding an isosceles triangle to a short side of the rectangle. The semiconductor device according to claim 1, wherein: 4. A notch extending from a first main surface to a second main surface of the substrate at a position where an extension of a center line of the slit intersects a long side of the semiconductor substrate. Item 2. The semiconductor device according to item 1. 5. The semiconductor device according to claim 1, wherein an aspect ratio of the semiconductor substrate in a region defined by the slit is not less than 2/3 and not more than 3/2. 6. The relationship between the length of the slit and the length of the short side of the semiconductor substrate is such that: slit length / substrate short side length = 0.6 to 0.8. The semiconductor device according to claim 1, wherein: