JPH11168222A - Surge protection element - Google Patents

Abstract

(57) Abstract: line L ₁ and between the ground G and line L ₂ and the ground G
If a surge enters both sides of the
To protect electronic circuits such as ICs. SOLUTION: This is a three-terminal surge protection element 10 comprising a plurality of pnpn-type or npnp-type thyristors, provided with first and second electrodes 11 and 12 on the front surface and a third electrode 13 on the back surface. A portion between the first electrode 11 and the third electrode 13 is formed in a thyristor structure, and the first electrode 11
Another portion between the second electrode 12 and the third electrode 13 is formed in a pn junction structure, and a portion between the second electrode 12 and the third electrode 13 is formed in a thyristor junction structure. Electrode 1
3 is formed in a pn junction structure, and between the first electrode 11 and the second electrode 12 is formed in a bidirectional thyristor structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surge protection device comprising a plurality of pnpn-type or npnp-type thyristors. For further details, see SLIC (Subscriber L
ine Interface Circuit: IC (Integ)
The present invention relates to a surge protection element for preventing an overvoltage surge from entering an electronic circuit such as a rated circuit, or a bidirectional surge protection element for protecting an overvoltage surge from entering an electronic circuit connected to a communication circuit.

[0002]

2. Description of the Related Art This type of SLIC is a central office, an automatic private branch exchange, and a four-wire single-terminal conversion and subscription that provides differential signal separation for the two-wire system by differentially suppressing vertical signals at the two-wire input. Used in person transporters. Also SLIC
Is supplied with a DC line current, normally biased to a negative voltage, which energizes the telephone set. The SLIC has a tip (TIP) terminal and a ring (RING) terminal connected to a telephone set. On the line hooked to the tip and ring terminal, lightning surge generated by occasional lightning,
Overvoltage surge caused by transient phenomena from nearby devices, lighting, and other electrical devices arrives.

[0003] Conventionally, as shown in FIG.
As a method of protecting the electronic circuit 3 and the like, a two-terminal surge protection device 1 and 2 between the line L ₂ and the ground G to be connected to the line L ₁ to be connected to chip terminals between the ground G and ring terminals There are ways to connect each. The two-terminal surge protection elements 1 and 2 have the same structure. This structure will be described with reference to FIG. 26. The two-terminal type surge protection element 1 (or 2) includes a plurality of npnp thyristors, and a first electrode 4 is provided on a front surface and a second electrode 5 is provided on a back surface. A part between the first electrode 4 and the second electrode 5 (left side in the figure) is formed in an npnp type thyristor structure, and another part between the first electrode 4 and the second electrode 5 (right side in the figure) Is p
An n-junction structure is formed. This two-terminal surge protection element 1 (or 2) has the VI characteristic shown in FIG. Also,
As a method of protecting the electronic circuit of this type from overvoltage surges using a bidirectional surge protection device, between and between the line L ₂ and the ground G of the line L ₁ and the ground G as shown in FIG. 29 There is a method of connecting the bidirectional two-terminal surge protection elements 1 and 2 respectively. The two-terminal surge protection elements 1 and 2 have the same structure. This structure will be described with reference to FIG. 28. The two-terminal type surge protection element 1 (or 2) includes a plurality of npnp thyristors, and a first electrode 4 is provided on the front surface and a second electrode 5 is provided on the back surface. This first
A part (left side in the figure) between the electrode 4 and the second electrode 5 is npnp
Another portion (the right side in the figure) between the first electrode 4 and the second electrode 5 is formed in a pnpn-type thyristor structure. This two-terminal surge protection element 1
(Or 2) has the VI characteristic shown in FIG.

However, this way the circuit using two two-terminal surge protection device 1 and 2, the line L ₁ and the ground G
When the simultaneous surge both between and between the line L ₂ and the ground G has entered the sometimes from variations in the characteristics of the two elements, without the actuating element 1 and 2 at the same time, operation of one of the elements However, in some cases, a delay may occur as compared with the operation of the other element. In these cases, since the surge voltage between the lines L ₁ and the line L ₂ (lateral surge) occurs, and entering the electronic circuit 3 connected between the surge current and the line L ₁ and the line L ₂ As a result, the circuit 3 may be damaged. Therefore, as shown in dotted line in FIG. 29, by adding line L ₁ and the line identity of the bidirectional two-terminal surge protection element 6 and the element shown in FIG. 28 also between the L _2, a total of three elements Has also been used.

On the other hand, to solve these problems, 3
A surge protection element having a structure having three terminals in one chip without using one element has been proposed (for example, Japanese Patent Application Laid-Open No. Hei 3-1).
36374, JP-A-3-136375). This protection element is provided with two terminals having a symmetrical electrode structure on the surface of the substrate with respect to a common substrate, and one terminal is provided on the back surface of the substrate, or by having a symmetrical two-terminal structure. , Forming a composite thyristor structure. As shown in FIG. 30, the second terminal of the surge protection element 7 line L ₁ and the line L ₂ and the surface of the structure is connected, the rear surface of the one terminal is connected to the ground G. If on the device is small variation in the very surge absorption properties, which between the terminal and the ground G is connected to the line L ₁ in FIG. 30 has operated in this device, the line L
It has also been said that the connection between the terminal connected to ₂ and the ground G also operates in accordance therewith.

Further, as shown in FIG.
As another method for protecting the electronic circuit 3, there is a method in which the first surge protection element 1 is provided in the first stage, which is the preceding stage of the electronic circuit 3, and the second surge protection element 2 is provided in the second stage. First and second terminal provided on the surface to the line L ₂ connecting to lines L ₁ and the ring terminal connected to the second surge protection devices 1 both chip terminal connected, connecting one terminal of the rear face to the ground G doing. These surge protection elements 1 and 2 have different structures from each other. PTC thermistors 3a and 3b having a positive temperature coefficient to the line L ₁ and L ₂ between the surge protection element 1 and 2
Are interposed respectively.

The structure of the surge protection element 1 will be described with reference to FIG. 31. The three-terminal surge protection element 1 has electrodes 4 and 5 on the front surface and an electrode 6 on the back surface. A part between the electrodes 4 and 6 and a part between the electrodes 5 and 6 are formed in a pnpn-type thyristor structure, respectively, and the other part between the electrodes 4 and 6 and between the electrodes 5 and 6 are formed.
The other portions between are each formed in an npnp junction structure. An oxide insulating film 1b is provided on the front and back surfaces of the n-type substrate 1a other than the electrodes. The three-terminal surge protection device 1 has a VI characteristic shown in FIG. FIG. 23A shows the horizontal characteristics, and FIG. 23B shows the vertical characteristics. The structure of the surge protection element 2 will be described with reference to FIG.
Electrodes 7 and 8 are provided on the surface of the three-terminal surge protection element 2.
However, electrodes 9 are provided on the back surface, respectively. A part between the electrodes 7 and 9 and a part between the electrodes 8 and 9 are formed in a pn junction structure, respectively, and the other part between the electrodes 7 and 9 and the part between the electrodes 8 and 9 are formed. The other parts are np
It is formed in an np type thyristor structure. Further, a part of the bonding portion between the electrode 7 and the electrode 8 and the substrate is provided with a region 2c having a lower withstand voltage as compared with the other parts. An oxide insulating film 2b is provided on the front and back surfaces of the n-type substrate 2a other than the electrodes. This three-terminal type surge protection device 2 has a V-
It has an I characteristic. FIG. 24A shows the horizontal characteristics, and FIG. 24B shows the vertical characteristics. 23 and 24, the second-stage surge protection element 2
Is the voltage V _bd2 protected by the first-stage surge protection element 1
_Is set to be lower than the voltage V _bd1 protected by.

[0008]

[SUMMARY OF THE INVENTION However, in the circuit using two two-terminal surge protection device 1 and 2 shown in FIG. 27, and between the line L ₂ and the ground G of the line L ₁ and the ground G Between the two surges at the same time,
Due to the variation of one element, the elements 1 and 2 may not operate at the same time, and the operation of one element may be delayed compared to the operation of the other element. If the two lines L ₁ and L ₂ themselves are uneven in quality and uneven,
In some cases, simultaneously generated surges arrive at the two two-terminal surge protection elements 1 and 2 with a time lag. In these cases, since the surge voltage between the lines L ₁ and the line L ₂ (lateral surge) occurs, and entering the electronic circuit 3 connected between the surge current and the line L ₁ and the line L ₂ As a result, the circuit 3 may be damaged.

Further, in the shown in JP-A-3-136374 and JP-A No. 3-136375 three-terminal bidirectional surge protection element 7, the quality of the two lines L ₁ and the line L ₂ are the same In some cases, since the generated surge reaches the element at the same time, the thyristors operate at almost the same time because the variation in element characteristics, which is a feature of this technology, is small. If the line itself of the line L ₁ and line L ₂ is non-uniform there are variations in its quality, it was the surge that occurred at the same time arrives displaced in three-terminal surge protection device 7 in time . Furthermore, since the operation is one of the thyristor, dependently on to the other works, actually caused by the amount time delay spread time of carriers, by a potential difference occurring during this time, the line L ₁ and the line or element between the L ₂ may be broken, or that there are problems such as damage to electronic circuits 3 revealed.

Further, in the surge protection device shown in FIGS. 26, 28 and 31, the junction between the substrate and the semiconductor layer determines the breakover voltage of the device, and the substrate concentration is determined in order to optimize this voltage. Had been. However,
In particular, when an element having a breakover voltage of 100 V or less is to be manufactured, the substrate concentration becomes 10 ¹⁶ / cm ³ or more. When the substrate concentration is set to the above value, there is a problem that the mobility and diffusion length of carriers in the substrate are reduced, the operation speed of the thyristor is significantly impaired, and as a result, the surge withstand capability is significantly reduced. Further, in the SLIC surge protection element shown in FIG. 26 or FIG. 31, of the two transistors constituting the thyristor, the metastable state which is considered to be caused by the low performance of the transistor based on the substrate region is considered. Occurs. Even after the surge has passed by this,
The surge protection element is turned on by the power supply voltage, and there is a problem that a so-called follow-on current occurs. Also, the circuit using two three-terminal surge protection elements 1 and 2 having different operating voltages shown in FIG. 33 has a problem that the number of components is large and it takes time to incorporate the protection circuit. In addition, it is necessary to manufacture two types of such surge protection elements, and there is a problem in manufacturing the surge protection elements and managing them as parts.

A first object of the present invention is to provide a line L ₁ and a ground G
Both the invention is to provide a surge protection device for protecting an electronic circuit ensures such SLIC for IC when a surge has entered between and between the line L ₂ and the ground G with. A second object of the present invention is to provide a surge protection element which does not reduce the surge withstand capability without impairing the operation speed of the thyristor and does not cause a continuation current after passing the surge. Third of the present invention
SUMMARY OF THE INVENTION It is an object of the present invention to provide a surge protection element which can be easily integrated into a circuit for protecting an electronic circuit against overvoltage surge by unifying two elements having different operating voltages.

[0012]

The invention according to claim 1 is
As shown in FIGS. 1 (a), 1 (b), 2 (a) and 2 (b), it is composed of a plurality of pnpn-type or npnp-type thyristors, and the first and second electrodes 11, 12 are provided on the surface. Is provided, and a part between the first electrode 11 and the third electrode 13 is formed in an npnp thyristor structure in the surge protection element 10 in which the third electrode 13 is provided on the back surface (FIG. 1).
(A)), another portion between the first electrode 11 and the third electrode 13 is formed in a pn junction structure (FIG. 1B), and similarly between the second electrode 12 and the third electrode 13. Are formed in an npnp type thyristor structure (FIG. 1B), and the first electrode 11
Another part between the first electrode 11 and the second electrode 12 is formed in a pn junction structure (FIG. 1A).
A three-terminal surge protection element characterized by having a bidirectional thyristor structure between the two.

As shown in FIG. 3, when a pair of lines L ₁ and L ₂ are connected to an electronic circuit 30 such as an SLIC IC,
The first electrode 11 to the line L _1, also line L ₂ of the second electrode 12
Then, the third electrode 13 is connected to the ground G. Applied negative overvoltage surge line L ₁ is, if the voltage, as shown by the solid line of the V-I characteristic of the FIG. 4 reaches the breakover voltage V _BO, the first electrode 11 between the third electrode 13 The thyristor structure (npnp) conducts, and a current equal to or greater than the holding current I _H flows through the surge protection element 10 to maintain the conduction state.
When the line L ₁ and a positive voltage is applied, the solid line in FIG. 4 V-
As indicated by the I characteristic, the pn junction structure between the first electrode 11 and the third electrode 13 immediately conducts. Due to the conduction, the surge current flows to the ground G without flowing to the electronic circuit 30, and protects the electronic circuit 30. If negative overvoltage surges or positive overvoltage surge line L ₂ is applied, the second electrode 12 and the third
Electrodes 13 operate in a similar manner to protect electronic circuit 30. Further surges between the line L ₁ and the line L ₂ (i.e., horizontal surge)
Because it if occurred, to between the first electrode 11 of the second electrode 12 is formed on the two-way thyristor structure, the line L ₁ and L ₂
A thyristor operation is performed between them, and the surge is absorbed.

[0014]

Embodiments of the present invention will now be described with reference to the drawings. 1 (a), 1 (b), 2
As shown in FIG. 2A and FIG. 2B, the three-terminal surge protection element 10 according to the first embodiment includes a plurality of pnpn-type or npnp-type thyristors.
And the second electrode 12 are provided, and the third electrode 13 is provided on the back surface. The surge protection device 10 includes a first semiconductor layer n ₁₀ of n-type, which is also the substrate. The second and third semiconductor layer p ₂₀ and p ₃₀ is the surface exposed to the surface and spaced apart from each other of a pair of p-type semiconductor layer n ₁₀ is formed. The outer surface of these semiconductor layers p ₂₀ and p ₃₀ exposed to the outer surface and the fourth semiconductor layer n _40, n ₄₀ of n-type, as contained in the semiconductor layer p ₂₀ and p ₃₀ are formed respectively. the back surface of the n-type first semiconductor layer n ₁₀ of exposed on the back surface and the fourth semiconductor layer n _40, the fifth semiconductor layer opposite the n ₄₀ p
_50, p ₅₀ is the sixth semiconductor layer n _60, n ₆₀ are respectively formed to face the second and third semiconductor layer p _20, p ₃₀ as well. The first electrode 11 is formed by a short circuit in each of the outer surface and a fourth semiconductor layer n ₄₀ which is included in this second semiconductor layer p _20. The second electrode 12 is formed by a short circuit in each of the outer surface and a fourth semiconductor layer n ₄₀ which is included in this and the third semiconductor layer p _30. Further, the third electrode 13 is the fifth
The semiconductor layers p ₅₀ , p ₅₀ , the sixth semiconductor layer n ₆₀ , n ₆₀ and the first semiconductor layer n ₁₀ are formed by short-circuiting each other on their outer surfaces. Although not shown in the front and back surfaces of the non-electrode n-type first semiconductor layer n ₁₀ of which is also the substrate will be described later 2
As shown in FIG. 1, an oxide insulating film is provided. Hereinafter, FIG.
The same applies to FIGS. 7 to 11, 15 and 17 to 20.

As shown in FIG. 3, the surge protection terminal 10 having such a configuration is connected to the SLICs connected to the lines L ₁ and L _2.
It is connected to the front stage of the electronic circuit 30 such as an IC for use. In the case where negative overvoltage surge line L ₁ or L ₂ is applied, the voltage semiconductor layer n _10, as shown by the solid line of the V-I characteristic of the FIG. 4
A breakdown exceeds the breakdown voltage of the junction between the semiconductor layer p ₂₀ or p _30, further reaches the breakover voltage V _BO, while between the electrodes 11 and 13 or electrodes 12 and 13 become conductive. On the other hand, when a positive voltage is applied to the line L ₁ or L ₂ ,
Semiconductor layer n ₁₀ from the semiconductor layer p ₃₀ or p ₂₀ as shown by the solid line of the V-I characteristic of the FIG. 4 is forward biased, the electrode 1
Conduction is immediately made between the electrodes 2 and 13 or between the electrodes 11 and 13. Due to the conduction, the surge current flows to the ground G without flowing to the electronic circuit 30, and protects the electronic circuit 30. If the surge has entered the more both of the line L ₁ and the line L _2, the first electrode 1
A semiconductor layer n ₄₀ between the first and second electrodes 12, a semiconductor layer p ₂₀ ,
Since the arrangement of the semiconductor layer n ₁₀ and the semiconductor layer p ₃₀ are formed in both directions thyristor structure, the thyristor operation is performed between lines L ₁ and L _2, the surge is absorbed.

FIGS. 5 (a), 5 (b), 6 (a) and 6 (b) show a second embodiment of the present invention. Also in this embodiment, the three-terminal type surge protection device 10 includes a plurality of pnp
The first electrode 11 and the second electrode 12 are provided on the front surface, and the third electrode 1 is provided on the back surface.
3 are provided. The surge protection device 10 includes a first semiconductor layer n ₁₀ of n-type, which is also the substrate. This semiconductor layer n ₁₀
A pair of second and third p-type second and third semiconductor layers p ₂₁ ⁺ and p ₃₁ ⁺ are formed on the surface of the substrate and exposed to and separated from each other. This is the semiconductor layer p ₂₁ ⁺ outer surface exposed to the outer surface and the semiconductor layer p ₂₂ ⁺⁺ fourth semiconductor layer n ₄₁ ⁺ and p-type n-type, as contained in the semiconductor layer p ₂₁ ⁺ is formed You. The semiconductor layer p ₃₂ ⁺⁺ fourth semiconductor layer n ₄₂ ⁺ and p-type n-type, as contained in the exposed and the semiconductor layer p ₃₁ ⁺ on this outer surface is formed in the semiconductor layer p ₃₁ ⁺ outer surface You.

[0017] The n-type first on the back surface of the semiconductor layer n ₁₀ exposed to the back surface and spaced apart from each other by a fifth semiconductor layer p ₅₁ ⁺ and p ₅₁ ⁺ and a pair of n-type a pair of p-type sixth The semiconductor layers n ₆₁ ⁺ and n ₆₁ ⁺ are formed. The outer surfaces of the fifth semiconductor layers p ₅₁ ⁺ and p ₅₁ ⁺ are exposed to this surface and the semiconductor layers p ₅₁ ⁺ and p ₅₁ ⁺
_The p-type semiconductor layers p ₅₂ ⁺⁺ and p ₅₂ are included in ₅₁ ^+
++ are formed respectively. The first electrode 11 includes a second semiconductor layer p ₂₁ ⁺ , a semiconductor layer n ₄₁ ⁺ and a semiconductor layer p contained therein.
₂₂ ⁺⁺ and short-circuited on each outer surface.
In addition, the second electrode 12 is formed by short-circuiting the third semiconductor layer p ₃₁ ⁺ and the semiconductor layer n ₄₂ ⁺ and the semiconductor layer p ₃₂ ⁺⁺ contained therein on the respective outer surfaces. Further, the third electrode 13 includes a pair of p-type fifth semiconductor layers p ₅₁ ⁺ and p ₅₁ ⁺ , semiconductor layers p ₅₂ ⁺⁺ and p ₅₂ ⁺⁺ included therein, and a pair of n-type sixth semiconductor layers. The layers n ₆₁ ⁺ and n ₆₁ ⁺ are formed by short-circuiting each other on their outer surfaces.

As compared with the first embodiment, on the surface of the device, a semiconductor layer p ₂₂ ⁺⁺ included in the second semiconductor layer p ₂₁ ⁺ is formed, and a third semiconductor layer p ₃₁ ^{+ is included.} This semiconductor layer p ₃₂ ⁺⁺ to be encapsulated to form respectively, in the rear surface of the device, the pair sixth semiconductor layer n ₆₁ ⁺ and n ₆₁ ⁺
And the semiconductor layers p ₅₂ ⁺⁺ and p ₅₂ ⁺⁺ included in the fifth semiconductor layers p ₅₁ ⁺ and p ₅₁ ⁺ , respectively, so that the surge protection characteristics of the element are improved. Become. The other operations are the same as those of the above-described embodiment, and the description thereof will not be repeated.

In the first and second embodiments, FIG.
(A), FIG. 1 (b), the FIG. 5 (a) and the second semiconductor layer p ₂₀ or p ₂₁ ⁺ and the third semiconductor layer p ₃₀ as shown in FIG. 5 (b)
Alternatively, when the distance between p ₃₁ ⁺ and w ₃₁ is w ₁ , w ₁ is the fifth semiconductor layer p ₅₀ or p ₅₁ ^{+ and} the second semiconductor layer p facing the fifth semiconductor layer p ₅₀ or p ₅₁ ^+. distance w _2, and the fifth semiconductor layer p ₅₀ or p ₅₁ ⁺ third semiconductor layer p ₃₀ or p to fifth faces the semiconductor layer p ₅₀ or p ₅₁ ⁺ of Toko between ₂₀ or p ₂₁ ⁺
₃₁ ⁺ whether each smaller than the distance w ₃ between, or preferably equal. Further, in the first and second embodiments, it is preferable that the structure between the first electrode 11 and the second electrode 12 be configured to perform a punch-through operation with respect to an overvoltage. Here, the punch-through operation refers to the surge protection element 10.
Depletion of the second semiconductor layer p ₂₀ that occurs when the overvoltage is applied (hereinafter, the spread of the depletion layer that w _p) and the third
It refers to the depletion layer and leads the operation of the semiconductor layer p _30. FIG.
(A) and FIGS. 5 (a) to the state where the depletion layer w _p of the second semiconductor layer p ₂₀ and p ₂₁ ⁺ are connected to the third semiconductor layer p ₃₀ and p ₃₁ ⁺ depletion layer respectively. w ₁ ≦ w ₂ and w ₁ ≦
w ₃ or the punch-through operation between the electrodes 11 and 12 against overvoltage, the quality of the _two lines L ₁ and L ₂ is not uniform, and the surge protection element 10 to be the time to reach deviated in line L ₁ and the line L _2, as compared with a case where the thyristor operation between the lines L ₁ and the line L _2, a very fast and reliable thyristor operation and surge within the protective element A punch-through operation is performed, and the electronic circuit can be protected. Here, with respect to w _p , the above-mentioned w ₁ , w ₂ and w ₃ are expressed by the following equation (1).
It is more preferable that the following relationship is satisfied: w _p <w ₁ ≦ w ₂ = w ₃ (1)

FIGS. 7A and 7B show a third embodiment of the present invention.
FIG. 8A and FIG. 8B show a fourth embodiment of the present invention. In these embodiments, the first semiconductor layer n ₁₀ of n-type ^- The first semiconductor layer n ₁₀ on the surface of the ^- same conductivity type in a by the first semiconductor layer n ₁₀ ^- higher impurity concentration than n-type seventh semiconductor layer n ₇₀ is formed. The seventh semiconductor layer n ₇₀ is thicker than the second and third semiconductor layers p ₂₀ , p ₃₀ or p ₂₁ ⁺ , p ₃₁ ⁺ and the second and third semiconductor layers n ₇₀ .
It is formed to include the semiconductor layers p ₂₀ and p ₃₀ or p ₂₁ ⁺ and p ₃₁ ⁺ . With this configuration, the break-over voltage surge protection device is a voltage that turns on is determined by the concentration of the seventh semiconductor layer n _70, the first semiconductor layer n
₁₀ ⁻ can be optimized independently of the breakover voltage so as not to reduce the diffusion length of carriers, and at the same time, considering the series resistance of the substrate (semiconductor layer n ₁₀ ⁻ ).

FIGS. 9 (a) and 9 (b) show a fifth embodiment of the present invention, and FIGS.
(B) shows a sixth embodiment of the present invention. In these embodiments, the seventh embodiment similar to the third and fourth embodiments will be described.
Semiconductor layer n ₇₀ is first semiconductor layer n ₁₀ ^- are formed on the surface of the. Here seventh semiconductor layer n ₇₀ the second and third semiconductor layer p _20, p ₃₀ or p ₂₁ ^+, p ₃₁ ⁺ thinner second and third semiconductor layer p _20, p ₃₀ or p ₂₁ ^+, p ₃₁ ⁺ , And the second and third semiconductor layers p ₂₀ and p ₃₀ or p ₂₁ ⁺ and p ₃₁ ⁺ are formed so as to be in contact with the first semiconductor layer n ₁₀ ⁻ . With such a configuration, a depletion layer at the junction between the substrates is mainly formed in the substrate region having a low concentration, so that the junction capacitance can be significantly reduced. This structure is suitable for digital lines such as ISDN.

Next, FIG. 11 (a), FIG. 11 (b), FIG.
FIGS. 2A and 12B show a seventh embodiment of the present invention. The bidirectional three-terminal surge protection device 10 of this embodiment includes a plurality of pnpn-type or npnp-type thyristors, the first electrode 11 and the second electrode 12 are provided on the front surface, and the third electrode 13 is provided on the back surface. Can be The surge protection device 10 includes a first semiconductor layer n ₁₀ of n-type, which is also the substrate. The semiconductor layer n the second and third semiconductor layer p ₂₀ and p ₃₀ each of the surfaces spaced this exposed to the surface and to each other of the pair of p-type ₁₀ is formed. These semiconductor layers p
The outer surfaces of ₂₀ and p ₃₀ are exposed on this outer surface and the semiconductor layer p
Fourth n-type semiconductor layers n ₄₀ and n ₄₀ are formed to be included in ₂₀ and p ₃₀ , respectively. The fifth semiconductor layer p ₅₀ single are formed opposite to exposed to the back surface and to the second and third semiconductor layer p ₂₀ and p ₃₀ on the back surface of the n-type first semiconductor layer n ₁₀ of . A pair of sixth semiconductor layers n ₆₀ , n ₆₀ are formed on the outer surface of the fifth semiconductor layer p _{50 so} as to be exposed on the outer surface and not to face the fourth semiconductor layers n ₄₀ , n ₄₀ .

[0023] The first electrode 11 is formed by short-circuiting the fourth semiconductor layer n ₄₀ which is included in this second semiconductor layer p ₂₀ in each of the outer surface. The second electrode 12 is formed by a short circuit in each of the outer surface and a fourth semiconductor layer n ₄₀ which is included in this and the third semiconductor layer p _30. Further, the third electrode 1
3 the sixth semiconductor layer n ₆₀ of the pair and the fifth semiconductor layer p _50, n ₆₀
Are short-circuited to each other on their outer surfaces.

The surge protection terminal 10 having such a configuration is connected to a stage preceding the electronic circuit 30 connected to the lines L ₁ and L ₂ as shown in FIG. In the case where the positive overvoltage surge line L ₁ or L ₂ is applied, exceeds the breakdown voltage of the junction between the semiconductor layer n ₁₀ and the semiconductor layer p ₅₀ the voltage is as shown in the solid line of the V-I characteristic of the FIG. 14 When the voltage reaches the breakover voltage V _BO , conduction between the electrodes 11 and 13 or between the electrodes 12 and 13 is established. On the other hand, is applied a negative voltage to the line L ₁ or L _2, solid lines V-I of the voltage is 14
Semiconductor layer n _10, as shown in characteristics and the semiconductor layer p ₂₀ or p ₃₀
If the breakdown voltage of the junction with
The connection between the electrodes 1 and 13 or between the electrodes 12 and 13 is conducted. Due to the conduction, the surge current flows to the ground G without flowing to the electronic circuit 30, and protects the electronic circuit 30. Further, when a surge intrudes between the line L ₁ and the ground G and between the line L ₂ and the ground G with a time lag, the semiconductor layer n ₄₀ between the first electrode 11 and the second electrode 12 , The arrangement of the semiconductor layer p ₂₀ , the semiconductor layer n ₁₀ and the semiconductor layer p ₃₀ is a bidirectional thyristor structure,
Thyristor operation is performed between lines L ₁ and L _2, the surge is absorbed.

FIGS. 15 (a), 15 (b), 16
(A) and FIG. 16 (b) show an eighth embodiment of the present invention. The bidirectional three-terminal surge protection element 10 of this embodiment is composed of a plurality of pnpn-type or npnp-type thyristors, the first electrode 11 and the second electrode 12 are provided on the front surface, and the third electrode 13 is provided on the back surface. . The surge protection device 10 includes a first semiconductor layer n ₁₀ of n-type, which is also the substrate. This is the surface of the semiconductor layer n ₁₀ exposed to the surface and respectively spaced apart from one another a pair of p-type of the second and third semiconductor layer p ₂₁ ⁺ and p ₃₁ ⁺ is formed. This semiconductor layer p ₂₁ ⁺
The n-type fourth semiconductor layer n ₄₁ ⁺ and the p-type semiconductor layer p ₂₂ ⁺⁺ are formed on the outer surface of the substrate so as to be exposed on the outer surface and included in the semiconductor layer p ₂₁ ⁺ . The addition to the semiconductor layer p ₃₁ ⁺ outer surface exposed to the outer surface and n-type as contained in the semiconductor layer p ₃₁ ⁺ the fourth semiconductor layer n ₄₂ ⁺ and p-type semiconductor layer p ₃₂
⁺⁺ is formed.

[0026] The back surface of the n-type first semiconductor layer n ₁₀ of exposed on the back surface and the p-type second and third semiconductor layer p ₂₁ ⁺
And a single p-type fifth semiconductor layer p ₅₁ ⁺ is formed to face p ₃₁ ⁺ . On the outer surface of the fifth semiconductor layer p ₅₁ ⁺ , a pair of p-type semiconductor layers p ₅₂ ⁺⁺ and p ₅₂ ⁺⁺ exposed on the outer surface and opposed to the fourth semiconductor layers n ₄₁ ⁺ and n ₄₂ ^+. Are also exposed on the outer surface and a pair of n-type sixth semiconductor layers n ₆₁ ⁺ and n ₆₁ ⁺ are formed facing the semiconductor layers p ₂₂ ⁺⁺ and p ₃₂ ⁺⁺ , respectively. The first electrode 11 is formed by short-circuiting the second semiconductor layer p ₂₁ ⁺ and the semiconductor layer n ₄₁ ⁺ and the semiconductor layer p ₂₂ ⁺⁺ contained therein on the respective outer surfaces. In addition, the second electrode 12 is formed by short-circuiting the third semiconductor layer p ₃₁ ⁺ and the semiconductor layer n ₄₂ ⁺ and the semiconductor layer p ₃₂ ⁺⁺ contained therein on the respective outer surfaces. Further, the third electrode 13 is a p-type fifth semiconductor layer p.
₅₁ ⁺ and the semiconductor layers p ₅₂ ⁺⁺ and n ₆₁ ⁺ included therein are short-circuited on their respective outer surfaces.
As compared with the above-described embodiment, the second
Thereby forming a semiconductor layer p ₂₂ ⁺⁺ to be encapsulated to the semiconductor layer p ₂₁ ^+, the semiconductor layer p ₃₂ ⁺⁺ to be encapsulated to the third semiconductor layer p ₃₁ ⁺ forms respectively, the rear surface of the element fifth semiconductor layer p ₅₁ ⁺ the sixth semiconductor layer n ₆₁ ⁺ and n ₆₁ ⁺ and the pair of the semiconductor layer p _{5 2} ⁺⁺ pair to be encapsulated and p ₅₂ ⁺⁺
Are formed, the surge protection characteristic of the element is improved. The other operations are the same as those of the above-described embodiment, and the description thereof will not be repeated.

In the seventh and eighth embodiments, FIG.
1 (a), FIG. 11 (b), FIG. 15 (a) and FIG.
The second semiconductor layer as shown in (b) p ₂₀ or p ₂₁ ⁺ the third
When the distance between the semiconductor layer p ₃₀ or p ₃₁ ⁺ and w _1,
The second semiconductor layer p ₂₀ or p ₂₁ of the w ₁ is opposed to the fifth semiconductor layer p ₅₀ or p ₅₁ ⁺ Toko fifth semiconductor layer p ₅₀ or p ₅₁ ^{+ +}
Distance w _2, and the fifth semiconductor layer p ₅₀ or p ₅₁ ⁺ distance between the fifth third semiconductor layer p ₃₀ or p ₃₁ facing the semiconductor layer p ₅₀ or p ₅₁ ^{+ +} of Toko w between It is preferable that each is smaller than or equal to ₃ . In addition, the seventh and eighth
In this embodiment, it is preferable that a punch-through operation is performed between the first electrode 11 and the second electrode 12 with respect to an overvoltage similarly to the first and second embodiments. FIGS. 11A and 15A show the second semiconductor layers p ₂₀ and p
Shows ₂₁ ⁺ of the state where the depletion layer w _p are connected to the third semiconductor layer p ₃₀ and p ₃₁ ⁺ depletion layer respectively. By setting w ₁ ≦ w ₂ and w ₁ ≦ w ₃ , or by performing a punch-through operation between the electrodes 11 and 12 with respect to an overvoltage, the quality of the _two lines L ₁ and L ₂ can be reduced. The time at which the surge protection element 10 arrives at the line L ₁
And it is shifted in the line L _2, as compared with a case where the thyristor operation between the lines L ₁ and the line L _2, a very fast and reliable thyristor operation and punch-through operation is performed in a surge protection element, electrons The circuit can be protected. Here, it is more preferable that w ₁ , w _2, and w ₃ described above have the relationship of the above-described expression (1) with respect to w _p .

FIGS. 17 (a) and 17 (b) show a ninth embodiment of the present invention, and FIGS.
(B) shows a tenth embodiment of the present invention. In these embodiments, n-type first semiconductor layer n ₁₀ of ^- higher impurity concentration than ^- front and rear surfaces on the first semiconductor layer n ₁₀ of ^- and have the same conductivity type first semiconductor layer n ₁₀ n-type seventh
A semiconductor layer _n70 and an eighth semiconductor layer _n80 are respectively formed. The seventh semiconductor layer n ₇₀ is thicker than the second and third semiconductor layers p ₂₀ , p ₃₀ or p ₂₁ ⁺ , p ₃₁ ⁺ and the second and third semiconductor layers n ₇₀ .
It is formed to include the semiconductor layers p ₂₀ and p ₃₀ or p ₂₁ ⁺ and p ₃₁ ⁺ . The eighth semiconductor layer n ₈₀ is the fifth semiconductor layer p ₅₀
Or and thicker than p ₅₁ ⁺ is formed so as to include a fifth semiconductor layer p ₅₀ or p ₅₁ ^+. With this configuration, the breakover voltage, which is the voltage at which the surge protection element is turned on, is determined by the concentration of the seventh semiconductor layer n ₇₀ , and the first semiconductor layer n ₁₀ ⁻ does not reduce the carrier diffusion length. At the same time, optimization can be performed independently of the breakover voltage in consideration of the series resistance of the substrate (semiconductor layer n ₁₀ ⁻ ).

FIGS. 19 (a) and 19 (b) show an eleventh embodiment of the present invention, and FIGS. 20 (a) and 20 (b) show a twelfth embodiment of the present invention. Is shown. In these embodiments, the ninth and tenth seventh semiconductor layer n ₇₀ and the eighth semiconductor layer n ₈₀ similar to the embodiment of the first semiconductor layer n ₁₀ ^- are formed respectively on the front and back surfaces of the. Here, the seventh semiconductor layer n ₇₀ is composed of the second and third semiconductor layers p ₂₀ , p _20
30 or p ₂₁ ⁺ , p ₃₁ ⁺ , surrounding the second and third semiconductor layers p ₂₀ , p ₃₀ or p ₂₁ ⁺ , p ₃₁ ⁺ , and covering the second and third semiconductor layers p ₂₀ , p ₃₀ or p ₃₁ ⁺ ₂₁ ⁺ and p ₃₁ ⁺ are formed to be in contact with the first semiconductor layer n ₁₀ . The eighth semiconductor layer n ₈₀
To contact ^- fifth semiconductor layer p ₅₀ or p ₅₁ ⁺ was thinner and surrounding the fifth semiconductor layer p ₅₀ or p ₅₁ ^+, and the fifth semiconductor layer p ₅₀ or p ₅₁ ⁺ the first semiconductor layer n ₁₀ is Formed.
With such a configuration, a depletion layer at the junction between the substrates is mainly formed in the substrate region having a low concentration, so that the junction capacitance can be significantly reduced. This structure is suitable for digital lines such as ISDN.

Further, FIGS. 21 (a), 21 (b), 2
2A and FIG. 22B show a thirteenth embodiment of the present invention. The thyristor-type surge protection element 10 of this embodiment includes a plurality of pnpn-type or npnp-type thyristors, and includes first, second, third, and fourth electrodes 11, 12,.
13 and 14, a fifth electrode 15 is provided on the back surface facing the first and second electrodes, and a sixth electrode 16 is provided facing the third and fourth electrodes. This surge protection element 10 starts from a silicon n-type substrate which is also a substrate 10a. On the left half surface of the n-type substrate, a pair of semiconductor layers p ⁺ is formed which are exposed on the surface and are separated from each other.
Semiconductor layers n ⁺ are respectively formed on the outer surfaces of these semiconductor layers p ^{+ so} as to be exposed on the outer surfaces and included in the semiconductor layers p ⁺ . These semiconductor layers n ⁺ are formed at positions not opposed to each other when viewed from above (FIG. 22).
(A)). The right half of the surface of the semiconductor layer n, which is also a substrate 10a semiconductor layer n ⁺ are respectively formed so as to be included in these semiconductor layers p ⁺ pair of semiconductor layer p ⁺ like the left half of the surface. Then, the pair of semiconductor layers p ⁺ and the substrate 10
At the junction of the semiconductor layer n which is also a, a trigger region 17 made of a semiconductor layer n ′ having a lower withstand voltage than other portions is formed.

In order to form the surface structure of the surge protection element, first, boron (B), which is a p-type impurity, is diffused into an n-type silicon substrate 10a to form a pn junction. The operating voltage is caused by the avalanche breakdown of the junction, and the operating voltage is determined by the impurity concentration (resistivity) in the silicon substrate as the starting material. On the other hand, a trigger region 17 (n ') having a higher impurity concentration than the silicon substrate is formed at the junction between the silicon substrate and the first diffusion layer p ⁺ . The trigger region 17 is formed by exposing a part of the surface of the silicon substrate and diffusing impurities of the same type as the substrate there. The trigger region 17 allows the operating voltage to be positively controlled to a voltage lower than the operating voltage determined by the substrate concentration. And the back surface of the left half of the semiconductor layer n, which is also the substrate 10a and exposed to the rear surface opposite to both of the semiconductor layer p ^{+ +} single semiconductor layer p is formed. The single semiconductor in layer p ⁺ external surface exposed to the outer surface and the semiconductor layer n ⁺ a pair of semiconductor layer so as not to face the n ⁺ are formed. A pair of semiconductor layers n ⁺ and a pair of semiconductor layers p ⁺ are provided on the back surface of the right half of the semiconductor layer n which is also the substrate 10a so as to be exposed on the back surface. These semiconductor layers n ⁺ and the semiconductor layer p ⁺ is when viewed from below, the semiconductor layer n ⁺
And p ⁺ are formed at positions adjacent to each other (FIG. 22).
(B)).

The first to fourth electrodes 11 to 14 are connected to a semiconductor layer p ⁺
And the semiconductor layer n ⁺ contained therein are short-circuited on the respective outer surfaces. The fifth electrode 15 is formed by short-circuiting the semiconductor layer p ⁺ and a pair of semiconductor layers n ⁺ included therein on the respective outer surfaces. Further, the sixth electrode 1
6 is formed by short-circuiting a pair of semiconductor layers n ⁺ and a pair of semiconductor layers p ⁺ on their respective outer surfaces. An oxide insulating film 10b is provided on the front and back surfaces of the n-type substrate 10a other than the electrodes. With the above configuration, the thyristor junction structure is formed between the first electrode 11 and the fifth electrode 15 and between the second electrode 12 and the fifth electrode 15, respectively, and the gap between the third electrode 13 and the sixth electrode 16 is formed. And a part between the fourth electrode 14 and the sixth electrode 16 are each formed in a pn junction structure,
Another portion between the third electrode 13 and the sixth electrode 16 and the fourth portion
Other portions between the electrode 14 and the sixth electrode 16 are each formed in a thyristor junction structure.

As shown in FIG. 25, the surge protection terminal 10 configured as described above is connected to a stage preceding the electronic circuit 30 connected to the lines L ₁ and L ₂ . That is, as shown in FIG. 25, the second electrode 12 and the third electrode 13 are connected to the line L ₁ .
The first electrode 11 and the fourth electrode 14 are connected to the line L ₂ , and the fifth electrode 15 and the sixth electrode 16 are connected to the ground G. Further, a line L between the second electrode 12 and the third electrode 13
₁ has a PTC thermistor 18 having a positive temperature coefficient,
The same PTC thermistor 19 is in line L ₂ between the first electrode 11 and the fourth electrode 14 are respectively interposed. The electrode 11 and the electrode 1 of the thyristor type surge protection element 10
The horizontal VI characteristics between the two are shown in FIG.
The vertical VI characteristics between the electrode 11 or 12 and the electrode 15 are shown in FIG. FIG. 24A shows the VI characteristics in the horizontal direction between the electrodes 13 and 14, and FIG. 24B shows the VI characteristics in the vertical direction between the electrodes 13 or 14 and the electrode 16. Is shown. The breakdown voltage V _bd2 shown in FIG. 14 by the trigger region 17 (FIG. 25) is shown in FIG.
3 is set lower than the breakdown voltage V _bd1 .

A positive overvoltage surge is applied to the line L ₂ ,
When this overvoltage is higher than the breakdown voltage _Vbd2 , first, conduction between the electrode 14 and the electrode 16 is conducted, and the electronic circuit 30 is protected. Now continuing to apply abnormal voltage exceeding the breakdown voltage V _bd2 a long time, by the thermistor 19 is generating heat resistance is increased, a potential difference is generated between the line L ₂ and the ground G. Thus, when the abnormal voltage exceeds the breakdown voltage _Vbd1 between the electrodes 11 and 15, the electrodes 11 and 15 conduct, and the thermistor 19 is prevented from being damaged. Also when a negative voltage is applied to the line L _1, FIG. 24
As shown in the VI characteristic of (b), the pn junction structure between the electrode 13 and the electrode 16 immediately conducts. The conduction protects the electronic circuit 30. Now a negative voltage is continuously applied for a long time, by the thermistor 18 is generating heat resistance is increased, a potential difference is generated between the line L ₁ and the ground G. Thus, when the abnormal voltage exceeds the breakdown voltage _Vbd1 between the electrodes 12 and 15, the electrodes 12 and 15 conduct, and the thermistor 18 is prevented from being damaged. Further, when a surge enters both the line L ₁ and the ground G and the line L ₂ and the ground G simultaneously or with a time lag, first, the line L ₁ between the electrode 13 and the electrode 14. a thyristor operation between L ₂ is performed, the surge is absorbed, the thyristor between the lines L ₁ and L ₂ between the electrodes 12 and 11 in order to protect the thermistor 18 or 19 if the surge continues The operation is performed and the surge is absorbed.

[0035]

As described above, according to the present invention, when the line L ₁ and L ₂ are connected to the electronic circuit of the IC or the like for SLIC, the line L ₁
During and between the line L ₂ and the ground G and the ground G, the conventional 2
Although two two-terminal surge protection elements are separately connected, according to the invention of claim 1, a single three-terminal surge protection element is connected. Disappears. As a result, if the surge both between and between the line L ₂ and the ground G of the line L ₁ and the ground G has entered, the surge almost simultaneously operate both thyristor in surge protection device of the present invention Absorb. Further, in the case where the two lines L ₁ and L ₂ themselves have irregularities in their quality and are non-uniform, the simultaneously generated surges are caused by the first electrode and the second electrode.
Even arrived shifted temporally electrode, because between the first electrode and the second electrode is formed on the two-way thyristor structure, thyristor operation between the lines L ₁ and the line L ₂ is performed, Surge is absorbed and protects electronic circuits. The bidirectional thyristor structure between the first electrode and the second electrode means that, in the surge protection element of the present invention, an appropriate operating voltage, holding current, surge current and the like can be applied between the two electrodes of the first electrode and the second electrode. It also has advantages such as withstand capability, no operation delay, and no element breakdown.

When the lines L ₁ and L ₂ are connected to the electronic circuit, two or three conventional two-terminal surges are provided between the line L ₁ and the ground G and between the line L ₂ and the ground G. According to the ninth aspect of the present invention, the protection elements are individually connected, but a single three-terminal surge protection element is connected. As a result, when both simultaneously surge intrudes, almost simultaneously operate both thyristor in surge protection device of the present invention surge and between the line L ₂ and the ground G of the line L ₁ and the ground G Absorb. Further, when the lines L ₁ and L ₂ are connected to the electronic circuit, two three-terminal type surge protection devices having different operating voltages are conventionally provided between the line L ₁ and the ground G and between the line L ₂ and the ground G. According to the seventeenth aspect of the present invention, the elements connected to the front stage of the electronic circuit are connected by connecting the elements having different operating voltages to each other. It will be easier. In addition, the production control and inventory control of the element are facilitated.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view of the surge protection element according to the first embodiment, taken along the line AA in FIG. 2A. (B) FIG. 2 of the surge protection element of the first embodiment
FIG. 3A is a cross-sectional view taken along line BB.

FIG. 2A is a plan view of a surge protection element according to the first embodiment. (B) The bottom view of the surge protective element of a 1st embodiment.

FIG. 3 is a surge protection circuit diagram using the surge protection element according to the first embodiment.

FIG. 4 is a VI characteristic diagram of the surge protection element according to the first embodiment.

FIG. 5A is a sectional view of the surge protection element according to the second embodiment, taken along the line CC in FIG. 6A. (B) FIG. 6 of the surge protection device of the second embodiment
FIG. 3A is a cross-sectional view taken along line DD.

FIG. 6A is a plan view of a surge protection element according to a second embodiment. (B) The bottom view of the surge protective element of a 2nd embodiment.

FIG. 7A is a sectional view of the surge protection element according to the third embodiment, corresponding to the line AA in FIG. 2A; (B) FIG. 2 of the surge protection element of the third embodiment
Sectional drawing corresponding to the BB line of (a).

FIG. 8A is a sectional view of a surge protection element according to a fourth embodiment, taken along line CC of FIG. 6A. (B) FIG. 6 of the surge protection element according to the fourth embodiment
Sectional drawing corresponding to DD line of (a).

FIG. 9A is a sectional view of a surge protection element according to a fifth embodiment, taken along line AA of FIG. 2A. (B) FIG. 2 of the surge protection element according to the fifth embodiment
Sectional drawing corresponding to the BB line of (a).

FIG. 10A is a sectional view of a surge protection element according to a sixth embodiment, taken along line CC of FIG. 6A. (B) FIG. 6 of the surge protection element according to the sixth embodiment
Sectional drawing corresponding to DD line of (a).

11A is a sectional view of the surge protection element according to the seventh embodiment taken along line HH of FIG. 12A. (B) FIG. 12 of the surge protection element of the seventh embodiment
(A) Sectional view on the JJ line.

FIG. 12A is a plan view of a surge protection element according to a seventh embodiment. (B) The bottom view of the surge protective element of a 7th embodiment.

FIG. 13 is a surge protection circuit diagram using the surge protection element according to the seventh embodiment.

FIG. 14 is a VI characteristic diagram of the surge protection element according to the seventh embodiment.

FIG. 15A is a sectional view of the surge protection element according to the eighth embodiment taken along line KK of FIG. 16A. (B) FIG. 16 of the surge protection element according to the eighth embodiment
FIG. 3A is a sectional view taken along line MM of FIG.

FIG. 16A is a plan view of a surge protection element according to an eighth embodiment. (B) The bottom view of the surge protective element of 8th Embodiment.

FIG. 17A is a sectional view of the surge protection element according to the ninth embodiment, taken along line HH of FIG. 12A. (B) FIG. 12 of the surge protection element according to the ninth embodiment
Sectional drawing corresponding to the JJ line of (a).

FIG. 18 (a) is a sectional view of a surge protection element according to a tenth embodiment, corresponding to line KK in FIG. 16 (a). (B) FIG. 16 of the surge protection element according to the tenth embodiment
Sectional drawing corresponding to the MM line of (a).

FIG. 19A is a cross-sectional view of the surge protection element according to the eleventh embodiment, corresponding to the line HH in FIG. (B) FIG. 12 of the surge protection element of the eleventh embodiment
Sectional drawing corresponding to the JJ line of (a).

FIG. 20 (a) is a sectional view of a surge protection element according to a twelfth embodiment, corresponding to the line KK in FIG. 16 (a). (B) FIG. 16 of the surge protection element of the twelfth embodiment
Sectional drawing corresponding to the MM line of (a).

FIG. 21 (a) is a sectional view of the surge protection element according to the thirteenth embodiment taken along line EE of FIG. 22 (a). (B) FIG. 22 of the surge protection element of the thirteenth embodiment
(A) Sectional view on the FF line.

FIG. 22 (a) is a plan view of a surge protection element according to a thirteenth embodiment. (B) The bottom view of the surge protective element of a 13th embodiment.

FIG. 23 (a) is a VI lateral direction characteristic diagram of the surge protection element of the thirteenth embodiment on the side remote from the electronic circuit. (B) VI vertical direction characteristic diagram of the surge protection element of the thirteenth embodiment on the side remote from the electronic circuit.

FIG. 24 (a) is a VI lateral direction characteristic diagram of the surge protection element of the thirteenth embodiment on the side closer to the electronic circuit. (B) VI vertical direction characteristic diagram of the surge protection element of the thirteenth embodiment near the electronic circuit.

FIG. 25 is a surge protection circuit diagram using the surge protection element according to the thirteenth embodiment.

FIG. 26 is a cross-sectional view of a conventional surge protection element with respect to the surge protection element of the first embodiment.

FIG. 27 is a surge protection circuit diagram using the conventional surge protection element shown in FIG. 26;

FIG. 28 is a sectional view of a conventional surge protection element with respect to the surge protection element of the seventh embodiment.

FIG. 29 is a surge protection circuit diagram using the conventional surge protection element shown in FIG.

FIG. 30 is a circuit diagram of a surge protection circuit using another conventional surge protection element for the surge protection element of the seventh embodiment.

FIG. 31 is a sectional view of a conventional surge protection element with respect to the surge protection element of the thirteenth embodiment.

FIG. 32 is a sectional view of another conventional surge protection element with respect to the surge protection element of the thirteenth embodiment.

FIG. 33 is a surge protection circuit diagram using the conventional surge protection element shown in FIGS. 31 and 32.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Surge protection element 11 1st electrode 12 2nd electrode 13 3rd electrode 14 4th electrode 15 5th electrode 16 6th electrode 17 Trigger area

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshio Murakami 1-297 Kitabukurocho, Omiya City, Saitama Prefecture Mitsubishi Materials Research Institute

Claims (17)

[Claims] 1. A surge protection element comprising a plurality of pnpn-type or npnp-type thyristors, provided with first and second electrodes (11, 12) on the front surface and a third electrode (13) on the back surface. A part between the first electrode (11) and the third electrode (13) is formed in a thyristor structure, and another part between the first electrode (11) and the third electrode (13) Is formed in a pn junction structure, a part between the second electrode (12) and the third electrode (13) is formed in a thyristor junction structure, and the second electrode (12) and the third electrode ( 13), the other portion between the first electrode (11) and the second electrode (12) is formed in a bidirectional thyristor structure. Protective element. 2. An n-type or p-type first semiconductor layer as a substrate
(n ₁₀ ) and a pair of p-type or n-type second and third semiconductor layers (p ₂₀ ) exposed on the surface of the first semiconductor layer (n ₁₀ ) and formed separately from each other. , so that a p _30), are contained in the second and third semiconductor layers (p _20, p ₃₀₎ outer surface exposed to the outer surface and the second and third semiconductor layers (p _20, p ₃₀₎ N-type or p-type fourth
A semiconductor layer (n ₄₀ , n ₄₀ ) and a back surface of the first semiconductor layer (n ₁₀ ) are formed on the back surface of the first semiconductor layer (n ₁₀ ) so as to be exposed on the back surface and face the fourth semiconductor layer (n ₄₀ , n ₄₀ ) A fifth semiconductor layer (p ₅₀ , p ₅₀ ), and a back surface of the first semiconductor layer (n ₁₀ ), which is exposed on the back surface and faces the second and third semiconductor layers (p ₂₀ , p ₃₀ ). The sixth semiconductor layer (n ₆₀ , n ₆₀ ) formed in this way, the second semiconductor layer (p ₂₀ ) and the fourth semiconductor layer (n ₄₀ ) included therein are short-circuited on the respective outer surfaces. A second electrode formed by short-circuiting the first electrode (11) formed by the above, the third semiconductor layer (p ₃₀ ), and the fourth semiconductor layer (n ₄₀ ) included in the first semiconductor layer (p ₃₀ ) on the respective outer surfaces. An electrode (12); and a third electrode (13) formed by short-circuiting the fifth semiconductor layer (p ₅₀ , p ₅₀ ) and the first semiconductor layer (n ₁₀ ) on their respective outer surfaces. Surge protection according to claim 1 Child. 3. An n-type or p-type first semiconductor layer as a substrate
(n ₁₀ ) and a pair of p-type or n-type second and third semiconductor layers (p ₂₁ ) exposed on the surface of the first semiconductor layer (n ₁₀ ) and formed separately from each other. ^+, p ₃₁ ^+), said second semiconductor layer (p ₂₁ ⁺⁾ outer surface n-type so formed respectively as contained in the exposed on an outer surface and said second semiconductor layer (p ₂₁ ⁺⁾ or a p-type fourth semiconductor layer (n ₄₁ ⁺ ) and a p-type or n-type semiconductor layer (p ₂₂ ⁺⁺ ); and an outer surface of the third semiconductor layer (p ₃₁ ⁺ ). third semiconductor layer (p ₃₁ ⁺⁾ the n-type in each formed as encapsulated or p-type fourth semiconductor layer (n ₄₂ ⁺⁾ and p-type or n-type semiconductor layer and the (p ₃₂ ^++), said first semiconductor layer backside to a pair of p-type or n-type fifth semiconductor layer of the backside exposed to and formed respectively spaced apart from each other ^{_{(p 51 +, p 51 +}} ) and a pair of (n ₁₀₎ An n-type or p-type sixth semiconductor layer (n ₆₁ ⁺ , n _{6 1} ⁺ ), on each of the outer surfaces of the pair of fifth semiconductor layers (p ₅₁ ⁺ , p ₅₁ ⁺ ) so as to be exposed on this surface and included in the fifth semiconductor layers (p ₅₁ ⁺ , p ₅₁ ⁺ ). The p-type or n-type semiconductor layer (p ₅₂
^++, and p ₅₂ ^++), said second semiconductor layer (p ₂₁ ⁺⁾ and the fourth semiconductor layer which is included in this (n ₄₁ ⁺⁾ and a semiconductor layer (p ₂₂ ^{+ +)} and the respective outer surfaces , A first electrode (11) formed by short-circuiting, the third semiconductor layer (p ₃₁ ⁺ ), the fourth semiconductor layer (n ₄₂ ⁺ ) and the semiconductor layer (p ₃₂ ⁺⁺ ) included therein. A second electrode (12) formed by short-circuiting the respective outer surfaces, the pair of fifth semiconductor layers (p ₅₁ ⁺ , p ₅₁ ⁺ ), and the semiconductor layer (p ₅₂ ⁺⁺ included therein). , p ₅₂ ⁺⁺ ) and a pair of sixth semiconductor layers
The surge protection device according to claim 1, further comprising a third electrode (13) formed by short-circuiting (n ₆₁ ⁺ , n ₆₁ ⁺ ) with each other on respective outer surfaces. 4. The distance (w ₁ ) between the second semiconductor layer (p ₂₀ or p ₂₁ ⁺ ) and the third semiconductor layer (p ₃₀ or p ₃₁ ⁺ ) is equal to the fifth semiconductor layer (p
₅₀ or p ₅₁ ⁺ ) and a distance (w ₂ ) between the fifth semiconductor layer (p ₅₀ or p ₅₁ ⁺ ) and the second semiconductor layer (p ₂₀ or p ₂₁ ⁺ ) facing the fifth semiconductor layer (p ₅₀ or p ₅₁ ⁺ ).
And the fifth semiconductor layer (p ₅₀ or p ₅₁ ⁺ ) and the fifth semiconductor layer (p
The opposed to ₅₀ or p ₅₁ ⁺⁾ the third semiconductor layer (p ₃₀ or p ₃₁ ⁺⁾
The surge protection element according to claim 2 or 3, wherein the distance (w ₃ ) is smaller than or equal to, respectively. 5. The surge protection device according to claim 1, wherein a punch-through operation is performed between the first electrode and the second electrode against an overvoltage. 6. The first semiconductor layer (n ₁₀ ⁻ ) has the same conductivity type as the first semiconductor layer (n ₁₀ ⁻ ) and a higher impurity concentration than the first semiconductor layer (n ₁₀ ⁻ ) on the surface of the first semiconductor layer (n ₁₀ ⁻ ). The surge protection device according to any one of claims 2 to 4, wherein a seventh semiconductor layer ( _n70 ) is formed. 7. The seventh semiconductor layer (n ₇₀ ) is thicker than the second and third semiconductor layers (p ₂₀ , p ₃₀ or p ₂₁ ⁺ , p ₃₁ ⁺ ) and the second and third semiconductor layers (p _20). , p ₃₀ or p ₂₁ ^+, p ₃₁ ⁺⁾ surge protection device according to claim 6, wherein formed so as to include a. 8. The second and third semiconductor layers (n ₇₀ ) are thinner than the second and third semiconductor layers (p ₂₀ , p ₃₀ or p ₂₁ ⁺ , p ₃₁ ⁺ ).
Surrounding the semiconductor layer (p ₂₀ , p ₃₀ or p ₂₁ ⁺ , p ₃₁ ⁺ ) and
And the third semiconductor layer (p _20, p ₃₀ or p ₂₁ ^+, p ₃₁ ⁺⁾ of the first semiconductor layer (n ₁₀ ^-) surge protection device according to claim 6, wherein formed in contact with. 9. A surge protection element comprising a plurality of pnpn-type or npnp-type thyristors, in which first and second electrodes (11, 12) are provided on the front surface and a third electrode (13) is provided on the back surface. Between the first electrode (11) and the third electrode (13),
Between the electrode (12) and the third electrode (13) and the first electrode
A bidirectional thyristor structure between (11) and the second electrode (12). 10. An n-type or p-type first semiconductor layer (n ₁₀ ) serving as a substrate, and formed on the surface of said first semiconductor layer (n ₁₀ ) so as to be exposed on said surface and spaced apart from each other. The pair of p-type or n-type second and third semiconductor layers (p ₂₀ , p ₃₀ ) and the outer surfaces of the pair of second and third semiconductor layers (p ₂₀ , p ₃₀ ) are exposed to the outer surfaces. And the second and third semiconductor layers (p ₂₀ , p ₃₀ )
An n-type or p-type fourth semiconductor layer (n ₄₀ , n ₄₀ ) respectively formed so as to be included in the first semiconductor layer (n ₁₀ ); A single p-type or n-type fifth semiconductor layer (p ₅₀ ) formed opposite to the second and third semiconductor layers (p ₂₀ , p ₃₀ ), and an outer surface of the fifth semiconductor layer (p ₅₀ ) A pair of n-type or p-type sixth semiconductor layers (n ₆₀ , n ₄₀ ) formed so as to be exposed on the outer surface and not to face the fourth semiconductor layers (n ₄₀ , n ₄₀ ).
₆₀ ), a first electrode (11) formed by short-circuiting the second semiconductor layer (p ₂₀ ) and the fourth semiconductor layer (n ₄₀ ) contained therein on the respective outer surfaces, A second electrode (12) formed by short-circuiting the third semiconductor layer (p ₃₀ ) and the fourth semiconductor layer (n ₄₀ ) included in the third semiconductor layer (p ₃₀ ) on the respective outer surfaces, and the fifth semiconductor layer (p ₅₀ ) And the pair of sixth semiconductor layers (n ₆₀ ,
10. A bidirectional surge protection device according to claim 9, further comprising a third electrode (13) formed by short-circuiting n ₆₀ ) with each other on respective outer surfaces. 11. An n-type or p-type first semiconductor layer (n ₁₀ ) as a substrate, and formed on the surface of the first semiconductor layer (n ₁₀ ) so as to be exposed on the surface and separated from each other. A pair of p-type or n-type second and third semiconductor layers (p ₂₁ ⁺ , p ₃₁ ⁺ ), and an outer surface of the second semiconductor layer (p ₂₁ ⁺ ) exposed to the outer surface and the second semiconductor layer an n-type or p-type fourth semiconductor layer (n ₄₁ ⁺ ) and a p-type or n-type semiconductor layer (p ₂₂ ⁺⁺ ) respectively formed to be included in (p ₂₁ ⁺ ); the semiconductor layer (p ₃₁ ⁺⁾ outer surface exposed to the outer surface of and the third semiconductor layer n-type are respectively formed so as to be enclosed by the (p ₃₁ ⁺⁾ or p-type fourth semiconductor layer (n ₄₂ ⁺ ) And a p-type or n-type semiconductor layer (p ₃₂ ⁺⁺ ), and exposed on the back surface of the first semiconductor layer (n ₁₀ ) and the second and third semiconductor layers (p ₂₁ ⁺ , single p which is formed opposite to p ₃₁ ⁺⁾ Counter or n-type fifth semiconductor layer between the (p ₅₁ ^+), the fifth semiconductor layer on the outer surface of the (p ₅₁ ⁺⁾ exposed to the outer surface and the fourth semiconductor layer ^{_{(n 41 +, n 42 +}} ) to a pair of p-type or n-type semiconductor layer formed respectively by ^{_{(p 52 ++, p 5 2}} ++)
A pair of n-type or p-type exposed on the outer surface of the fifth semiconductor layer (p ₅₁ ⁺ ) and formed opposite to the semiconductor layer (p ₂₂ ⁺⁺ , p ₃₂ ⁺⁺ ). Sixth semiconductor layer (n ₆₁ ⁺ , n ₆₁ ⁺ )
A second semiconductor layer (p ₂₁ ⁺ ) and a fourth semiconductor layer (n ₄₁ ⁺ ) and a semiconductor layer (p ₂₂ ⁺⁺ ) included therein are short-circuited on their respective outer surfaces. One electrode (11), the third semiconductor layer (p ₃₁ ⁺ ) and the fourth semiconductor layer (n ₄₂ ⁺ ) and the semiconductor layer (p ₃₂ ⁺⁺ ) included therein are short-circuited on their outer surfaces. The second electrode (12) formed in this way, the fifth semiconductor layer (p ₅₁ ⁺ ) and the semiconductor layer (p ₅₂ ⁺⁺ , n ₆₁ ⁺ ) included therein are short-circuited on their respective outer surfaces. 10. The bidirectional surge protection device according to claim 9, further comprising a third electrode formed. 12. The distance (w ₁ ) between the second semiconductor layer (p ₂₀ or p ₂₁ ⁺ ) and the third semiconductor layer (p ₃₀ or p ₃₁ ⁺ ) is the fifth semiconductor layer.
(p ₅₀ or p ₅₁ ⁺⁾ fifth semiconductor layer of Toko (p ₅₀ or p ₅₁ ⁺⁾ in opposite the second semiconductor layer (p _20, or p ₂₁ ⁺⁾ the distance between the (w ₂₎
And the fifth semiconductor layer (p ₅₀ or p ₅₁ ⁺ ) and the fifth semiconductor layer (p
The opposed to ₅₀ or p ₅₁ ⁺⁾ the third semiconductor layer (p ₃₀ or p ₃₁ ⁺⁾
12. The bidirectional surge protection device according to claim 10, wherein the distance (w ₃ ) between them is smaller than or equal to each other. 13. The surge protection device according to claim 9, wherein a punch-through operation is performed between the first electrode (11) and the second electrode (12) against an overvoltage. 14. The first semiconductor layer (n ₁₀ ⁻ ) has the same conductivity type as the first semiconductor layer (n ₁₀ ⁻ ) on the front and back surfaces thereof, and has an impurity concentration higher than that of the first semiconductor layer (n ₁₀ ⁻ ). High seventh semiconductor layer
13. The bidirectional surge protection device according to claim 10, wherein (n ₇₀ ) and the eighth semiconductor layer (n ₈₀ ) are formed respectively. 15. The seventh semiconductor layer (n ₇₀ ) is thicker than the second and third semiconductor layers (p ₂₀ , p ₃₀ or p ₂₁ ⁺ , p ₃₁ ⁺ ) and the second and third semiconductor layers (p _20). , p ₃₀ or p ₂₁ ^+, are formed so as to include the p ₃₁ ^+), the eighth semiconductor layer (n ₈₀₎ is the fifth semiconductor layer (p ₅₀₎ or (p ₅₁ ⁺⁾ than thick and said fifth semiconductor layer (p ₅₀₎ or (p ₅₁ ⁺⁾ bidirectional surge protection device formed according to claim 14, wherein so as to include a. 16. The seventh semiconductor layer (n ₇₀₎ are second and third semiconductor layers (p _20, p ₃₀ or p ₂₁ ^+, p ₃₁ ⁺⁾ thinner the second and third semiconductor layers (p _20, contact with) ^- p ₃₀ or p ₂₁ ^+, p ₃₁ ⁺⁾ surrounds and the second and third semiconductor layers (p _20, p ₃₀ or p ₂₁ ^+, p ₃₁ ⁺⁾ of the first semiconductor layer (n ₁₀ is formed as eighth semiconductor layer (n ₈₀₎ is the fifth semiconductor layer (p ₅₀₎ or (p ₅₁ ⁺⁾ thinner the fifth semiconductor layer (p ₅₀₎ or (p ₅₁ ⁺⁾ surrounds and the The fifth semiconductor layer (p ₅₀ ) or (p ₅₁ ⁺ ) is ^replaced with the first semiconductor layer (n ₁₀ ⁻ )
15. The bidirectional surge protection device according to claim 14, wherein the device is formed so as to be in contact with. 17. A pnpn-type or npnp-type thyristor having first, second, third and fourth electrodes on a surface thereof.
(11,12,13,14), a fifth electrode (15) on the back surface facing the first and second electrodes, and a sixth electrode (15) facing the third and fourth electrodes. 16) provided with a surge protection element, wherein between the first electrode (11) and the fifth electrode (15) and between the second electrode (12) and the fifth electrode (15). Are respectively formed in a thyristor junction structure, and a portion between the third electrode (13) and the sixth electrode (16) and a portion between the fourth electrode (14) and the sixth electrode (16). Part of each is formed in a pn junction structure, and another part between the third electrode (13) and the sixth electrode (16) and the fourth electrode (14) and the sixth electrode (16) The other portion between the third electrode (13) and the fourth electrode (14) is formed into a thyristor junction structure, and a portion of the junction that determines a forward breakdown voltage between the third electrode (13) and the fourth electrode (14) is compared with the other portion. That the trigger region (17) with low withstand voltage was provided. Features a surge protection element.