JPH11167777A - Disk-shaped recording medium - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] CD-WO and CD-R capable of writing and rewriting data in block units and capable of managing data in block units
Data recording media such as AM. A recording track formed in a spiral shape.
3 is an optical disk 101 that forms a data block as a data recording unit along with an address area 104 having a track width changed in a burst shape;
And a data area 106 following the address area. In the data area, m-bit data is converted into n-bit data larger than the m-bit data,
A p-bit merging bit of a bit pattern corresponding to the value of V (Digital Sum Value) is inserted between n-bit data, and a "0" bit in a series of n-bit data and p-bit merging bit Is modulated and recorded so that it is equal to or more than a predetermined number d and equal to or less than k, and the DSV value is given independently for each data block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION For example, a CD-WO or a C-ROM according to the data format of a so-called compact disc (CD)
The present invention relates to a data recording medium applied to a data storage such as a D-RAM.

[0002]

2. Description of the Related Art Conventionally, a reproduction-only disk player device such as a CD player for reproducing a so-called compact disk (CD) in which an audio signal such as a sound or a musical sound is digitized and recorded on an optical disk has been generally provided.

In the above compact disc (CD), EFM (Eight to Fourteen) in which a signal of 8 bits per symbol is converted into data of 14 bits (1 channel bit).
Modulation) 24-bit synchronization signal given as data, 14-bit (one symbol) subcode, 14 ×
As shown in FIG. 6, one frame is composed of data and parity of 32 bits (32 symbols) of performance information and the like, and 588 bits composed of three margin bits provided between each symbol. The data format used as code blocks has been standardized,
The absolute address of the one subcode block is given by the Q channel signal of the subcode, and data processing is performed on data such as performance information in units of the one subcode block.

EF in the above compact disc (CD)
In M, modulation is performed so that the number of consecutive “0” bits is 2 or more and 10 or less in a series of 14-bit (1 symbol) data and 3-bit merging bits.
Also, the DSV (Digital S
um Value) is continuously counted, and the above-mentioned DSV is controlled by giving a merging bit having a bit pattern corresponding to the value of the DSV.

The digital audio signals of the left and right channels recorded on the compact disk (CD) are alternately successively arranged for each word (2 symbols = 16 bits) and treated as a one-channel serial data signal. In a CD-ROM or the like, a header portion and a synchronization signal are added prior to one subcode block, that is, 98 frames of data in the data format of the CD, so that the data format shown in FIG.
One sector (or one block) is composed of K bytes of data.

Further, since the conventional CD player is exclusively for reproduction, recording and reproduction can be performed using a magneto-optical disk formed of, for example, a magneto-optical recording medium on which information can be rewritten. CDs that maintain compatibility
-Development of data storage such as WO and CD-RAM has been progressed conventionally.

[0007]

In the CD data format, the DSV is continuously counted from the start position of the recording data as described above.
By giving the merging bit of the bit pattern according to the value of the above, the DSV is controlled,
Data cannot be written or rewritten in the middle. In data storage such as CD-WO and CD-RAM, it is necessary to efficiently manage data in block units.

Accordingly, the present invention has been made in view of the above-mentioned circumstances, and has been made in view of the above-described circumstances. It is intended to make it possible.

[0009]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention provides a disk-shaped recording device in which a data block as a data recording unit is formed along a spirally formed recording track. The data block includes a synchronization signal area in which a synchronization signal is recorded, and m
Bit data is converted to n-bit data larger than the m bits, and the DSV (Digital Sum Val
ue), a p-bit merging bit of a bit pattern according to the value of the bit pattern is inserted between the n-bit data, and "0" is set in the alternating sequence of the n-bit data and the p-bit merging bit. And a data area following the synchronization signal area, which is modulated and recorded so that the number of consecutive bits of "" is equal to or larger than d and equal to or smaller than k and larger than d.
It is characterized in that the value of V is given independently for each data block.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

A data recording medium according to the present invention records data generated by a modulation circuit having a configuration as shown in FIG. 1, for example. In the block diagram of FIG. 1 showing this modulation circuit, 1 is a data input terminal to which an 8-bit parallel data signal Sd is supplied from a CIRC encoder (not shown), and 2 is a 4.3218 MHz system clock signal Sc. And 3 and 4 are frame sync signals S of 7.35 kHz.
f and each sync input terminal to which one subcode block, that is, a block sync signal Sb for every 98 frames is supplied.

Here, between the frame sync signals Sf, as shown in FIG. 2, 32 8-bit parallel data signals Sd based on CIRC-encoded audio signals are formed, and 8-bit parallel sub-signals are formed. Code signal SC
Is formed, and the data signal Sd and the subcode signal S
C is selected at a predetermined timing by a selector (not shown) or the like and supplied to the data input terminal 1.

The data signal Sd is supplied from the data input terminal 1 to a read-only memory 11, where the data is converted from 8-bit data to 14-bit data according to a predetermined conversion table. 1 converted by the read-only memory 11
The data signal converted to 4-bit data is stored in register 1
2, 13, and 14 sequentially.

The system clock signal Sc, frame sync signal Sf and block sync signal Sb are:
The system control circuit 1 is connected via the input terminals 2, 3, and 4
5. The system control circuit 15 controls the system clock signal Sc and the frame sync signal Sf.
Based on the block sync signal Sb, the operation of each circuit block is controlled in units of 98 frames, that is, one subcode block.

Here, in the CD data format, the sync pattern in the data signal is [100000
0000010000000000010], and in this embodiment, the above-described register 1
Since 2, 13, and 14 handle 14-bit data, they are handled by replacing them with a 14-bit pattern of [1000000000000100].
The bit sync pattern is restored. The 14-bit pattern data is read-only memory 16 and supplied to the registers 12, 13, and 14 by a signal from the system control circuit 15 corresponding to the frame sync signal Sf. Also, in the above-described sub-code signal, specific pattern data of S ₀ = [001000000000001] S ₁ = [00000000000010010] is inserted for each sub-code block, ie, every 98 frames, so that these signals S ₀ and S ₁ is formed in the read-only memory 16 by a signal from the system control circuit 15 corresponding to the block sync signal Sb, and
2, 13, and 14.

These signals are applied to the registers 12, 13,
By being sequentially transferred at 14, the data held immediately before the data held in the register 12 is held in the register 13, and the data immediately before the data held in the register 12 is held in the register 14.

The read-only memories 11, 1
Since the number of leading "0" s and the number of trailing "0" s of the 14-bit data formed in 6 are uniquely determined by the data signal Sd, these values are formed simultaneously with the data signal. Here, the number of leading and trailing "0" s of the 14-bit data is determined to be 9 or less in the above conversion table, and is represented by 4 bits. In the sync pattern, the number of "0" at the end of the 14-bit replacement data is two, but in the 24-bit pattern, it is one, so the number of "0" at the end in this case is [000].
1]. These 4-bit signals are also transferred in the registers 12, 13, and 14 in the same manner as the data signals.

A numerical value F ₁ indicating the number of “0” at the front end of the register 12 and a numerical value B ₂ indicating the number of “0” at the end of the register 13 are read-only memories forming three merging bits. It is supplied to addresses 17 and 18.

Here, the merging bit is stored in the read only memories 17 and 18.

Four types of bit patterns satisfying the above-mentioned rule of setting the number of consecutive “0” of [000], [001], [010], and [100] to 2 or more are selected. Also, the merging bit needs to satisfy the rule that the number of consecutive “0” s inserted between the preceding and succeeding data signals is 2 or more and 10 or less. as an address a number B ₂ indicating the number of numerical values of F ₁ and terminating "0" indicates the bit pattern except for the combination which does not satisfy the above rule is selected. Further, the merging bit is inserted between the preceding and succeeding data signals, so as not to coincide with the above-mentioned 24-bit sync pattern.
If the pattern of the data signal before and after is one of the following 11 patterns, the X of each merging bit
Combinations marked with are removed. The merging bits indicate all cases selected by the above numerical values F ₁ and B ₂ .

[0020]

(Equation 1)

The above 11 bit patterns can be distinguished by the current data, the previous data, the previous data, and the previous merging bit. In this embodiment, all the merging bits are output from the read only memory 17 for the numerical values F ₁ and B ₂ , and the read only memory 18 outputs
A merging bit is output from the above-mentioned numerical values F ₁ and B _{2 in one} case, excluding the combination marked with a cross. Further, the data signal held in the registers 12, 13, and 14 and the immediately preceding merging bit held in a register 42, which will be described later, are supplied to the detection circuit 19, and the detection circuit 19 outputs Cases are detected. Normally, the read only memory 17 is selected by the detection signal from the detection circuit 19, and in the case of the above 11 cases, the read only memory 18 is selected.
Is selected.

In this embodiment, the merging bits output from the read only memories 17 and 18 are:
It is supplied to the selector 20. The numerical values of 0 to 3 are sequentially supplied to the selector 21 from the system control circuit 15. The selector 21 initially selects the system control circuit 15 side, and provides the selector 20 with numerical values of 0 to 3 from the system control circuit 15. Thus, the selector 20 selects an input, that is, a merging bit, according to the numerical value [0 to 3] from the system control circuit 15.

The merging bit selected by the selector 20 is supplied to the address of the read only memory 22, and the read only memory 22 uses the DSV (Dig) of the digital signal constituting the merging bit.
Ital Sum Value) and the polarity signal are formed. The data signal of the register 12 is transmitted to the read only memory 2.
The data is supplied to the address No. 3 and the read-only memory 23 forms a digital signal DSV (Digital Sum Value) of the data signal and a polarity signal. The DS of this data signal and the merging bit
The signals indicating V and polarity are respectively supplied to the DSV register 24,
25, and are supplied to polarity registers 26 and 27.

The signals from the DSV registers 24 and 25 are supplied to one input A of an addition / subtraction circuit 28.
A signal from the accumulation DSV register 29 is supplied to the other input B of the addition / subtraction circuit 28. Further, the signals from the polarity registers 26 and 27 and the signal from the cumulative polarity register 30 are supplied to a combinational logic circuit 31.
Control of addition and subtraction of 8 is performed.

The output signal of the addition / subtraction circuit 28 is supplied to registers 32 and 33 and also to registers 35 and 36 via an absolute value circuit 34. The output signal of the register 36 is supplied to one input A of the addition / subtraction circuit 28. Further, the above register 3
The output signals of 2, 33 and 35 are supplied to the other input B of the addition / subtraction circuit 28, and the accumulated DSV
It is supplied to a register 29.

A signal from the logic circuit 31 is supplied to a selector 37. Further, the polarity register 38
Is supplied to the selector 37. The selector 37 is controlled by a signal from the addition / subtraction circuit 28. The signal from the selector 37 is supplied to the polarity register 38. The signal from the polarity register 38 is supplied to the cumulative polarity register 30.

Further, the numerical value supplied from the system control circuit 15 to the selector 21 is also supplied to the selector 39. The selector 39 includes an indicator 40
The selector 39 is controlled by a signal from the addition / subtraction circuit 28, and a signal from the selector 39 is supplied to the indicator 40. Further, a signal from the indicator 40 is supplied to the selector 21.

These circuits are controlled by signals from the system control circuit 15 to remove combinations that are problematic in the rules of the data format of the CD and to merge optimal combinations for suppressing the DC component. Bit selection is performed.

Here, in order to serially output a set of a 14-bit data signal and a 3-bit merging bit signal, 17 clock periods of 14 + 3 = 17 are required, and all of the above data are processed in parallel. In this case, as shown in FIG. 3, processing is performed at timings 0 to 16 using 17 time slots A to R, and a new 14-bit pattern is input at the next timing 0.

That is, first, at timing 0, arbitrary 14-bit data is set in the register 12. Then, during the period A, each of the read-only memories 17, 1
8, 20, and 23, and the selector 2
The read-only memory 22 is accessed by the first merging bit selected at 0.

Next, at timing 1, the data signals from the read only memories 22 and 23 and the DSV and polarity of the first merging bit are stored in the registers 24 and 27.
Set to. In the period B, the above register 2
5 and 29 are selected and supplied to the addition / subtraction circuit 28, and the logic circuit 31 takes out the polarity of the register 30 as it is and supplies it to the addition / subtraction circuit 28. When the polarity is negative "0", the addition is performed. A + B is performed, and when the polarity is positive “1”, subtraction AB is performed.

The operation result of the addition / subtraction circuit 28 is set in the register 32 at timing 2, and the absolute value of this value is set in the register 35. During the period C, the outputs of the registers 32 and 24 are selected and supplied to the addition / subtraction circuit 28, and the logic circuit 31 extracts the exclusive OR of the outputs of the registers 30 and 27. The addition / subtraction circuit 28 is controlled by the polarity.

The operation result and the absolute value of the addition / subtraction circuit 28 are set in the registers 32 and 35 at the timing 3, and the exclusive OR operation of the exclusive OR output by the logic circuit 31 and the contents of the register 26 is performed. The sum is taken out and set in the register 38, and 0 is set in the indicator 40.

During this period C, the selector 20
Selects the second merging bit, and sets the output of the read only memory 22 in the registers 25 and 26 at timing 3. Then, during the period D, the outputs of the registers 25 and 29 are set in the addition / subtraction circuit 28, and an operation according to the polarity of the register 30 is performed in the addition / subtraction circuit 28.

The operation result and the absolute value of the addition / subtraction circuit 28 are set in the registers 33 and 36 at timing 4. Then, during the period E, the outputs of the registers 33 and 24 are set in the addition / subtraction circuit 28, and an operation according to the polarity of the exclusive OR of the registers 30 and 26 is performed in the addition / subtraction circuit 28.

The operation result and the absolute value of the addition / subtraction circuit 28 are set in the registers 33 and 36 at timing 5. In the period F, the outputs of the registers 35 and 36 are set in the addition / subtraction circuit 28, and the calculation of BA is performed by the addition / subtraction circuit 28.

At timing 6, when the operation result of the addition / subtraction circuit 28 is positive, the absolute value of the content of the register 32 is larger than the absolute value of the content of the register 33. The contents are transferred to the register 32, and
The exclusive OR of the contents of 0 and 26 and the exclusive OR of the contents of the register 27 are extracted and set in the register 38, and 1 is set in the indicator 40.

During this period F, the selector 20
Selects the third merging bit, and sets the output of the read only memory 22 in the registers 25 and 26 at timing 6.

In the same manner, the operation for the third merging bit is performed in the periods G to I, and the operation result is set in the indicator 40 at timing 9.

Further, the fourth merging bit is set at timing 9, and the arithmetic processing for this is performed during the period J.
To L, and the calculation result is set in the indicator 40 at the timing 12.

During the period M, the selector 21 is switched to the indicator 40 side, the selector 20 is switched according to the contents of the indicator 40, and the optimum merging bit selected at the timing 13 is supplied to the register 41. I do. At this time, since the contents of the registers 32 and 38 are the accumulated DSV and the polarity corresponding to the above-mentioned optimum merging bits, these values are set in the registers 29 and 30.

Further, the contents of the register 41 are transferred to the register 42 at the next timing 0,
The two 3-bit merging bits and the 14-bit data signal of the register 13 are combined, and a 17-bit signal is supplied to the shift register 43 for parallel-serial conversion. The contents of the shift register 43 are read out in accordance with the system clock signal Sc, the sync pattern is restored by the exclusive OR circuit 44, and output from the output terminal 46 via the flip-flop 45.

In this embodiment, the above-mentioned cumulative DSV
By resetting the registers 29 and 30 that hold the polarity and the polarity for each 98 subframes, that is, for each subcode block, D
SV is controlled, and recording data is formed by inserting merging bits of a bit pattern corresponding to the DSV value between the n (n = 14) bit data. The recording data is independent D data for each sub-code block.
Since SV control is performed, it is possible to individually manage and record / reproduce as block data having one subcode block unit as one sector.

The data block of one subcode block (one sector) thus obtained is recorded on, for example, an optical disk 101 as shown in FIG.

In FIG. 4, which schematically shows the whole and a part of the data recording medium according to the present invention in an enlarged scale, an optical disk 101 has a perpendicular magnetization film having a magneto-optical effect as a recording medium formed on a transparent substrate. Pre-groove 10 formed in a spiral shape using a magneto-optical disk
The land between the two is a recording track 103. For example, the CD-RO obtained by the modulation circuit shown in FIG.
Block data of 2 Kbytes complete according to the M data format is magneto-optically recorded on the recording track 103.

The recording track 103 has the CD-
At equal intervals corresponding to the synchronization signal (SYNC) portion or the error correction signal (ECC) portion in the data format of the ROM, an address area 104 whose track width is changed in a burst shape is provided. Due to the change, for example, 19-bit address information is recorded in each address area 104 in advance. The signal spectrum of the address information due to the change in the track width is a component above the servo band.

In the optical disc 101, a lead-in area 107 is provided on the inner peripheral side of a data area 106 in which data is recorded, and lead-in information indicating the recording status of the data area 106 is stored in the lead-in area 107. Is recorded.

As described above, the optical disc 101 having the recording track 103 in which the address information of a predetermined bit is previously recorded in each address area 104 due to the change of the track width.
Is used as a data storage, a four-divided detector 110 composed of detectors A, B, C, and D as shown in FIG. 5 is used as an optical pickup for reading data. Each output S _A , S of each detector A, B, C, D
_The data signal RF can be detected as an added output signal (S _A + S _B + S _C + S _D ) obtained by adding _B , S _C , and S _D by the adder 111, and the longitudinal direction (X -X 'direction) arrayed in that each detector a, the output S _a of B, S sum output S _AB and the respective detectors C by the adder 112 of _B, the output S _C and D, the addition of S _D Output signal (S _AB -S _CD ) obtained by subtracting the addition output S _CD from the adder 113 with the subtractor 114, that is, the detectors A arranged in the width direction (YY ′ direction) of the recording track 103. , B and the outputs S _A , S _B , S _C , S _D of the detectors C, D can be detected as push-pull outputs of the address information ADR.

In the optical disk 101, the recording data is managed by individually controlling the recording data subjected to DSV control independently for each subcode block unit as one sector block data for each subcode block unit.
It can be recorded and reproduced.

[0050]

According to the disk-shaped recording medium of the present invention,
Since the DSV of the recording data is independently controlled in data block units, writing or rewriting the recording data in data block units does not affect the contents of the recording data in other data blocks. Therefore, according to the present invention, data can be written or rewritten in block units on a data recording medium such as CD-WO or CD-RAM, and data management in block units can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a modulation circuit used to carry out the present invention.

FIG. 2 is a schematic diagram showing a relationship between signals in the modulation circuit.

FIG. 3 is a time chart for explaining the operation of the modulation circuit.

FIG. 4 is a schematic plan view of an optical disc to which the present invention is applied.

FIG. 5 is a schematic diagram showing a configuration of an optical pickup for reading data from the optical disc.

FIG. 6 is a schematic diagram showing a data format of a compact disc (CD).

FIG. 7 is a schematic diagram showing a data format of a CD-ROM.

[Explanation of symbols]

101 optical disk, 103 recording track, 104
Address area, 106 data area

Claims (1)

[Claims] 1. A disk-shaped recording medium in which a data block as a data recording unit is formed along a spirally formed recording track, wherein the data block is a synchronization signal on which a synchronization signal is recorded. The area and the m-bit data are converted to n-bit data larger than the m bits, and the DSV (Digital Sum V
alue), a p-bit merging bit having a bit pattern corresponding to the value of “n” is inserted between the n-bit data, and “0” is included in the alternating sequence of the n-bit data and the p-bit merging bit. And a data area subsequent to the synchronization signal area, which is modulated and recorded so that the number of consecutive bits of "" is equal to or greater than a predetermined d and equal to or less than k, and the data area is the DSV A data recording medium in which the values are independently given for each data block.