JPH11150426A - Monolithic high frequency ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve electrostatic destruction resistance, without increasing the area of MIM capacitors by having an IC contain a capacitor whose one electrode is connected to a pad and connecting at leas one electrode on the pad-side of one capacitor to the source or drain of a FET in the IC by lines of low resistance with respect to DC and high impedance with respect to high frequency. SOLUTION: The electrode of a bonding pad-side in the electrodes of MIM capacitors C1-C3 is connected to the source of GaAs a FETQ1 in a first stage or a GaAs FETQ2 in a second stage through lines S1-S3. Thus, the MIM capacitors C1-C3 are imparted with current leak paths, and electrostatic destruction resistance is improved. When the lines S1-S3 re set to be high impedance in terms of high frequency, the grounding ability of the FaAs FETQ1 and Q2 can be prevent from deteriorating. Thus, a capacity insulating film can be thinned, and the areas of the MIM capacitors C1-C3 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic high-frequency IC using a compound semiconductor [hereinafter referred to as an MMIC (monoli
thic microwave IC), and more particularly to a connection structure of a capacitor in an MMIC.

[0002]

2. Description of the Related Art MMI which is a monolithic analog IC
C is generally configured by integrating an FET, a capacitor, a resistor, an inductance element, and the like on a semi-insulating GaAs substrate. A two-stage power amplifier will be described as an example of a conventional MMIC with reference to FIG. 2 which is an equivalent circuit diagram thereof.

In FIG. 2, IN and OUT are RF input / output bonding pads, VG1 and VG2 are gate bias bonding pads, VD1 and VD2 are drain bias bonding pads, and GND is a ground bonding pad. C1 to C7 are MIM capacitors, L1 to L5 are inductors, Q1 and Q2 are GaAs FETs, and R1 and R2 are resistance elements. In the MMIC used in the microwave band, the ground terminal (source in this case) of the FET is independently arranged as shown in FIG. 2 in order to improve the grounding property and reduce the interference with the input (gate) side. Often. The circuit configuration will be described below. C1, L1, C2, and R1 constitute a matching circuit on the input side and a gate bias circuit of the first-stage FET (Q1). Similarly, the gate bias circuit of the second-stage FET (Q2) includes L2, C3, and R2. First stage FET
A matching circuit between the FET and the second-stage FET is constituted by L3 and C4. L4 and C5 are drain bias circuits of the first stage FET (Q1), and L5 and C6 are second stage FETs (Q1).
The drain bias circuit of 2) is configured. C7
Is a coupling capacitor.

Now, considering the period from the completion of the MMIC chip shown in FIG. 2 to the completion of assembly, the ground terminal (GND) is not grounded yet, so that the FE
Elements other than T and the elements connected to the source / drain of the FET are in a floating state with respect to the substrate. FE
Since T has a leak current path between the source and the substrate and between the drain and the substrate, the element connected to the source or the drain does not enter a floating state. When static electricity is applied to such a circuit from a bonding pad, the MIM capacitors C1 and C
2 and C3 are C4 and C having a leak path through the FET.
5, C6 and C7 are more susceptible to electrostatic breakdown. In order to ensure sufficient electrostatic breakdown resistance, the capacity of the MIM capacitor may be increased, or the capacitance insulating film may be increased. However, an increase in the capacitance of the MIM capacitor has a circuit design upper limit, and the degree of freedom in circuit design is reduced. Therefore, it is easier to increase the thickness of the capacitance insulating film. In order to secure the electrostatic breakdown resistance by increasing the thickness of the capacitive insulating film, the film thickness must be designed in accordance with the lowest resistance, that is, C1, C2, and C3.

[0005]

Normally, in order to avoid complication of the process, all the capacitor insulating films of the MIM capacitor are formed to have the same thickness. Therefore, as described above, if the capacitance insulating film of the capacitor having the lowest electrostatic breakdown strength is made to have a film thickness that can secure a sufficient electrostatic breakdown strength, the capacitance insulating film of another capacitor which does not need to be thicker from the viewpoint of the breakdown voltage is also required. Thick and large MIM to secure required capacity
This requires a capacitor area. This has hindered a reduction in chip area. It is considered that the area of the MIM capacitor can be reduced by inserting some protection circuit, specifically, a buffer element that temporarily receives electric charge. However, the reduction in the area of the MIM capacitor and the increase in the area of the buffer element cancel each other. Therefore, it cannot be an effective measure.

An object of the present invention is to provide a conventional MMIC as described above.
Is to solve the problem of
An object is to improve electrostatic breakdown resistance without increasing the area of a capacitor.

[0007]

SUMMARY OF THE INVENTION A monolithic high frequency IC according to the present invention includes an FET integrated on a semi-insulating GaAs substrate and a capacitor having at least one electrode directly connected to a pad. 1
The electrode on the pad side of one capacitor is connected to the source or drain of the FET in the IC by a line having low resistance in DC. If necessary, the DC low-resistance line has a high-frequency high impedance. Further, the capacitor having the MIM structure is used.

[Operation] In the compound semiconductor MMIC of the present invention, the electrode connected to the bonding pad of the MIM capacitor is connected by a DC-low resistance line.
Connect to source or drain of FET on MMIC. Although this is not the case with an ideal FET, a current leak path exists between a source and a substrate and between a drain and a substrate in an actual FET. Further, in MMICs, particularly in power amplifiers, large FETs having a gate width of several mm to several tens mm are often used. Therefore, the FET in the MMIC can function as a sufficiently large buffer element. In other words, the MIM capacitor connected to the source or drain of the FET by a DC low-resistance line has improved resistance to electrostatic breakdown due to the presence of the leak path formed in this way, and allows the capacitance insulating film to be made thinner. Become. As a result, the area of the MIM capacitor can be reduced, and the chip size can be reduced. It should be noted that the connection between the MIM capacitor and the FET via a high-impedance line at a high frequency is, for example, shown in FIG.
This is to prevent the grounding of the FET from being deteriorated when connected to the source (GND) side as described above, and to prevent interference from the output side to the input side.

[0009]

Next, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit in which lines S1 to S3 such as strip lines are added to the circuit of FIG.
FIG. 3 is an equivalent circuit diagram of an MMIC in which MIM capacitors C1 to C3 having low electrostatic breakdown resistance have improved electrostatic breakdown resistance. S
Since 1 to S3 are conductor lines, they have low resistance in terms of DC. The electrodes on the bonding pad side of the electrodes of the MIM capacitors C1 to C3 are S1 to S3, respectively.
3, the first stage FET (Q1) or the second stage FET
(Q2). As a result, C1
C3 has a current leak path, and the electrostatic breakdown resistance is improved. Here, if S1 to S3 are set to high impedance in terms of high frequency, the grounding properties of Q1 and Q2 will not be degraded and the interference to the input side can be suppressed to a small level. As S1 to S3, a strip line (or microstrip line) having a length of 波長 wavelength of the operating frequency may be used, or a low resistance line sufficiently thinner than the thickness of the substrate may be used.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG. This example is a two-stage high-frequency power amplifier having an operation frequency of 10 GHz formed on a semi-insulating GaAs substrate. The gate width of the first stage FET (Q1) is 1.
5 mm, the second-stage FET (Q2) is 6 mm. MI
The M capacitors C1 to C3 are connected to Q1 or Q1 by a strip line (about 2 mm in length) having a quarter wavelength of the operating frequency.
2 and a leak path for the electric charge is secured. By connecting with a 1/4 wavelength strip line, C1 to C3 and the source of the FET are separated from each other in terms of high frequency.

In other MIM capacitors, C4 to C
6 is connected to Q1 or Q2 through an inductor having a low DC resistance.
2 is connected to the drain side. C7 is directly connected to the drain of Q2. That is, all MIs from C1 to C7
Since the M capacitor is connected to the source or drain of Q1 or Q2, there is no MIM capacitor having a small electrostatic breakdown resistance. Since the minimum value of the electrostatic breakdown resistance is improved, the capacitance insulating film can be thinned. Therefore, the area of the MIM capacitor can be reduced.

Referring to FIG. 1 again, a second embodiment of the present invention will be described. This embodiment is a two-stage power amplifier having an operation frequency of 2 GHz. At this operating frequency, the quarter wavelength becomes as long as about 11 mm (the height of the GaAs substrate). Therefore, it is not preferable in terms of chip area to use a quarter wavelength strip line. Therefore, in this case, the thickness of the substrate (2
MIM capacitors C1 to C3 are connected to the source of Q1 or Q2 through a conductor line (10 μm in width) that is sufficiently narrow. 2-5μm thickness for conductor line
If the Au plating wire is used, a wiring having a sufficiently high impedance at high frequencies and a low resistance at DC can be obtained.

[0013]

As described above, the MM according to the present invention is used.
Since the IC has an electrode on the bonding pad side of a capacitor having low electrostatic breakdown resistance connected to a source or a drain having a leak path to the substrate by a low resistance line, the IC has a partial resistance to electrostatic breakdown. Capacitors no longer exist. Therefore, according to the present invention, the capacitance insulating film can be made thinner, whereby the size of the capacitor can be reduced, and the chip size of the MMIC can be reduced.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram for describing an embodiment and an example of the present invention.

FIG. 2 is an equivalent circuit diagram of a conventional MMIC.

[Explanation of symbols]

 IN RF input bonding pad OUT RF output bonding pad VG1, VG2 Gate bias bonding pad VD1, VD2 Drain bias bonding pad GND Ground bonding pad C1-C7 MIM capacitor L1-L5 Inductor Q1, Q2 GaAs FET R1, R2 Resistance S1-S3 Line

Claims (5)

[Claims] In a compound semiconductor monolithic high-frequency IC including an FET and a capacitor in which at least one electrode is directly connected to a pad, an electrode on a pad side of at least one capacitor is connected to the inside of the IC by a line having a low DC resistance. A monolithic high-frequency IC connected to the source or drain of an FET. 2. The monolithic high-frequency IC according to claim 1, wherein the DC low-resistance line has a high-frequency high impedance. 3. The monolithic high-frequency IC according to claim 1, wherein the FETs are connected in multiple stages to form a power amplifier. 4. The monolithic high-frequency IC according to claim 1, wherein said capacitor is a capacitor having an MIM structure. 5. The monolithic high-frequency IC according to claim 1, wherein the line having a low DC resistance is a strip line, a microstrip line, or a conductor line having a width sufficiently narrow with respect to a substrate thickness.