JPH11150037A - Laminated ceramic capacitor - Google Patents
Laminated ceramic capacitorInfo
- Publication number
- JPH11150037A JPH11150037A JP9335006A JP33500697A JPH11150037A JP H11150037 A JPH11150037 A JP H11150037A JP 9335006 A JP9335006 A JP 9335006A JP 33500697 A JP33500697 A JP 33500697A JP H11150037 A JPH11150037 A JP H11150037A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- layer
- layers
- dielectric layer
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003985 ceramic capacitor Substances 0.000 title claims abstract description 30
- 239000003990 capacitor Substances 0.000 claims abstract description 101
- 239000010410 layer Substances 0.000 claims description 167
- 239000002344 surface layer Substances 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 abstract description 29
- 239000003989 dielectric material Substances 0.000 abstract description 2
- 230000002265 prevention Effects 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 5
- 238000010030 laminating Methods 0.000 description 5
- 239000002002 slurry Substances 0.000 description 5
- 238000007606 doctor blade method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000002003 electrode paste Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、高電圧回路等に使
用される大容量で高耐電圧の積層構造を有する積層セラ
ミックコンデンサに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor having a large capacity and a high withstand voltage laminated structure used for a high voltage circuit or the like.
【0002】[0002]
【従来の技術】一般に、積層セラミックコンデンサは内
部電極を誘電体層となるセラミックグリーンシートのシ
ート面に印刷し、これを複数枚積層させてコンデンサ層
を形成すると共に、外表面層を形成する最外誘電体層を
重ね合わせて一体に燒結することによりコンデンサ素子
を形成し、更に、コンデンサ層の内部電極と電気的に接
続する一対の外部電極をコンデンサ素子の両端部に設け
ることにより構成されている。2. Description of the Related Art Generally, in a multilayer ceramic capacitor, an internal electrode is printed on the surface of a ceramic green sheet serving as a dielectric layer, and a plurality of these are laminated to form a capacitor layer and an outer surface layer. A capacitor element is formed by superposing and sintering the outer dielectric layers together, and furthermore, a pair of external electrodes electrically connected to the internal electrodes of the capacitor layer are provided at both ends of the capacitor element. I have.
【0003】その積層セラミックコンデンサは、大容量
化の要請から内部電極並びに誘電体層の層数を増加する
傾向にある。然し、チタン酸バリウム等を主成分とする
高誘電率系の誘電体材料は誘電率(ε)が1,000〜
20,000と高くて双極子を形成し易い結晶構造のも
ので、大きな歪みを有し且つ膨張,収縮するものである
ため、電圧の印加に伴って電圧を機械的に変化させる圧
電現象または逆圧電現象,即ち、電歪現象が起き易い。[0003] The multilayer ceramic capacitor tends to increase the number of internal electrodes and dielectric layers due to a demand for large capacity. However, a dielectric material having a high dielectric constant based on barium titanate or the like has a dielectric constant (ε) of 1,000 to 1,000.
Since it has a crystal structure that is as high as 20,000 and easily forms a dipole, has a large strain and expands and contracts, a piezoelectric phenomenon or a reverse phenomenon in which a voltage is mechanically changed with the application of a voltage is applied. A piezoelectric phenomenon, that is, an electrostrictive phenomenon is likely to occur.
【0004】そのため、積層セラミックコンデンサでは
内部電極並びに誘電体層の層数を単に増やすだけである
と、電歪現象から絶縁破壊の電圧域に達する前に膨張,
収縮の繰り返しで、機械的応力破壊によるクラックがコ
ンデンサ素子に発生し、絶縁破壊電圧や電歪破壊発生電
圧のような耐電圧レベルが低くなってしまう。このクラ
ックの発生を防止するにはコンデンサ層の誘電体層を厚
く形成することがあるが、これでは全体形状が大きくな
るばかりでなく、誘電体層を厚くすることによって容量
の低下を招くことになる。For this reason, in a multilayer ceramic capacitor, if the number of internal electrodes and dielectric layers is simply increased, the expansion and expansion of the capacitor before the dielectric breakdown voltage range is reached due to the electrostriction phenomenon.
By the repetition of contraction, cracks are generated in the capacitor element due to mechanical stress destruction, and the withstand voltage level such as the dielectric breakdown voltage or the electrostriction breakdown generation voltage is lowered. In order to prevent the occurrence of cracks, the dielectric layer of the capacitor layer may be formed to be thick. However, this not only increases the overall shape but also causes a decrease in capacitance due to the thick dielectric layer. Become.
【0005】従来、半田付けによる熱的ストレスの影響
によりクラックがコンデンサ素子に生ずるのを防止し、
または、表面層から侵入する水分と電極間の直流電圧に
より電極材料が移動することによる絶縁抵抗の低下や短
絡を防止することから、中間が分離されて外部電極と電
気的に接続される一対の電極を誘電体層の同一面に設
け、その誘電体層を最外誘電体層とコンデンサ層の間に
介在させてコンデンサ素子を構成することが提案されて
いる(特開平1ー220420号,実開平5ー6695
1号)。Conventionally, cracks are prevented from being generated in a capacitor element due to the influence of thermal stress due to soldering.
Alternatively, since a reduction in insulation resistance or a short circuit caused by the movement of the electrode material due to the moisture invading from the surface layer and the DC voltage between the electrodes is prevented, a pair of intermediate members are separated and electrically connected to the external electrode. It has been proposed that an electrode is provided on the same surface of a dielectric layer, and that the dielectric layer is interposed between the outermost dielectric layer and the capacitor layer to constitute a capacitor element (Japanese Patent Laid-Open No. 1-242020, Japanese Patent Application Laid-Open No. Hei. Kaihei 5-6695
No. 1).
【0006】また、電圧破壊が外部電極の折返し先端と
内部電極の先端との間で生ずるのを防止し、電界強度も
低減させて耐電圧を向上することから、上述したものと
同様な中間が分離されて外部電極と電気的に接続される
一対の電極を同一面に設けた誘電体層を最外誘電体層側
に配置すると共に、その誘電体層とコンデンサ層の間に
は外部電極に接続されない浮遊電極を設けた誘電体層を
介在させてコンデンサ素子を形成することも提案されて
いる(実開昭60ー99522号)。Further, since voltage breakdown is prevented from occurring between the folded tip of the external electrode and the tip of the internal electrode, the electric field strength is reduced, and the withstand voltage is improved. A dielectric layer in which a pair of electrodes separated and electrically connected to an external electrode are provided on the same surface is arranged on the outermost dielectric layer side, and an external electrode is provided between the dielectric layer and the capacitor layer. It has also been proposed to form a capacitor element with a dielectric layer provided with a floating electrode not connected (Japanese Utility Model Application Laid-Open No. 60-99522).
【0007】然し、上述した誘電体層を付加しただけで
は、内部電極並びに誘電体層の層数を増やことに伴う電
歪現象から、機械的応力破壊によるクラックがコンデン
サ素子に発生するのを確実に防ぐことはできない。However, simply adding the above-described dielectric layer prevents the occurrence of cracks in the capacitor element due to mechanical stress destruction due to the electrostriction phenomenon caused by increasing the number of internal electrodes and dielectric layers. It cannot be surely prevented.
【0008】[0008]
【発明が解決しようとする課題】本発明は、内部電極並
びに誘電体層の層数を増やすことにより高容量値を確保
すると共に、絶縁破壊電圧,電歪破壊発生電圧を高め、
機械的応力破壊によるクラックがコンデンサ素子に生ず
るのを確実に防げる積層セラミックコンデンサを提供す
ることを目的とする。SUMMARY OF THE INVENTION According to the present invention, a high capacitance value is ensured by increasing the number of internal electrodes and dielectric layers, and a dielectric breakdown voltage and an electrostriction breakdown occurrence voltage are increased.
An object of the present invention is to provide a multilayer ceramic capacitor capable of reliably preventing a crack due to mechanical stress breakdown from occurring in a capacitor element.
【0009】また、本発明は絶縁破壊電圧,電歪破壊発
生電圧と共に、沿面放電発生電圧も高められる積層セラ
ミックコンデンサを提供することを目的とする。It is another object of the present invention to provide a multilayer ceramic capacitor capable of increasing a creeping discharge generation voltage as well as a dielectric breakdown voltage and an electrostriction breakdown generation voltage.
【0010】[0010]
【課題を解決するための手段】本発明の請求項1に係る
積層セラミックコンデンサにおいては、複数個のコンデ
ンサ層と、外表面層を形成する最外誘電体層とに加え、
コンデンサ層の誘電体層よりも厚みの厚い中間誘電体層
を該コンデンサ層の間に介在させることによりコンデン
サ素子が構成されている。In the multilayer ceramic capacitor according to the first aspect of the present invention, in addition to a plurality of capacitor layers and an outermost dielectric layer forming an outer surface layer,
A capacitor element is constituted by interposing an intermediate dielectric layer thicker than the dielectric layer of the capacitor layer between the capacitor layers.
【0011】本発明の請求項2に係る積層セラミックコ
ンデンサにおいては、複数個のコンデンサ層と、そのコ
ンデンサ層の誘電体層よりも厚みの厚い中間誘電体層と
を交互に重ね合わせた第1のコンデンサ層と、第1のコ
ンデンサ層の内部電極よりも相対的に小さい対向面積を
有する内部電極と誘電体層とを交互に重ね合わせた第2
のコンデンサ層とを備え、第2のコンデンサ層を第1の
コンデンサ層の外側に重ね合わせ、更に、最外誘電体層
を第2のコンデンサ層の外側に重ね合わせることにより
コンデンサ素子が構成されている。In a multilayer ceramic capacitor according to a second aspect of the present invention, a first capacitor in which a plurality of capacitor layers and an intermediate dielectric layer thicker than the dielectric layer of the capacitor layer are alternately stacked. A second layer in which a capacitor layer, an internal electrode having an opposing area relatively smaller than the internal electrode of the first capacitor layer, and a dielectric layer are alternately overlapped;
A capacitor element is formed by superimposing a second capacitor layer outside the first capacitor layer and further superposing an outermost dielectric layer outside the second capacitor layer. I have.
【0012】本発明の請求項3に係る積層セラミックコ
ンデンサにおいては、中間が分離されて外部電極と電気
的に接続される一対の電極を同一面に設けた誘電体層を
沿面放電制御層とし、その沿面放電制御層を最外誘電体
層とコンデンサ層の間に介在させることによりコンデン
サ素子が構成されている。In the multilayer ceramic capacitor according to a third aspect of the present invention, a dielectric layer having a pair of electrodes separated on the middle and electrically connected to an external electrode provided on the same surface is used as a surface discharge control layer, A capacitor element is formed by interposing the surface discharge control layer between the outermost dielectric layer and the capacitor layer.
【0013】[0013]
【発明の実施の形態】以下、添付図面を参照して説明す
ると、図示の積層セラミックコンデンサは内部電極1a
…と誘電体層1b…とを交互に重ね合わせた複数個のコ
ンデンサ層10…と、外表面層を形成する最外誘電体層
11a,11bとに加え、各コンデンサ層10…を形成
する誘電体層1b…の厚みt1 よりも厚みt2 が厚い
(t1 <t2 )中間誘電体層12…を該コンデンサ層1
0…の間に介在させてコンデンサ素子1を構成し、コン
デンサ層10…の内部電極1a…と電気的に接続する一
対の外部電極2,3をコンデンサ素子1の両端部に設け
た基本形態を有する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the accompanying drawings, the illustrated multilayer ceramic capacitor has an internal electrode 1a.
And the dielectric layers 1b are alternately stacked, and the outermost dielectric layers 11a and 11b forming the outer surface layers, and the dielectric layers forming the respective capacitor layers 10 are formed. body layer 1b ... thick thickness t 2 than the thickness t 1 of the (t 1 <t 2) the intermediate dielectric layer 12 ... the capacitor layer 1
0 and a pair of external electrodes 2 and 3 electrically connected to the internal electrodes 1 a of the capacitor layers 10 are provided at both ends of the capacitor element 1. Have.
【0014】コンデンサ層10…は、チタン酸バリウム
系のセラミック誘電体粉末を主成分とし、それに所要の
有機溶剤とバインダーを添加したスラリーを得、このス
ラリーからドクターブレード法により所定厚みt1 の誘
電体層1b…となるセラミックグリーンシートを得、更
に、Pd電極ペーストからスクリーン印刷法により所定
パターンの内部電極1a…をセラミックグリーンシート
のシート面に印刷し、そのセラミックグリーンシートを
複数枚積層することにより形成されている。この誘電体
層1b…は、図示実施の形態では厚みt1 が25μm程
度に設定されている。[0014] Capacitor layer 10 ... are mainly composed of ceramic dielectric powder of barium titanate, it give a slurry prepared by adding the required organic solvent and a binder, having a predetermined thickness t 1 by a doctor blade method from the slurry dielectric Obtaining ceramic green sheets to be the body layers 1b, and further printing a predetermined pattern of internal electrodes 1a on the sheet surface of the ceramic green sheets by screen printing from a Pd electrode paste, and laminating a plurality of the ceramic green sheets. Is formed. The thickness t 1 of the dielectric layers 1 b is set to about 25 μm in the illustrated embodiment.
【0015】最外誘電体層11a,11bは、コンデン
サ層10…の誘電体層1b…と同じ材料のスラリーを用
いてドクターブレード法により形成できる。その厚みt
3 は通常150〜300μm程度に設定され、図示実施
の形態では150μm程度に設定されている。また、中
間誘電体層12…は最外誘電体層11a,11bと同様
にコンデンサ層10…の誘電体層1b…と同じ材料のス
ラリーを用いてドクターブレード法により形成され、そ
の厚みt2 は50〜300μm程度、図示実施の形態で
は50μm程度に設定されている。The outermost dielectric layers 11a and 11b can be formed by a doctor blade method using a slurry of the same material as the dielectric layers 1b of the capacitor layers 10. Its thickness t
3 is usually set to about 150 to 300 μm, and is set to about 150 μm in the illustrated embodiment. The intermediate dielectric layers 12 are formed by a doctor blade method using a slurry of the same material as the dielectric layers 1b of the capacitor layers 10 like the outermost dielectric layers 11a and 11b, and have a thickness t 2. It is set to about 50 to 300 μm, and in the illustrated embodiment, to about 50 μm.
【0016】これら各層は後述するように複数個のコン
デンサ層と、各コンデンサ層の間に介在させて中間誘電
体層とを交互に重ね合わせ、更に、最外誘電体層をコン
デンサ層の外側に重ね合わせて誘電体積層シートとして
プレス成形した後、所定の部品単位に切断し、脱バイン
ダー工程,焼成工程を経てコンデンサ素子1として構成
されている。また、このコンデンサ素子1にはフリット
含有の銀ーパラジュウム合金を端部面に印刷,焼き付け
処理し、ニッケル,錫メッキを電気メッキ処理で施すこ
とにより外部電極2,3を設けて積層セラミックコンデ
ンサとして構成されている。As will be described later, each of these layers has a plurality of capacitor layers and an intermediate dielectric layer interposed between the respective capacitor layers, which are alternately superposed on each other, and further, the outermost dielectric layer is provided outside the capacitor layer. After being laminated and press-formed as a dielectric laminated sheet, it is cut into a predetermined component unit, and is subjected to a binder removal step and a firing step to form the capacitor element 1. The capacitor element 1 is formed as a multilayer ceramic capacitor by printing and baking a frit-containing silver-palladium alloy on the end face and applying nickel and tin plating by electroplating to provide external electrodes 2 and 3. Have been.
【0017】図1は、内部電極1a…を厚みt1 :25
μmの誘電体層1b…に設けて20層積層することによ
りコンデンサ層を形成し、そのコンデンサ層10,10
a,10bを3個備えた第1の実施の形態を示す。この
積層セラミックコンデンサでは、厚みt2 :50μmの
中間誘電体層12,12aをコンデンサ層10と10
a、10aと10bの各間に重ね合わせ、更に、厚みt
3 :150μmの最外誘電体層11a,11bをコンデ
ンサ層10,10bの外側に重ね合わせることにより構
成されている。FIG. 1 shows that the internal electrodes 1a have a thickness t 1 : 25.
A capacitor layer is formed by laminating 20 dielectric layers 1b of .mu.m and laminating 20 layers.
1 shows a first embodiment having three a and 10b. In this multilayer ceramic capacitor, the intermediate dielectric layers 12, 12a having a thickness t 2 of 50 μm are formed on the capacitor layers 10 and 10a.
a, superimposed between each of 10a and 10b, and furthermore, the thickness t
3 : constituted by superposing outermost dielectric layers 11a and 11b of 150 μm outside capacitor layers 10 and 10b.
【0018】図2は、内部電極1a…を厚みt1 :25
μmの誘電体層1b…に設けて12層積層することによ
りコンデンサ層を形成し、そのコンデンサ層10〜10
dを5個備えた第2の実施の形態を示す。この積層セラ
ミックコンデンサでは、第1の実施の形態と同様に厚み
t2 :50μmの中間誘電体層12〜12cをコンデン
サ層10と10a、10aと10b、10bと10c、
10cと10dの各間に介在させ、厚みt3 :150μ
mの最外誘電体層11a,11bをコンデンサ層10,
10dの外側に重ね合わせることによりコンデンサ素子
1が構成されている。FIG. 2 shows that the internal electrodes 1a have a thickness t 1 : 25.
A capacitor layer is formed by laminating 12 layers on the dielectric layers 1b of.
A second embodiment having five d's is shown. In this multilayer ceramic capacitor, as in the first embodiment, the intermediate dielectric layers 12 to 12c having a thickness t 2 of 50 μm are formed with the capacitor layers 10 and 10a, 10a and 10b, 10b and 10c,
Interposed between each of 10c and 10d, thickness t 3 : 150 μ
m of the outermost dielectric layers 11a and 11b
The capacitor element 1 is formed by superimposing on the outside of 10d.
【0019】図3は第3の実施の形態を示すもので、こ
の積層セラミックコンデンサは第2の実施の形態と同様
に内部電極1a…を厚みt1 :25μmの誘電体層1b
…に設けて12層積層することによりコンデンサ層を形
成し、そのコンデンサ層10〜10dを5個備えると共
に、厚みt2 が50μmの中間誘電体層12〜12cを
コンデンサ層10と10a、10aと10b、10bと
10c、10cと10dの各間に介在させて第1のコン
デンサ層とする。これに加えて、第2のコンデンサ層1
0e,10fが第1中のコンデンサ層10,10dの外
側に重ね合わされている。FIG. 3 shows a third embodiment. In this multilayer ceramic capacitor, as in the second embodiment, the internal electrodes 1a are formed by forming a dielectric layer 1b having a thickness t 1 of 25 μm.
... form a capacitor layer by 12 layers stacked is provided on, the capacitor layer 10~10d with 5 comprising a capacitor layer 10 of the intermediate dielectric layer 12~12c thickness t 2 is 50 [mu] m 10a, and 10a A first capacitor layer is interposed between each of 10b, 10b and 10c, 10c and 10d. In addition to this, the second capacitor layer 1
0e and 10f are superimposed on the outside of the first middle capacitor layers 10 and 10d.
【0020】その第2のコンデンサ層10e,10f
は、第1中のコンデンサ層10〜10dと同様に内部電
極1a’…を厚みt1 :25μmの誘電体層1b’…に
設けて12層積層することにより形成されている。ま
た、このコンデンサ層10e,10fの内部電極1a’
…としては対向面積w1 が第1のコンデンサ層10〜1
0dの内部電極1a…の対向面積w2 よりも相対的に小
さく(w1 <w2 )設けられている。その第2のコンデ
ンサ層10e,10fの外側には、厚みt3 :150μ
mの最外誘電体層11a,11bをコンデンサ層10,
10dの外側に重ね合わせることによりコンデンサ素子
1が構成されている。The second capacitor layers 10e, 10f
The internal electrodes 1a similarly to the capacitor layer 10~10d of the in one '... the thickness t 1: 25 [mu] m of the dielectric layer 1b' is formed by 12 layers stacked is provided on .... Also, the internal electrodes 1a 'of the capacitor layers 10e and 10f are formed.
.., The facing area w 1 is the first capacitor layer 10-1.
Relatively smaller than the internal electrodes 1a ... facing area w 2 of 0d (w 1 <w 2) are provided. Outside the second capacitor layers 10e and 10f, the thickness t 3 : 150 μm
m of the outermost dielectric layers 11a and 11b
The capacitor element 1 is formed by superimposing on the outside of 10d.
【0021】図4は第4の実施の形態を示すもので、図
3で示す実施の形態に加えて、沿面放電制御層13a,
13bを備えることによりコンデンサ素子1が構成され
ている。その沿面放電制御層13a,13bは中間Gが
分離されて外部電極2,3と電気的に接続される一対の
電極1a1 ,1a2 を誘電体層1b”の同一面に設けた
もので、この誘電体層1b”も他の誘電体層と同じ材料
のスラリーを用いてドクターブレード法により厚みt
4 :25μm厚みに形成されている。この沿面放電制御
層13a,13bは、最外誘電体層11a,11bと第
2のコンデンサ層10e,10fの間に介在させてコン
デンサ素子1が構成されている。FIG. 4 shows a fourth embodiment. In addition to the embodiment shown in FIG. 3, a creeping discharge control layer 13a,
13b constitutes the capacitor element 1. The creeping discharge control layers 13a and 13b are provided with a pair of electrodes 1a 1 and 1a 2 that are separated from the middle G and electrically connected to the external electrodes 2 and 3 on the same surface of the dielectric layer 1b ″. This dielectric layer 1b ″ is also made to have a thickness t by a doctor blade method using a slurry of the same material as the other dielectric layers.
4 : formed to a thickness of 25 μm. The creeping discharge control layers 13a and 13b constitute the capacitor element 1 interposed between the outermost dielectric layers 11a and 11b and the second capacitor layers 10e and 10f.
【0022】図5は従来構造の積層セラミックコンデン
サであり、図1,図2の比較例として示す。その積層セ
ラミックコンデンサは内部電極1a…を厚み:25μm
の誘電体層1b…に設けて60層積層することによりコ
ンデンサ層10を形成し、外表面層を形成する厚み:1
50μmの最外誘電体層11a,11bを外側に重ね合
わせてコンデンサ素子1を構成し、コンデンサ層10の
内部電極1a…と電気的に接続する一対の外部電極2,
3をコンデンサ素子1の両端部に設けることにより構成
されている。FIG. 5 shows a multilayer ceramic capacitor having a conventional structure, which is shown as a comparative example of FIGS. In the multilayer ceramic capacitor, the internal electrodes 1a have a thickness of 25 μm.
The capacitor layer 10 is formed by providing the dielectric layers 1b and laminating 60 layers, and the thickness for forming the outer surface layer: 1
The outermost dielectric layers 11a and 11b of 50 μm are superposed on each other to form the capacitor element 1, and a pair of external electrodes 2 electrically connected to the internal electrodes 1a.
3 is provided at both ends of the capacitor element 1.
【0023】上述した実施の形態1〜4並びに従来例に
ついて夫々50個の試料を作成し、実施の形態1,2と
従来例に基づいて中間誘電体層の有無による絶縁破壊電
圧,電歪破壊発生電圧を測定した。この測定は電圧を1
00V/秒の昇圧速度により絶縁油中で印加し、漏れ電
流が10mAとなったところを破壊発生電圧と判断する
ことにより行った。その平均値は表1で示す通りであ
り、厚み50μm程度の中間誘電体層を備えると、最外
誘電体層の厚みを150μm程度に抑えても、中間誘電
体層を備えないものよりも、絶縁破壊電圧,電歪破壊発
生電圧をいずれも高められる。特に、実施の形態2のよ
うに4層程度多層を備えると、電歪破壊発生電圧を1.
5倍も向上できることが判る。Fifty samples were prepared for each of the above-described first to fourth embodiments and the conventional example. The generated voltage was measured. This measurement measures 1
The voltage was applied in the insulating oil at a boosting rate of 00 V / sec, and the point where the leakage current reached 10 mA was determined as the breakdown occurrence voltage. The average value is as shown in Table 1, and when an intermediate dielectric layer having a thickness of about 50 μm is provided, even if the thickness of the outermost dielectric layer is suppressed to about 150 μm, compared to a case where no intermediate dielectric layer is provided, Both the dielectric breakdown voltage and the electrostriction breakdown generation voltage can be increased. In particular, when about four layers are provided as in the second embodiment, the electrostriction breakdown generation voltage is 1.
It turns out that it can improve 5 times.
【0024】[0024]
【表1】 [Table 1]
【0025】また、実施の形態2と実施の形態3に基づ
いて第2のコンデンサ層の有無による絶縁破壊電圧,電
歪破壊発生電圧を測定した。この測定も電圧を100V
/秒の昇圧速度により絶縁油中で印加し、漏れ電流が1
0mAとなったところを破壊発生電圧と判断することに
より行った。その平均値は表2で示す通りであり、容量
の相対的に小さい第2のコンデンサ層を外層側に備える
と、絶縁破壊電圧,電歪破壊発生電圧を共に更に高める
ことができ、特に、電歪破壊発生電圧は0.5KVも向
上できることが判る。In addition, based on the second and third embodiments, the dielectric breakdown voltage and the electrostriction breakdown occurrence voltage were measured with and without the second capacitor layer. This measurement also uses a voltage of 100V
Applied in an insulating oil at a pressure increase rate of 1 / sec.
The test was performed by determining the point where the current became 0 mA as the breakdown occurrence voltage. The average value is as shown in Table 2. When the second capacitor layer having a relatively small capacity is provided on the outer layer side, both the dielectric breakdown voltage and the electrostriction breakdown generation voltage can be further increased. It can be seen that the strain breakdown generation voltage can be improved by 0.5 KV.
【0026】[0026]
【表2】 [Table 2]
【0027】更に、実施の形態3と実施の形態4に基づ
いて沿面放電制御層の有無による沿面放電発生電圧を測
定した。この測定は電圧を100V/秒の昇圧速度によ
り空気中で印加し、漏れ電流が1mAとなったところを
沿面放電発生電圧と判断することにより行った。その平
均値は表3で示す通りであり、沿面放電制御層の中間が
分離された一対の電極と外部電極との極性が等しくな
り、電気力線が外部電極と各電極との間に集中しないこ
とにより沿面放電の発生を抑えられるもので、この沿面
放電制御層を備えないものよりも、沿面放電発生電圧を
2倍以上も向上できることが判る。Further, based on the third and fourth embodiments, the creeping discharge generation voltage was measured depending on the presence or absence of the creeping discharge control layer. This measurement was performed by applying a voltage in the air at a boosting rate of 100 V / sec, and judging that the leakage current was 1 mA as the creeping discharge generation voltage. The average value is as shown in Table 3. The polarities of the pair of electrodes where the middle of the creeping discharge control layer is separated and the external electrode are equal, and the lines of electric force do not concentrate between the external electrode and each electrode. As a result, it is found that the generation of the creeping discharge can be suppressed, and the creeping discharge generation voltage can be more than doubled as compared with the case without the creeping discharge control layer.
【0028】[0028]
【表3】 [Table 3]
【0029】[0029]
【発明の効果】以上の如く、本発明の請求項1に係る積
層セラミックコンデンサに依れば、中間誘電体層を備え
てコンデンサ素子を構成することから、最外誘電体層の
厚みを薄く抑えても、中間誘電体層を備えないものより
も、絶縁破壊電圧,電歪破壊発生電圧をいずれも高めら
れ、特に、電歪破壊発生電圧を著しく向上することがで
きる。As described above, according to the multilayer ceramic capacitor of the first aspect of the present invention, since the capacitor element is provided with the intermediate dielectric layer, the thickness of the outermost dielectric layer is reduced. However, both the dielectric breakdown voltage and the electrostriction breakdown occurrence voltage can be increased as compared with those having no intermediate dielectric layer, and in particular, the electrostriction breakdown occurrence voltage can be significantly improved.
【0030】本発明の請求項2に係る積層セラミックコ
ンデンサに依れば、コンデンサ層と中間誘電体層と交互
に重ね合わせた第1のコンデンサ層と共に、容量の相対
的に小さい第2のコンデンサ層を外層側に備えてコンデ
ンサ素子を構成することにより、絶縁破壊電圧,電歪破
壊発生電圧を共に更に高められ、特に、電歪破壊発生電
圧を向上するようにできる。According to the multilayer ceramic capacitor of the present invention, the second capacitor layer having a relatively small capacitance is provided together with the first capacitor layer alternately stacked with the capacitor layer and the intermediate dielectric layer. Is provided on the outer layer side to constitute the capacitor element, thereby further increasing both the dielectric breakdown voltage and the electrostriction breakdown occurrence voltage, and in particular, the electrostriction breakdown occurrence voltage can be improved.
【0031】本発明の請求項3に係る積層セラミックコ
ンデンサに依れば、中間誘電体層と交互に重ね合わせた
コンデンサ層と共に、沿面放電制御層を備えてコンデン
サ素子を構成することから、絶縁破壊電圧,電歪破壊発
生電圧を高められるばかりでなく、電気力線が沿面放電
制御層の中間が分離された一対の電極と外部電極との間
に集中しないことにより、沿面放電制御層を備えないも
のよりも、沿面放電発生電圧を極めて向上することがで
きる。According to the multilayer ceramic capacitor according to the third aspect of the present invention, since the capacitor element is provided with the creeping discharge control layer together with the capacitor layer alternately superimposed on the intermediate dielectric layer, the dielectric breakdown occurs. Not only can the voltage and electrostriction breakdown occurrence voltage be increased, but the electric field lines do not concentrate between the pair of electrodes separated from the middle of the creeping discharge control layer and the external electrode, so that the creeping discharge control layer is not provided. The creeping discharge generation voltage can be significantly improved as compared with the case.
【図1】本発明の第1実施の形態に係る2層の中間誘電
体層を備えた積層セラミックコンデンサを示す説明図で
ある。FIG. 1 is an explanatory diagram showing a multilayer ceramic capacitor including two intermediate dielectric layers according to a first embodiment of the present invention.
【図2】本発明の第2実施の形態に係る4層の中間誘電
体層を備えた積層セラミックコンデンサを示す説明図で
ある。FIG. 2 is an explanatory diagram illustrating a multilayer ceramic capacitor including four intermediate dielectric layers according to a second embodiment of the present invention.
【図3】本発明の第3実施の形態に係る第1のコンデン
サ層と第2のコンデンサ層を備えた積層セラミックコン
デンサを示す説明図である。FIG. 3 is an explanatory diagram showing a multilayer ceramic capacitor including a first capacitor layer and a second capacitor layer according to a third embodiment of the present invention.
【図4】本発明の第4実施の形態に係る沿面放電制御層
を備えた積層セラミックコンデンサを示す説明図であ
る。FIG. 4 is an explanatory view showing a multilayer ceramic capacitor including a creeping discharge control layer according to a fourth embodiment of the present invention.
【図5】従来例に係る積層セラミックコンデンサを内部
電極の電極パターンで示す説明図である。FIG. 5 is an explanatory view showing a multilayer ceramic capacitor according to a conventional example by electrode patterns of internal electrodes.
1 コンデンサ素子 1a… 内部電極 1b… 誘電体層 10,10a,10b コンデンサ層 11a,11b 最外誘電体層 12,12a,12c 中間誘電体層 2,3 外部電極 DESCRIPTION OF SYMBOLS 1 Capacitor element 1a ... Internal electrode 1b ... Dielectric layer 10, 10a, 10b Capacitor layer 11a, 11b Outer dielectric layer 12, 12a, 12c Intermediate dielectric layer 2, 3 External electrode
Claims (3)
せたコンデンサ層をコンデンサ素子の内部に備え、その
コンデンサ層の内部電極と電気的に接続する一対の外部
電極をコンデンサ素子の両端部に設けてなる積層セラミ
ックコンデンサにおいて、 複数個のコンデンサ層と、外表面層を形成する最外誘電
体層とに加え、コンデンサ層の誘電体層よりも厚みの厚
い中間誘電体層を該コンデンサ層の間に介在させてコン
デンサ素子を構成したことを特徴とする積層セラミック
コンデンサ。A capacitor layer in which an internal electrode and a dielectric layer are alternately superposed on each other, and a pair of external electrodes electrically connected to the internal electrode of the capacitor layer are provided at both ends of the capacitor element. A multilayer ceramic capacitor comprising: a plurality of capacitor layers; an outermost dielectric layer forming an outer surface layer; and an intermediate dielectric layer thicker than the dielectric layer of the capacitor layer. A multilayer ceramic capacitor characterized by comprising a capacitor element interposed therebetween.
サ層の誘電体層よりも厚みの厚い中間誘電体層とを交互
に重ね合わせた第1のコンデンサ層と、第1のコンデン
サ層の内部電極よりも相対的に小さい対向面積を有する
内部電極と誘電体層とを交互に重ね合わせた第2のコン
デンサ層とを備え、第2のコンデンサ層を第1のコンデ
ンサ層の外側に重ね合わせ、更に、最外誘電体層を第2
のコンデンサ層の外側に重ね合わせてコンデンサ素子を
構成したことを特徴とする請求項1に記載の積層セラミ
ックコンデンサ。2. A first capacitor layer in which a plurality of capacitor layers and an intermediate dielectric layer thicker than the dielectric layer of the capacitor layer are alternately stacked, and an internal electrode of the first capacitor layer. A second capacitor layer in which an internal electrode having a relatively smaller opposing area and a dielectric layer are alternately superimposed, the second capacitor layer being superimposed on the outside of the first capacitor layer, And the outermost dielectric layer as the second
The multilayer ceramic capacitor according to claim 1, wherein a capacitor element is formed by superimposing the capacitor element on the outside of the capacitor layer.
続される一対の電極を同一面に設けた誘電体層を沿面放
電制御層とし、その沿面放電制御層を最外誘電体層とコ
ンデンサ層の間に介在させてコンデンサ素子を構成した
ことを特徴とする請求項1または2に記載の積層セラミ
ックコンデンサ。3. A creeping discharge control layer comprising a dielectric layer having a pair of electrodes separated on the middle and electrically connected to an external electrode provided on the same surface, and the creeping discharge control layer is defined as an outermost dielectric layer. 3. The multilayer ceramic capacitor according to claim 1, wherein the capacitor element is formed by being interposed between the capacitor layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9335006A JPH11150037A (en) | 1997-11-19 | 1997-11-19 | Laminated ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9335006A JPH11150037A (en) | 1997-11-19 | 1997-11-19 | Laminated ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11150037A true JPH11150037A (en) | 1999-06-02 |
Family
ID=18283693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9335006A Pending JPH11150037A (en) | 1997-11-19 | 1997-11-19 | Laminated ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11150037A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112007000130T5 (en) | 2006-01-13 | 2008-12-18 | Murata Mfg. Co., Ltd., Nagaokakyo-shi | Multilayer capacitor |
| JP2015073115A (en) * | 2009-07-01 | 2015-04-16 | ケメット エレクトロニクス コーポレーション | High capacitance multilayer with high voltage capability |
| JP2015226026A (en) * | 2014-05-29 | 2015-12-14 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
| JP2018110250A (en) * | 2018-02-15 | 2018-07-12 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
| JP2018110251A (en) * | 2018-02-15 | 2018-07-12 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
-
1997
- 1997-11-19 JP JP9335006A patent/JPH11150037A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112007000130T5 (en) | 2006-01-13 | 2008-12-18 | Murata Mfg. Co., Ltd., Nagaokakyo-shi | Multilayer capacitor |
| US7715172B2 (en) | 2006-01-13 | 2010-05-11 | Murata Manufacturing Co., Ltd. | Multilayer capacitor |
| JP2015073115A (en) * | 2009-07-01 | 2015-04-16 | ケメット エレクトロニクス コーポレーション | High capacitance multilayer with high voltage capability |
| JP2015226026A (en) * | 2014-05-29 | 2015-12-14 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
| JP2018110250A (en) * | 2018-02-15 | 2018-07-12 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
| JP2018110251A (en) * | 2018-02-15 | 2018-07-12 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
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