JPH1115691A - Processor and debug equipment - Google Patents

Abstract

(57) [Problem] To provide a processor capable of tracing an operation such as tracing of an execution address of a program even during a cache hit, and to provide a processor without stopping the operation of a cache memory. An object of the present invention is to provide a debugging device that enables debugging. SOLUTION: An access address of a cache is always output by buffers 10 and 13 irrespective of a hit / miss of a cache 7 or 8. When the caches 7 and 8 hit, the buffers 11 and 14 output the data read from the caches. As a result, the debug device 20 can always track the operation of the central processing unit 2 of the processor 1 irrespective of the hit / miss of the caches 7 and 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a processor having a cache memory, and a debugging device for debugging a program applied to the processor.

[0002]

2. Description of the Related Art With the recent development of electronic technology, microprocessors and other information processing apparatuses have become widespread and used in various fields. Particularly, the operation speed of the processor has been remarkably improved. However, although the degree of integration of DRAMs and other semiconductor memories has increased remarkably, there is a situation where the performance of the processor is not sufficiently exhibited because the speed does not follow. In order to overcome this, it is well known that a high-speed cache memory having a small capacity is mounted on a processor.

A conventional processor equipped with a cache memory outputs an address to the outside and outputs a desired program or operand data when the cache memory does not have a copy of a program or operand data, that is, in the case of a cache mishit. Access is made, but once a copy is stored in the cache memory, that is, in the case of a cache hit, the processor does not output information such as the address accessing the cache memory, and performs an operation closed by the processor.

Therefore, the conventional debugging device corresponding to the above processor stops the operation of the cache memory so as not to have a copy of the program or the operand data in the cache memory and debugs the program.

[0005]

However, in the above-described processor, information such as the address accessing the cache memory is not output. Therefore, during a cache hit, tracing of a program address, verification of an instruction, or operand However, there is a problem that the operation of the processor such as monitoring of addresses and data cannot be tracked.

Further, in the above-mentioned debugging apparatus, since the operation of the cache memory is stopped to debug the program, there is a problem that debugging cannot be performed in the same processor execution state as when the cache memory is actually operated. There is a problem that it is impossible to measure the execution time when the cache memory is operated and to evaluate the cache memory such as the cache hit rate.

In view of the foregoing, the present invention provides a processor capable of tracing an operation such as tracing the execution address of a program even during a cache hit, and
It is an object of the present invention to provide a debugging device that enables a program to be debugged without stopping the operation of the cache memory.

[0008]

A processor according to the present invention for solving this problem comprises a central processing unit for processing operands according to a program, a cache memory for storing the program or the operand, and a cache memory for storing the program or the operand. When a stored program or operand is read, a bus control device is provided for outputting at least one of an address to be read and read contents to the outside.

A processor according to the present invention has an internal program bus for transferring a program, an internal operand bus for transferring an operand, a central processing unit for processing the operand in accordance with the program, and An instruction cache memory that is connected to store the program, a data cache memory that is connected to the internal operand bus, and stores the operand, and an internal program that is used when the program stored in the instruction cache memory is read. A bus control device for outputting the content on the bus to the outside and outputting the content on the internal operand bus to the outside when the operand stored in the data cache memory is read.

A processor according to the present invention has an internal program bus for transferring a program, an internal operand bus for transferring an operand, and a central processing unit for processing the operand in accordance with the program. An instruction cache memory connected to store the program, temporary storage means for temporarily storing contents on the internal program bus when a program stored in the instruction cache memory is read, and an internal operand bus When the operand is transferred to the internal operand bus, only the content on the internal operand bus is output to the outside, and when the operand is not transferred to the internal operand bus, the content stored in the temporary storage means is output to the outside. And a bus control device for outputting.

A processor according to the present invention has an internal program bus for transferring a program, an internal operand bus for transferring an operand, and a central processing unit for processing the operand in accordance with the program. A data cache memory connected to store the operand, temporary storage means for temporarily storing contents on the internal operand bus when a program stored in the data cache memory is read, and the internal program bus When the program is transferred to the internal program bus, only the content on the internal program bus is output to the outside, and when the program is not transferred to the internal program bus, the content stored in the temporary storage unit is output to the outside. And a bus control device for outputting.

Further, according to the present invention, there is provided a debugging apparatus, comprising: a central processing unit for processing an operand in accordance with a program; a cache memory for storing the program or the operand; When a program or operand is read, at least one of an address to be read and read content is output to a bus, and when a program or operand that is not stored in the cache memory is read, an address to be read A bus control device that outputs a signal to the bus, an emulation memory connected to the bus and supplying a program or operand to the processor, and a processor connected to the bus and based on contents on the bus. Before And a monitor device that tracks the operation of the central processing unit.

A processor according to the present invention has an internal program bus for transferring a program, an internal operand bus for transferring an operand, a central processing unit for processing the operand in accordance with the program, and a processor connected to the internal program bus. A processor having an instruction cache memory connected to store the program and a bus control device connected to the internal program bus and the internal operand bus, wherein the central processing unit is stored in the cache memory. A processor that cancels, delays, or suspends the reading of the program when the reading of a program that has not been performed and the reading or writing of an operand occur simultaneously.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a configuration of a processor and a debugging device according to the first embodiment of the present invention.

In FIG. 1, a processor 1 comprises a central processing unit 2, a data cache 7, an instruction cache 8, and a bus control unit 9, and outputs an operand address bus 16, an input / output operand data bus 17, and an output. A program address bus 18 and an input / output program data bus 19 are provided as interfaces with the outside world.

The central processing unit 2 includes an output internal operand address bus 3 and an input / output internal operand data bus 4.
And an internal program address bus 5 for output and an internal program data bus 6 for input as interfaces.
The operands are processed according to the program input via the internal program address bus 5 and the internal program data bus 6. The operand before the processing or the operand after the processing is input / output via the internal operand address bus 3 and the internal operand data bus 4.

The data cache 7 is connected to the internal operand address bus 3 and the internal operand data bus 4, and stores operands.

The instruction cache 8 is connected to the internal program address bus 5 and the internal program data bus 6, and stores a program.

The bus controller 9 includes a buffer 10 for outputting the contents of the internal operand address bus 3 to the operand address bus 16 and a buffer 11 for outputting the contents of the internal operand data bus 4 to the operand data bus 17.
Buffer 12 for outputting the contents of operand data bus 17 to internal operand data bus 4, and the contents of internal program address bus 5 to program address bus 18
A buffer 13 for outputting the contents of the internal program data bus 6 to the program data bus 19, a buffer 15 for outputting the contents of the program data bus 19 to the internal program data bus 6, and a bus control circuit (not shown). And Buffer 10 and Buffer 1
3 always operates, but the buffer 11 operates at the time of a write or read hit of the data cache 7, the buffer 12 operates at the time of a read miss hit of the data cache 7, the buffer 14 operates at the time of a hit of the instruction cache 8, Numerals 15 are controlled by the bus control circuit so as to operate when the instruction cache 8 has a miss hit. It is assumed that writing to the instruction cache 8 does not occur.

In FIG. 1, the debugging device 20 comprises:
Processor 1, data emulation memory 21, program emulation memory 22, and monitor device 23
It is composed of

The data emulation memory 21 includes an operand address bus 16 and an operand data bus 17
When the data cache 7 is written, write data is input from the operand data bus 17 for writing, and when the data cache 7 has a read miss, the read data is output to the operand data bus 17. No operation is performed during a read hit of the data cache 7.

Program emulation memory 22
Are connected to a program address bus 18 and a program data bus 19, and output data to the program data bus 19 when the instruction cache 8 misses. No operation is performed when the instruction cache 8 hits. The program emulation memory 22 stores a program to be debugged as data by a method (not shown) such as transfer from a host computer.

The monitor device 23 inputs the operand address bus 16, the operand data bus 17, the program address bus 18 and the program data bus 19, and tracks the operation of the central processing unit 2. The tracing of the operations includes tracing the operand addresses, measuring the operand address breakpoints, measuring the operand coverage, measuring the hit ratio of the data cache 7 based on the addresses on the operand address bus 16, and measuring the data on the operand data bus 17. Verification of breakpoint processing based on the contents of operands, tracing of program addresses based on addresses on the program address bus 18, program address breakpoint processing, measurement of program coverage, measurement of the hit rate of the instruction cache 8, Verification such as breakpoint processing based on the contents of an instruction based on data on the data bus 19 is included.

The operation of the thus configured processor and debug device according to the first embodiment of the present invention will be described.

Since the operation of the program and the operand can be grasped completely independently, the description will be made separately for each of the cache hit and the mishit.

(1) Central processing unit 2 for programs
Understanding the operation of i. In the case of a hit in the instruction cache 8, in the processor 1, the central processing unit 2 outputs an address to the program address bus 18 via the internal program address bus 5 and the buffer 13, and the instruction cache 8 , The program is read out based on the address, input to the central processing unit 2 via the internal program data bus 6, and output to the program data bus 19 via the buffer 14.

In the debug device 20, the monitor device 23 inputs the program address output from the central processing unit 2 from the program address bus 18 and the program output from the instruction cache 8 from the program data bus 19.

In this case, although data is present in the instruction cache 8, an address is output to the program emulation memory 22 via the program address bus 18 and data collision becomes a problem. Data collision is avoided by deactivating signals such as an address strobe signal and a chip select signal.

This is the same when the data cache 7 hits. B. In the case of a miss hit in the instruction cache 8, in the processor 1, the central processing unit 2 outputs an address to the program address bus 18 via the internal program address bus 5 and the buffer 13, and
The program is input to the central processing unit 2 from the program data bus 19 via the internal data bus 5 and the internal program data bus 6.

In the debug device 20, the program emulation memory 22 reads a program based on the address on the program address bus 18 and outputs the program to the program data bus 19, and the monitor device 23 transmits the program from the program address bus 18 to the central processing unit. 2 and the program output from the program emulation memory 22 from the program data bus 19 are input.

(2) Central processing unit 2 for operands
Understanding the operation of c. In the case of a read hit of the data cache 7, in the processor 1, the central processing unit 2 outputs an address to the operand address bus 16 via the internal operand address bus 3 and the buffer 10, and the data cache 7 outputs the address to the internal operand address bus 3. Operands are read based on the above address, input to the central processing unit 2 via the internal operand data bus 4, and output to the operand data bus 17 via the buffer 11.

In the debug device 20, the monitor device 23 inputs the operand address output from the central processing unit 2 from the operand address bus 16 and the operand output from the data cache 7 from the operand data bus 17.

D. In the case of a read mishit in the data cache 7, in the processor 1, the central processing unit 2 outputs an address to the operand address bus 16 via the internal operand address bus 3 and the buffer 10, and the buffer 1
The operand is input from the operand data bus 17 to the central processing unit 2 via the internal operand data bus 4 and the internal operand data bus 4.

In the debug device 20, the data emulation memory 21 is connected to the operand address bus 16
Based on the above address, the operand is read and output to the operand data bus 17, and the monitor device 23 outputs the operand address output by the central processing unit 2 from the operand address bus 16 and the data emulation memory 21 from the operand data bus 17. Input the operand to be output.

E. In the case of writing data in the data cache 7, in the processor 1, the central processing unit 2 outputs an address to the operand address bus 16 via the internal operand address bus 3 and the buffer 10, and the central processing unit 2 outputs the operand to the internal operand bus. Data bus 4
The data cache 7 writes the operand on the internal operand data bus 4 based on the address on the internal operand address bus 3.

In the debug device 20, the monitor device 23 inputs the operand address output from the central processing unit 2 from the operand address bus 16 and the operand output from the central processing unit 2 from the operand data bus 17.

As described above, according to the first embodiment of the present invention, even when the data cache 7 or the instruction cache 8 is hit, the processor 1 outputs the address and data of the program and the operand to the outside. . Therefore, the debugging device 20 enables debugging of the program without stopping the operation of the cache memory.

FIG. 2 is a block diagram showing a configuration of a processor and a debugging device according to the second embodiment of the present invention. 2, the same components as those in FIG. 1 are denoted by the same reference numerals.

Referring to FIG. 2, a processor 41 comprises a central processing unit 2, a data cache 7, an instruction cache 8, and a bus control unit 42.
3 and an input / output data bus 54 as an interface with the outside world.

The bus controller 42 has an address FIFO memory 43 for storing the contents of the internal program address bus 5.
And a data FIFO memory 44 for storing the contents of the internal program data bus 6, and a buffer 45 for outputting the contents of the internal operand address bus 3 to the address bus 53.
And a buffer 46 for outputting the contents of the internal program address bus 5 to the address bus 53 and a buffer 47 for outputting the output of the address FIFO memory 43 to the address bus 53.
And the contents of internal operand data bus 4 to data bus 5
And a buffer 49 for outputting the contents of the data bus 54 to the internal operand data bus 4.
And the contents of the internal program data bus 6 to the data bus 5
And a buffer 51 for outputting the contents of the data bus 54 to the internal program data bus 6.
And a buffer 52 for outputting the output of the data FIFO memory 44 to the data bus 54, and a bus control circuit (not shown). Buffers 45 to 47 operate exclusively with each other, and buffers 48, 50 and 52 operate exclusively with each other.
The conditions for the operation will be described in the following description of the operation. In addition,
Write to the instruction cache 8 does not occur.

In FIG. 2, the debugging device 55
Processor 41, data emulation memory 56, program emulation memory 57, and monitor device 5
And 8.

The data emulation memory 56 is connected to the address bus 53 and the data bus 54. The data emulation memory 56 receives write data from the data bus 54 when writing data in the data cache 7, and writes data when the read cache hits the data cache 7. The read data is output to 54. No operation is performed during a read hit of the data cache 7.

Program emulation memory 57
Are connected to an address bus 53 and a data bus 54,
When a miss occurs in the instruction cache 8, data is output to the data bus 54. No operation is performed when the instruction cache 8 hits. The program emulation memory 5
7 stores a program to be debugged as data by a method (not shown) such as transfer from a host computer.

The monitor device 58 inputs the address bus 53 and the data bus 54, and tracks the operation of the central processing unit 2. The tracing of the operations includes tracing of an operand address, operand address breakpoint processing, measurement of operand coverage, measurement of a hit ratio of the data cache 7, program address tracing, and program address breakpoint processing based on an address on the address bus 53. , Measurement of program coverage, measurement of the hit rate of the instruction cache 8, verification of breakpoint processing by the contents of operands based on data on the data bus 54, and verification of breakpoint processing by the contents of instructions.

The operation of the processor and the debug device according to the second embodiment of the present invention configured as described above will be described.

The operation cannot be grasped independently of the program and the operand. Here, the instruction cache 8
And the data cache 7 will be described separately.

B. In the case where the instruction cache 8 is hit and the data cache 7 is a read hit In the processor 41, the central processing unit 2 outputs an address to the internal program address bus 5, and the instruction cache 8 outputs the address based on the address on the internal program address bus 5. And the program is input to the central processing unit 2 via the internal program data bus 6. At the same time, the address on the internal program address bus 5 and the data on the internal program data bus 6 are stored in the address FIFO memory 43 and the data FIFO memory 44, respectively. Also,
The central processing unit 2 outputs the address to the address bus 53 via the internal operand address bus 3 and the buffer 45, and the data cache 7 reads the operand based on the address on the internal operand address bus 3 to read the internal operand data. The data is input to the central processing unit 2 via the bus 4 and output to the data bus 54 via the buffer 48.

In the debug device 55, the monitor device 58 inputs an operand address output from the central processing unit 2 from the address bus 53 and an operand output from the data cache 7 from the data bus 54. Therefore, in this case, the operation of the central processing unit 2 can be grasped only with respect to the operand.

B. In the case where the instruction cache 8 is hit and the data cache 7 is a read miss hit In the processor 41, the central processing unit 2 outputs an address to the internal program address bus 5, and the instruction cache 8 outputs the address based on the address on the internal program address bus 5. And the program is input to the central processing unit 2 via the internal program data bus 6. At the same time, the address on the internal program address bus 5 and the data on the internal program data bus 6 are stored in the address FIFO memory 43 and the data FIFO memory 44, respectively. Also,
The central processing unit 2 outputs the address to the address bus 53 via the internal operand address bus 3 and the buffer 45, and outputs the operand from the data bus 54 via the buffer 49 and the internal operand data bus 4. To enter.

In the debug device 55, the data emulation memory 56 reads an operand based on the address on the address bus 53 and outputs it to the data bus 54, and the monitor device 58 outputs the data from the address bus 53 to the central processing unit 2. Operand address and data bus 5
4 and the operand output from the data emulation memory 56. Therefore, in this case, the operation of the central processing unit 2 can be grasped only with respect to the operand.

C. When the instruction cache 8 is hit and the data cache 7 is write In the processor 41, the central processing unit 2 outputs an address to the internal program address bus 5, and the instruction cache 8 outputs the address based on the address on the internal program address bus 5. The program is read and input to the central processing unit 2 via the internal program data bus 6. At the same time, the address on the internal program address bus 5 and the data on the internal program data bus 6 are stored in the address FIFO memory 43 and the data FIFO memory 44, respectively. Also,
The central processing unit 2 outputs the address to the address bus 53 via the internal operand address bus 3 and the buffer 45, and the central processing unit 2 similarly outputs the operand via the internal operand data bus 4 and the buffer 48 to the data bus 54. The data cache 7 writes the operand on the internal operand data bus 4 based on the address on the internal operand address bus 3.

In the debug device 55, the monitor device 58 inputs the operand address output from the central processing unit 2 from the address bus 53 and the operand output from the central processing unit 2 from the data bus 54. Therefore, in this case, the operation of the central processing unit 2 can be grasped only with respect to the operand.

D. When the instruction cache 8 is hit and the data cache 7 is not accessed In the processor 41, the central processing unit 2 outputs an address to the internal program address bus 5, and the instruction cache 8 outputs the address based on the address on the internal program address bus 5. And the program is input to the central processing unit 2 via the internal program data bus 6. At this time, if the address FIFO memory 43 and the data FIFO memory 44 are empty, the address on the internal program address bus 5 and the data on the internal program data bus 6 are transferred to the address bus 53 via the buffer 46 and the buffer 50, respectively. And the data bus 54. Address FIFO
When the memory 43 and the data FIFO memory 44 are not empty, the address on the internal program address bus 5 and the data on the internal program data bus 6 are newly stored in the address FIFO memory 43 and the data FIFO memory 44, respectively. The oldest address stored in the memory 43 and the oldest data stored in the data FIFO memory 44 are output to an address bus 53 and a data bus 54 via a buffer 46 and a buffer 50, respectively.

In the debug device 55, the monitor device 58 controls the program address output from the central processing unit 2 or the address FIFO memory 43 via the address bus 53 and the instruction cache 8 or data from the data bus 54 via the data bus 54.
The program output from the FIFO memory 44 is input. Therefore, in this case, the operation of the central processing unit 2 can be grasped only for the program.

E. When the instruction cache 8 is a mishit and the data cache 7 is a read hit In the processor 41, the central processing unit 2 outputs an address to the internal program address bus 5 to read a program. Nothing happens (program reading of the same address is repeated). The central processing unit 2 outputs the address to the address bus 53 via the internal operand address bus 3 and the buffer 45, and the data cache 7 reads the operand based on the address on the internal operand address bus 3 and The data is input to the central processing unit 2 via the operand data bus 4 and output to the data bus 54 via the buffer 48.

In the debug device 55, the monitor device 58 inputs an operand address output from the central processing unit 2 via the address bus 53 and an operand output from the data cache 7 via the data bus 54. Therefore, in this case, the operation of the central processing unit 2 can be grasped only with respect to the operand.

F. In the case where the instruction cache 8 is a mishit and the data cache 7 is a read mishit In the processor 41, the central processing unit 2 outputs an address to the internal program address bus 5 to read a program. Nothing happens (program reading of the same address is repeated). The central processing unit 2 outputs the address to the address bus 53 via the internal operand address bus 3 and the buffer 45, and centrally processes the operand from the data bus 54 via the buffer 49 and the internal operand data bus 4. Input to the device 2.

In the debug device 55, the data emulation memory 56 reads an operand based on the address on the address bus 53 and outputs it to the data bus 54, and the monitor device 58 outputs the operand from the address bus 53 to the central processing unit 2. Operand address and data bus 5
4 and the operand output from the data emulation memory 56. Therefore, in this case, the operation of the central processing unit 2 can be grasped only with respect to the operand.

G. When the instruction cache 8 is a mishit and the data cache 7 is a write In the processor 41, the central processing unit 2 outputs an address to the internal program address bus 5 to read a program. Does not occur (program reading of the same address is repeated). Further, the central processing unit 2 outputs the address to the address bus 53 via the internal operand address bus 3 and the buffer 45, and the central processing unit 2 similarly outputs the operand to the internal operand data bus 4 and the buffer 4
8 and output to the data bus 54, and the data cache 7 writes the operand on the internal operand data bus 4 based on the address on the internal operand address bus 3.

In the debug device 55, the monitor device 58 inputs an operand address output from the central processing unit 2 from the address bus 53 and an operand output from the central processing unit 2 from the data bus 54. Therefore, in this case, the operation of the central processing unit 2 can be grasped only with respect to the operand.

H. When the instruction cache 8 is mishit and the data cache 7 is not accessed. When the address FIFO memory 43 and the data FIFO memory 44 are empty.

In the processor 41, the central processing unit 2 outputs an address to the address bus 53 via the internal program address bus 5 and the buffer 46, and outputs the data bus via the buffer 51 and the internal program data bus 6. From 54, the program is input to the central processing unit 2.

In the debugging device 55, the program emulation memory 57 reads out the program based on the address on the address bus 53 and outputs it to the data bus 54, and the monitor device 58 outputs the data from the address bus 53 to the central processing unit 2. A program address to be output and a program output from the program emulation memory 57 from the data bus 54 are input.

Address FIFO memory 43 and data FIFO
When the memory 44 is not empty. In the processor 41, the central processing unit 2 outputs an address to the internal program address bus 5 to read the program, but nothing more occurs in the program reading (the program reading of the same address is repeated). The oldest address stored in the address FIFO memory 43 and the oldest data stored in the data FIFO memory 44 are output to an address bus 53 and a data bus 54 via a buffer 46 and a buffer 50, respectively.

In the debug device 55, the monitor device 58 is connected to the address FIFO memory 43 via the address bus 53.
And the program output from the data FIFO memory 44 from the data bus 54 are input.

Therefore, in each case, the operation of the central processing unit 2 can be grasped only with respect to the program.

Re. In the case where the instruction cache 8 has no access and the data cache 7 has a read hit, in the processor 41, the central processing unit 2 outputs an address to the address bus 53 via the internal operand address bus 3 and the buffer 45, and the data cache 7
Reads an operand based on the address on internal operand address bus 3 and inputs it to central processing unit 2 via internal operand data bus 4 while buffer 48
To the data bus 54 via

In the debug device 55, the monitor device 58 inputs the operand address output from the central processing unit 2 via the address bus 53 and the operand output from the data cache 7 via the data bus 54. Therefore, in this case, the operation of the central processing unit 2 can be grasped only with respect to the operand.

Nu. In the case where the instruction cache 8 has not been accessed and the data cache 7 has a read mishit, in the processor 41, the central processing unit 2 outputs the address to the address bus 53 via the internal operand address bus 3 and the buffer 45, and Operands are input from the data bus 54 to the central processing unit 2 via the internal operand data bus 4.

In the debug device 55, the data emulation memory 56 reads an operand based on the address on the address bus 53 and outputs it to the data bus 54, and the monitor device 58 outputs the data from the address bus 53 to the central processing unit 2. Operand address and data bus 5
4 and the operand output from the data emulation memory 56. Therefore, in this case, the operation of the central processing unit 2 can be grasped only with respect to the operand.

R. In the case where the instruction cache 8 is not accessed and the data cache 7 is write In the processor 41, the central processing unit 2 outputs an address to the address bus 53 via the internal operand address bus 3 and the buffer 45, and the central processing unit 2 outputs the operand to the data bus 54 via the internal operand data bus 4 and the buffer 48, and the data cache 7 writes the operand on the internal operand data bus 4 based on the address on the internal operand address bus 3. Put in.

In the debug device 55, the monitor device 58 inputs the operand address output from the central processing unit 2 from the address bus 53 and the operand output from the central processing unit 2 from the data bus 54. Therefore, in this case, the operation of the central processing unit 2 can be grasped only with respect to the operand.

ヲ. When the instruction cache 8 is not accessed and the data cache 7 is not accessed When the address FIFO memory 43 and the data FIFO memory 44 are empty.

There is no change in both the processor 41 and the debug device 55. When the address FIFO memory 43 and the data FIFO memory 44 are not empty.

In the processor 41, the address FIFO
The oldest address and data FIFO stored in the memory 43
The oldest data stored in the memory 44 is output to the address bus 53 and the data bus 54 via the buffer 46 and the buffer 50, respectively.

In the debug device 55, the monitor device 58 is connected to the address FIFO memory 43 via the address bus 53.
And the program output from the data FIFO memory 44 from the data bus 54 are input. Therefore, in this case, the operation of the central processing unit 2 can be grasped only for the program.

As described above, according to the second embodiment of the present invention, even when the data cache 7 or the instruction cache 8 is hit, the processor 41 outputs the address and data of the program and the operand to the outside. . Therefore, the debug device 55 enables debugging of the program without stopping the operation of the cache memory.

Further, according to the second embodiment of the present invention, an address FIFO memory 43 and a data FIFO memory 44 are provided to temporarily store program addresses and data, and to store operand addresses and data to the outside. By outputting the stored program address and data to the outside when they are not output, even if the processor 41 transfers the program and the operand by sharing the address bus 53 and the data bus 54, the addresses of the program and the operand are transferred. And data can be output to the outside.

Further, according to the second embodiment of the present invention, when a miss hit of the instruction cache 8 and an operand access occur simultaneously, the instruction cache 8 is repeatedly read at the same address. The bus control unit 42 does not need any means relating to the miss hit of the instruction cache 8.

In the second embodiment, the address FI
The program address and data are temporarily stored in the FO memory 43 and the data FIFO memory 44, and the stored program address and data are output to the outside when the operand address and data are not output to the outside. May temporarily store the operand address and data and output the stored operand address and data to the outside when the program address and data are not output to the outside, or the program and operand address And two addresses for storing data
It is also possible to provide a FIFO memory and a data FIFO memory, and output the other address and data stored when one address or data of one of the program and the operand is not output to the outside.

In the above embodiments of the present invention, both the data cache 7 and the instruction cache 8 are provided, but only one of them may be provided.

In the above embodiment, the processor outputs the access address of the cache and the data read from the cache when the cache hits, and inputs them by the monitor device in the debug device. Either one of them may be used. In particular, when only the address is added to the monitor device, the operation of the central processing unit 2 can be traced more widely than when only the data is added, such as tracing, address breakpoint processing, coverage measurement, and cache hit ratio measurement. Will be possible.

In the above embodiment, the processor outputs the access address of the cache and the data read from the cache at the time of a cache hit, and inputs them by the monitor device in the debug device. Processor outputs a cache hit signal,
A cache hit signal may be input to a monitor device in the debug device. This makes it possible to easily determine whether the access is due to a cache hit or a cache miss.

[0085]

As described above, the processor according to the present invention comprises a central processing unit for processing operands according to a program, a cache memory for storing the program or the operand, and a program or operand stored in the cache memory. And a bus controller for outputting at least one of the address to be read and the read content to the outside when the data is read.
According to this configuration, even during a cache hit, the read address or the read content of the cache memory can be tracked externally.

Further, a processor according to the present invention has an internal program bus for transferring a program and an internal operand bus for transferring an operand, and a central processing unit for processing the operand in accordance with the program; And an instruction cache memory for storing the program, a data cache memory for storing the operands connected to the internal operand bus, and an internal memory for reading the program stored in the instruction cache memory. A bus control device for outputting the contents on the program bus to the outside and outputting the contents on the internal operand bus to the outside when the operand stored in the data cache memory is read. According to this configuration, even if the instruction cache memory or the data cache memory hits, their operations can be tracked externally.

A processor according to the present invention has an internal program bus for transferring a program and an internal operand bus for transferring an operand, and a central processing unit for processing the operand in accordance with the program; An instruction cache memory for storing the program, temporary storage means for temporarily storing contents on the internal program bus when the program stored in the instruction cache memory is read, and the internal operand When the operand is transferred to the bus, only the content on the internal operand bus is output to the outside, and when the operand is not transferred to the internal operand bus, the content stored in the temporary storage means is output to the external. And a bus control device for outputting the data to the bus. According to this configuration, even if there is a single path to output to the outside,
The operation of the instruction cache memory and the address and data of the operand transferred to the internal operand bus can be tracked externally.

Further, a processor according to the present invention has an internal program bus for transferring a program and an internal operand bus for transferring an operand, a central processing unit for processing the operand in accordance with the program, and an internal operand bus. A data cache memory for storing the operands, temporary storage means for temporarily storing the contents on the internal operand bus when a program stored in the data cache memory is read, and When the program is transferred to the bus, only the contents on the internal program bus are output to the outside, and when the program is not transferred to the internal program bus, the contents stored in the temporary And a bus control device for outputting the data to the bus.
According to this configuration, the operation of the data cache memory and the address and data of the program transferred to the internal program bus can be tracked externally even if there is only one external output path.

Further, in the debugging device according to the present invention, a central processing unit for processing operands according to a program, a cache memory for storing the program or the operand, and a program or operand stored in the cache memory are read. A bus for outputting at least one of an address to be read and read contents to a bus, and outputting an address to be read to the bus when a program or an operand not stored in the cache memory is read. A processor having a control device, and a processor connected to the bus;
An emulation memory for supplying a program or an operand to the processor; and a monitor connected to the bus and tracking operation of the central processing unit in the processor based on contents on the bus.
According to this configuration, the monitor device can track the read address or read content of the cache memory during a cache hit and the read address or read content of the emulation memory during a cache miss.
The program can be debugged without stopping the operation of the cache memory.

A processor according to the present invention has an internal program bus for transferring a program and an internal operand bus for transferring an operand, and a central processing unit for processing the operand according to the program. An instruction cache memory that stores the program, and a bus control device that is connected to the internal program bus and the internal operand bus, wherein the central processing unit includes:
If reading of a program not stored in the cache memory and reading or writing of an operand occur simultaneously, cancel reading of the program;
A processor that is delayed or put on hold.
According to this configuration, since the reading of the program is repeated until the reading or writing of the operands does not occur at the same time, the bus control device does not need a means for reading a program that is not stored in the cache memory.

As described above, according to the present invention, it is possible to trace an operation such as tracing the execution address of a program even during a cache hit, and to debug the program without stopping the operation of the cache memory. An advantageous effect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a processor and a debug device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a processor and a debug device according to a second embodiment of the present invention.

DESCRIPTION OF SYMBOLS 1, 41 Processor 2 Central processing unit 3 Internal operand address bus 4 Internal operand data bus 5 Internal program address bus 6 Internal program data bus 7 Data cache 8 Instruction cache 9, 42 Bus control devices 10 to 15, 45 ~ 52 Buffer 16 Operand address bus 17 Operand data bus 18 Program address bus 19 Program data bus 20,55 Debug device 21,56 Data emulation memory 22,57 Program emulation memory 23,58 Monitor device 43 Address FIFO memory 44 Data FIFO memory 53 Address bus 54 Data bus

Claims (12)

[Claims] A central processing unit for processing operands according to a program; a cache memory for storing the program or the operand; and an address for reading when a program or operand stored in the cache memory is read. And a bus control device for outputting at least one of the read contents to the outside. 2. A central processing unit having an internal program bus for transferring a program and an internal operand bus for transferring an operand, performing a processing of the operand in accordance with the program, and connected to the internal program bus, An instruction cache memory connected to the internal operand bus, and a data cache memory storing the operands. When a program stored in the instruction cache memory is read, the contents on the internal program bus are read. A processor, comprising: a bus controller for outputting to the outside and outputting the contents on the internal operand bus to the outside when an operand stored in the data cache memory is read. 3. The bus control device according to claim 2, wherein each of the bus control devices is provided separately and connected to an external program bus for transferring a program to / from an external device and an external operand bus for transferring an operand to / from the external device. When the program stored in the instruction cache memory is read, the contents on the internal program bus are output to an external program bus, and when the operand stored in the data cache memory is read, A processor for outputting contents on an internal operand bus to an external operand bus. 4. A central processing unit having an internal program bus for transferring a program and an internal operand bus for transferring an operand, performing a processing of the operand in accordance with the program, and connected to the internal program bus, An instruction cache memory for storing the contents of the instruction cache memory, a temporary storage means for temporarily storing the contents on the internal program bus when the program stored in the instruction cache memory is read, and an operand transferred to the internal operand bus. A bus control device that outputs only the content on the internal operand bus to the outside when the operand is not transferred to the internal operand bus, and outputs the content stored in the temporary storage means to the outside when the operand is not transferred to the internal operand bus And a processor comprising: 5. The bus control device according to claim 4, wherein the bus control device is connected to a single external bus, and using the external bus, any of the content on the internal operand bus or the content stored in the temporary storage means. A processor that selectively outputs the data to the outside. 6. A central processing unit having an internal program bus for transferring a program and an internal operand bus for transferring an operand, and performing a processing of the operand in accordance with the program; A data cache memory for storing data stored in the data cache memory, a temporary storage means for temporarily storing the contents on the internal operand bus when the program stored in the data cache memory is read, and a program transferred to the internal program bus. A bus control device that outputs only the content on the internal program bus to the outside when the program is not transferred to the internal program bus, and outputs the content stored in the temporary storage unit to the outside when the program is not transferred to the internal program bus And a processor comprising: 7. The bus control device according to claim 6, wherein the bus control device is connected to a single external bus, and using the external bus, any of the content on the internal program bus or the content stored in the temporary storage means. A processor that selectively outputs the data to the outside. 8. A central processing unit for processing an operand according to a program, a cache memory for storing the program or the operand, and an address for reading when the program or operand stored in the cache memory is read. And at least one of the read contents is output to the bus,
A processor having a bus control device for outputting an address to be read to the bus when a program or an operand not stored in the cache memory is read; A debugging device, comprising: an emulation memory to be supplied; and a monitoring device connected to the bus and tracking the operation of the central processing unit in the processor based on the content on the bus. 9. The bus control device according to claim 8, wherein when a program or an operand stored in said cache memory is read, an address to be read and a read content are respectively stored in an address portion of said bus. A debugger for outputting the data to a data section, and wherein the monitor tracks the operation of the central processing unit in the processor based on the address and the data of the bus. 10. A bus control device according to claim 1, wherein when a program or an operand stored in a cache memory is read, an address to be read and a program or an operand stored in the cache memory are read. And outputting an identification signal indicating the fact to the outside. 11. A bus control device according to claim 8, wherein when a program or an operand stored in the cache memory is read, an address to be read is output to the bus, and the program or the operand stored in the cache memory is output. A debugging device for outputting an identification signal indicating that an operand has been read, wherein the monitor device tracks the operation of the central processing unit in the processor based on the address on the bus and the identification signal. . 12. A central processing unit having an internal program bus for transferring a program and an internal operand bus for transferring an operand, and performing a processing of the operand in accordance with the program. And a bus control device connected to the internal program bus and the internal operand bus, wherein the central processing unit reads a program that is not stored in the cache memory; A processor characterized by canceling, delaying, or suspending the reading of the program when reading or writing of operands occurs simultaneously.