JPH11154102A - Emulator having data conversion circuit - Google Patents

Abstract

(57) [Summary] [Problem] Without stopping execution of an evaluation CPU,
An object of the present invention is to easily change data in debugging and improve debugging efficiency. An address detection circuit for outputting an address coincidence signal when an coincidence between an address on an address bus and a preset address of data to be replaced is detected; An output prohibition circuit 32 for requesting output prohibition from the memory 2 to the data bus based on S4, and data for outputting preset conversion data to be replaced to the data bus in response to a request from the evaluation CPU 1. A data conversion circuit 3 including at least a switching circuit 34, and replaces data from the memory 2 with arbitrary conversion data during execution of the evaluation CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulator having a data conversion circuit, and more particularly, to an IC product having a microcomputer, which facilitates debugging of the IC product and improves debugging efficiency. About technology.

[0002]

2. Description of the Related Art Generally, in the development of an IC product incorporating a microcomputer, an emulator is used.
Debugging for verifying the hardware and software design of the IC product is performed.

[0003] That is, debugging means that the microcomputer and its peripheral circuits in an IC product repeatedly adjust parameter data using the actual machine environment until the microcomputer and the peripheral circuits satisfy the functional specifications and timing specifications at the time of design. The content is to confirm.

[0004] The emulator is a tool for confirming the operation of the target product by checking the operations of the CPU and the memory of the target product for the target in the debugging.

In general, such an emulator is mainly composed of an evaluation CPU having the same function as a target CPU, a rewritable memory, and a control CPU for controlling the entire emulator. They are connected by an address bus and a data bus.

A conventional debugging operation using an emulator will be described below.

[0007] In debugging of the target CPU and its peripheral circuits, the evaluation CPU executes the program while accessing the memory storing the parameter data as needed, and observes the actual operating state at that time while observing the actual target state. This is performed by repeatedly adjusting the parameter data stored in the CPU until a desired operation is realized. During the execution of the program, the address bus and the data bus between the evaluation CPU and the memory are in the exclusive state.

[0008] More specifically, the adjustment of the parameter data is performed at any time by a memory (RAM, Random).
This is performed by rewriting and changing the contents of the data table stored in the Access Memory) by the control CPU.

However, as described above, the address bus and data bus required for rewriting are exclusively used between the evaluation CPU and the memory due to the configuration, and the control CP
Since the bus was not released to U, the control CPU could not rewrite the contents of the memory during the execution of the program.

Therefore, when certain parameter data is changed,
In order to observe the operation state based on the parameter data after the change, the following series of procedures was required every time the change was performed. That is, first, the evaluation C
After stopping the program execution of the PU, the evaluation CPU and the peripheral circuits are simultaneously stopped, and the directions of the address bus and the data bus are switched toward the control CPU. Then, the content of the data table in the memory is controlled by the control CPU. Was rewritten, the evaluation CPU and the peripheral circuit were operated again, the evaluation CPU was re-executed from the first processing, and the operation state of the peripheral circuit was monitored. Also, rewriting of memory data is, specifically,
The corresponding portion of the data table stored in the memory had to be rewritten and loaded into the memory again.

In addition to the emulator having the above configuration, an OTP microcomputer, that is, an OTP (One Time)
A combination of an e-PROM and an evaluation microcomputer is also frequently used as a debugging tool. In the case of such an OTP microcomputer, the parameter data for evaluation can be written only once, and the memory cannot be rewritten. Therefore, a plurality of OTPs are prepared for each parameter data pattern, and the The data was being adjusted. Therefore, the change of the parameter data includes stopping the execution of the program by the evaluation CPU, stopping the evaluation CPU and peripheral circuits, replacing the OTP, and re-executing the program from the first processing, as in the above-described emulator. Was needed.

[0012]

As described above, the above-mentioned conventional emulator has the following problems. That is,
In order to adjust the parameter data to be programmed in the microcomputer, it is necessary to rewrite the data in the memory. Each time such a change is made, the evaluation CP
After stopping the execution of the program U, the evaluation CPU and the peripheral circuits were simultaneously stopped, and the program was executed again from the first processing, so that it took a long time to adjust the parameters. Further, as described above, the work of changing the parameter data on the memory itself took a long time.

Therefore, the debugging work itself was inefficient. And this is especially
When a parameter is required to be finely adjusted, such as in an image display device that requires confirmation of the display function, the parameter is frequently changed, or when a predetermined operation point is reached, such as in a certain peripheral circuit. This is particularly noticeable in cases where it takes a long time to perform the operations and it is difficult to compare the operations, etc., and has become a bottleneck in debugging, prolonging the debugging work and impeding the speeding up. That is, in these processes, particularly, easy change and continuous change of data are required, but this cannot be realized by the conventional emulator.

As described above, the present invention has been made in order to solve the problem in the prior art that it takes a long time to adjust parameter data in debugging and debugging work is inefficient. It is. The purpose is to evaluate the CPU during program execution.
Has a data conversion circuit capable of easily changing data in debugging without stopping execution of the evaluation CPU, and improving debugging efficiency by replacing data read by the CPU with arbitrary data. To provide an emulator.

Another object of the present invention is to further improve the debugging efficiency by rewriting the contents of the memory with the replaced data, thereby leaving the parameter data obtained with a good evaluation.

Another object of the present invention is to achieve more accurate parameter adjustment by replacing data with arbitrary data in bit units.

In addition, another object of the present invention is to make it possible to continuously check the operation in the vicinity of the parameter data by performing replacement with data that has been continuously increased or decreased with arbitrary data as a starting point. To improve the efficiency of the system.

[0018]

In short, the device of the present invention (claim 1) comprises an evaluation CPU and at least a memory connected by an address bus and a data bus between the evaluation CPU and the evaluation CPU. Requesting output prohibition from the memory to the data bus when the emulator has at least a match between an address on the address bus and a preset address of data to be replaced. A data conversion circuit for outputting, to the data bus, any conversion data set in advance, which is to be replaced, in response to a request from the evaluation CPU. . According to this method, when a match between the address on the address bus and the address of the preset replacement target data is detected, the data originally output from the memory is replaced with arbitrary data. It is possible to easily change the data read by the evaluation CPU without stopping the execution.

According to the second aspect of the present invention, at least a memory connected by an address bus and a data bus is provided between the evaluation CPU and the evaluation CPU.
An emulator having at least: an address connected to the address bus, and an address on the address bus;
When a match with a preset address of data to be replaced is detected, an address detection circuit that outputs an address match signal, and, based on the address match signal, a signal from the memory to the data bus. An output inhibition circuit for requesting output inhibition, connected to the data bus,
In response to the request of the evaluation CPU, a preset
And a data switching circuit for outputting conversion data to be replaced to the data bus, the data switching circuit having at least a data switching circuit. The read data can be easily changed.

Further, in the invention according to claim 3, the memory is a rewritable memory, and the data conversion circuit further includes a memory for writing the evaluation data based on the address match signal in accordance with a preset write request. A signal conversion circuit that converts a read signal output from the CPU as a write signal to the memory and outputs the converted data output from the data switching circuit; By doing, C for evaluation
It is possible to simultaneously rewrite the contents of the memory with any data that has been replaced for the PU. That is,
The parameter data with good evaluation can be left on the memory as it is, and can be used for subsequent operation check.

According to a fourth aspect of the present invention, there is provided an emulator having at least a memory connected by an address bus between the evaluation CPU and the evaluation CPU, the emulator being connected to the address bus, When a match between an address on the address bus and a preset address of data to be replaced is detected, an address detection circuit that outputs an address match signal, A data bus is provided between the bit data switching determination circuit that outputs a bit switching permission signal for a replacement designation bit in the replacement target data in accordance with the set conversion bit pattern data, and the evaluation CPU and the memory. And input based on the bit switching permission signal. The data to be replaced is replaced only with respect to the replacement designation bit according to the bit pattern data, and a data conversion circuit having at least a bit data switch for outputting to the data bus is provided. Replacement with data can be performed. That is, the adjustment of the parameter data based on the bit pattern is also facilitated.

Further, in the invention according to claim 5, the data switching circuit or the bit data switch further outputs the data after the replacement.
A data output completion signal is output, and the data conversion circuit further performs any one of an increment and a decrement on the conversion data for performing a preset replacement based on the data output completion signal in accordance with a preset value. In this case, the replacement data can be continuously increased / decreased from an arbitrary data as a starting point by providing a circuit for outputting the data to the data switching circuit or the bit data switch. That is, it is possible to continuously confirm the operation near the parameter data.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. In the present embodiment, in response to a data request from the CPU for evaluation, a function of replacing the arbitrary data without stopping the CPU for evaluation and rewriting the memory with the replaced data is realized.

FIG. 1 is a diagram showing a system configuration of the emulator according to the present embodiment. As shown in FIG. 1, the emulator according to the present embodiment includes an evaluation CPU 1 for executing a program, a memory 2, and a data conversion circuit 3. Here, the evaluation CPU 1 and the memory 2 are connected by an address bus and a data bus, and the data conversion circuit 3 is also connected to these buses. In the following figures, AB
US indicates an address bus, and DBUS indicates a data bus.

FIG. 2 is a block diagram showing a circuit configuration of the data conversion circuit 3. The data conversion circuit 3 is a circuit constituting a novel part of the present invention. As shown in FIG. 2, the data conversion circuit 3 further includes an address detection circuit 31, a DBUS output inhibition circuit 3,
2. RD / WR signal conversion circuit 33, data switching circuit 34
It consists of.

The address detection circuit 31 compares the address of the data to be replaced, which is set in the address setting register in advance, with the address on the ABUS. Outputs a signal. The setting of the address does not necessarily need to be performed by the address setting register, but may be provided from outside the data conversion circuit 3 by some method. The same applies to other registers described later, such as other data setting registers and memory write permission registers.

When an address match signal is input, the DBUS output prohibition circuit 32 sends an MO signal to the memory 2.
By outputting an E (Output Enable) signal, output from the memory 2 to DBUS is inhibited (Hi-
Z).

When a write request is set in the memory write enable register, the RD / WR signal conversion circuit 33 forcibly sends an RD (read) signal S1a output from the evaluation CPU 1 to a WR (write) request. , And outputs an M-WR signal S2b to the memory 2 so as to perform an operation when writing from the evaluation CPU is instructed.

When the address match signal S4 is input, the data switching circuit 34 outputs data set in advance in the data setting register to DBUS.

The emulator having the data conversion circuit according to the present embodiment is configured as described above.
The operation will be described.

(1) First, the operation in replacing read data from the memory 2 will be described below.

First, data to be replaced is set in advance as an initial setting. Specifically, first, an address at which data to be replaced is stored is set in an address setting register, and data having arbitrary contents to be replaced is set in a data setting register.

Next, actual debugging is performed. At this time, the contents of the address setting register and
After the addresses on the ABUS match, the evaluation CPU 1
When the RD signal S1a is output, the data conversion circuit 3 according to the present embodiment operates.

Here, the address detection circuit 31 compares the address preset in the address setting register with the address AB.
When a match between addresses on the US is detected, an address match signal S4 is output to the DBUS output prohibition circuit 32, the RD / WR signal conversion circuit 33, and the data switching circuit 34, respectively.

In response to the input of the address match signal S4, the DBUS output inhibition circuit 32 outputs the data from the memory to the data bus by the M-OE signal S3b for the memory 2 regardless of the state of the OE signal S3a at that time. Requests a forbidden (Hi-Z) state. Further, in response to the address match signal S4, the data switching circuit 34 sets the evaluation CPU
When the RD signal S1a is input from No. 1, data set in advance in the data setting register is output to DBUS.

Thus, after outputting the RD signal S1a, the evaluation CPU 1 reads not the output data from the memory 2 but the data output from the data switching circuit 34 at a predetermined read timing.

On the other hand, the contents of the address setting register and A
When the WR signal S2a is output from the evaluation CPU 1 after the addresses on the BUS match, the data output from the evaluation CPU 1 is written to the memory 2 as it is in a normal operation. During the write cycle of the evaluation CPU 1 to the memory 2, the RD signal S1a is not input to the data switching circuit 34, so that the data output port of the data switching circuit 34 is output inhibited (Hi
-Z) state. Therefore, the data output from the evaluation CPU 1 does not collide with the data set in the data setting register on the DBUS.

The contents of the address setting register and A
While the addresses on the BUS do not match, the evaluation CP
Even if the RD signal S1a is output from U1, the address detection circuit 31 does not output the address match signal S4.

When the address match signal S4 is not input, the DBUS output inhibition circuit 32 outputs the OE signal S4.
3a is output as it is to the memory 2 as the M-OE signal S3b, and the RD / WR signal conversion circuit 33 also changes the output state of the RD signal S1a to M-OE signal S3b.
Output to the memory 2 as the RD signal S1b.

Further, when the address match signal S4 is not input, the data switching circuit 34 does not output the data of the data setting register even if the RD signal S1a is generated. That is, each signal from the evaluation CPU 1 is passed through to the memory 2 as it is, and a normal operation of reading data from the memory 2 is performed.

This operation is the same even when the evaluation CPU 1 outputs the WR signal S2a.
The / WR signal conversion circuit 33 changes the state of the WR signal S2a to
Since the data is output as it is to the memory 2 as the M-WR signal S2b, the data output from the evaluation CPU 1 is written to the memory 2 as it is.
At this time, since the data output port of the data switching circuit 34 is in the output inhibition (Hi-Z) state unless the address match signal S4 is input, the evaluation CPU 1
The output data does not collide with the data set in the data setting register on DBUS. That is, when the address match signal is not output, a normal write operation to the memory 2 becomes possible.

(2) Next, an operation of simultaneously replacing read data from the memory 2 and writing the replaced data to an arbitrary address in the memory 2 will be described below.

First, as an initial setting, replace
And the settings of the data to be rewritten in the memory 2
This is performed in the same manner as in (1). Further, here, a write request is set in the memory write permission register in order to instruct the memory 2 to write the replaced data.

Next, during the actual debugging work,
When the RD signal S1a is output from the evaluation CPU 1 after the contents of the address setting register match the address on the ABUS, the data conversion circuit 3 according to the present embodiment
Operates in the same manner as (1), but here, since writing is requested by the memory write enable register, the RD / WR signal conversion circuit 33
4 simultaneously outputs the data, the RD signal S1a output from the evaluation CPU 1 is forcibly converted into a write request, and the M-WR signal S2b is output to the memory 2.
With this operation, the read cycle of the evaluation CPU 1 is converted into a write cycle in a pseudo manner, and the data output from the data switching circuit 34 is further written into the memory 2 in the same cycle.

The contents of the address setting register and AB
Regarding the operation when the WR signal S2a is output from the evaluation CPU 1 after the address on the US matches and the operation when the address on the ABUS does not match the contents of the address setting register, see (1). The same is true.

According to the present embodiment, the following effects can be obtained. That is, A between the evaluation CPU 1 and the memory 2
BUS is monitored from time to time, and when a match with an address previously set in the address setting register is detected, by replacing data originally output from the memory with arbitrary data, that is, by converting read data, The data read by the evaluation CPU 1 can be easily changed to data of any content during runtime without stopping the program execution of the evaluation CPU 1.

Further, it is also possible to simultaneously rewrite the contents of the memory with arbitrary data obtained by replacing the evaluation CPU.

Second Embodiment Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings, focusing only on the differences from the first embodiment. In this embodiment, in response to a data read request from the evaluation CPU, bit-by-bit replacement with arbitrary data without stopping the evaluation CPU and a data write request of an arbitrary address from the evaluation CPU Similarly, a function of replacing write data for each bit is realized without stopping the evaluation CPU.

FIG. 3 is a diagram showing a system configuration of the emulator according to the present embodiment. As shown in FIG. 3, the emulator according to the present embodiment includes an evaluation CPU 1 for executing a program, a memory 2, a bit data conversion circuit 4
It is composed of Here, the evaluation CPU 1 and the memory 2 are connected by an address bus, and the data bus is connected between the evaluation CPU 1 and the bit data conversion circuit 4 via the bit data conversion circuit 4. , And a data bus (M-DBUS) between the memory 2 and the bit data conversion circuit 4.

FIG. 4 is a block diagram showing a circuit configuration of the bit data conversion circuit 4. Bit data conversion circuit 4
Is a circuit constituting a new part of the present invention. As shown in FIG. 4, an address detection circuit 31, a bit data switching determination circuit 41, a read bit data switching multiplexer 42, and a write bit data switching A multiplexer 43 is provided.

Here, the bit data switching judgment circuit 41
When an address match signal S4 is input, a bit switching permission signal S5 for designating permission / prohibition of switching for each bit is set according to the content of the data setting register in accordance with the bit designated for replacement. Output to the data switching multiplexers 42 and 43.

The bit data switching multiplexer 42,
Reference numeral 43 replaces only the bits of the input data which are permitted to be replaced by the bit switching permission signal S5 with the contents of the bit data of the data setting register, and merges and outputs the data. That is, in the case of the read bit data switching multiplexer 42, the data input from the M-DBUS, that is, the output data from the memory 2 is replaced with the designated bit and output to the DBUS to be read data of the evaluation CPU 1. . In the case of the write bit data switching multiplexer 43, data input from DBUS,
That is, the output data from the evaluation CPU 1 is replaced with respect to the designated bit, and is output to the M-DBUS to be written data to the memory 2.

It is to be noted that the replacement for each bit applies to all bits of the DBUS of the emulator, and it is also possible to replace only the designated bits.
It is also possible to replace all bits of S at the same time.

The emulator having the data conversion circuit according to the present embodiment is configured as described above.
The operation will be described.

(1) First, an operation of replacing a designated bit of data read from the memory 2 in response to a read request will be described below.

First, as initial setting, bit data to be replaced is set in advance. Specifically, first, the address at which the bit data to be replaced is stored is
Set in the address setting register, and set the bit data to be replaced in the data setting register. In this case,
Replacement data is set for all bits of DBUS of the system, but don't care is set for bits that do not replace data.

Next, the actual debugging work is performed. At this time, the contents of the address setting register and
When the addresses on the ABUS match, the bit data conversion circuit 4 according to the present embodiment operates.

First, the address detection circuit 31 compares the address preset in the address setting register with the ABU
When a match of the address on S is detected, an address match signal S4 is output to the bit data switching determination circuit 41.

In response to the input of the address coincidence signal S4, the bit data switching determination circuit 41 outputs a bit switching permission signal S5 to the bit data switching multiplexers 42 and 43, respectively. The bit switching permission signal is a signal that permits switching only for bits for which replacement is specified in advance in the data setting register, and prohibits switching for bits that are not specified.

Here, the RD signal S1
a is output, the read bit data switching multiplexer 42 outputs the DBUS line,
The M-DBUS line is in an input permission state. The RD signal S1a output from the evaluation CPU 1 is also input to the memory 2 together with the read bit data switching multiplexer 42, and accordingly, the read data is output from the memory 2 to the M-DBUS. Is done.

The read bit data switching multiplexer 42 sets the read data input from the M-DBUS in the data setting register in advance only for bits for which bit replacement is permitted according to the bit switching permission signal S5. The data is replaced with the bit pattern of the content, and the replaced data is output to DBUS. Therefore, at this time, the bits set to "don't care" in the data setting register are not replaced, and are output to DBUS with the bit contents input from M-DBUS.

Thus, after outputting the RD signal S1a, the evaluation CPU 1 reads the data output from the read bit data switching multiplexer 42 in which only the desired bits have been replaced at a predetermined read timing. Will do. The replacement for each bit is for all bits of the emulator DBUS.
It is possible to replace only specified bits. It is also possible to replace all bits of DBUS at the same time.

Here, the contents of the address setting register,
While the addresses on ABUS do not match, the evaluation C
Even when the RD signal S1a is output from the PU1, the address detection circuit 31 does not output the address match signal S4, as in the first embodiment.

Thus, the bit data switching determination circuit 4
1 does not output the bit switching permission signal S5 corresponding to the address coincidence signal S4, and therefore the read bit data switching multiplexer 42 does not perform the above-described data replacement. That is, the RD signal S1a from the evaluation CPU 1 is passed through to the memory 2 as it is, and the normal operation of reading data from the memory 2 is performed.

(2) Next, the operation of replacing the designated bits of the data written from the evaluation CPU 1 to the memory 2 in response to the write request will be described below.

First, as an initial setting, data to be rewritten in the memory 2 is set in advance for each bit as in the case of (1).

Next, in an actual debugging operation, first, the address detection circuit 31 and the bit data switching determination circuit 41 perform the address matching signal S4 and the bit switching permission signal under the same conditions as in (1). Output S5.

Here, the WR signal S2 from the evaluation CPU 1
a is output, the write bit data switching multiplexer 43 sets the DBUS line to an input enabled state,
The M-DBUS line is in an output enabled state.

The write bit data switching multiplexer 43 converts the write data input from DBUS from the evaluation CPU 1 in accordance with the bit switching permission signal S5.
Only for bits for which bit replacement is permitted, data replacement is performed using the bit pattern of the content set in the data setting register in advance, and the replaced data is output to M-DBUS. Therefore, at this time, the bits set to "don't care" in the data setting register are not replaced, and are output to the M-DBUS with the bit contents input from DBUS.

The WR signal S output from the evaluation CPU 1
2a is a write bit data switching multiplexer 4
3 and also input to the memory 2. As a result, the write data from the evaluation CPU 1 is converted to data output from the write bit data switching multiplexer 43 in which only desired bits are replaced, and is written to the memory 2. The replacement for each bit is performed in the DB of the emulator as in (1).
All bits of the US are targeted, and it is possible to replace only specified bits. It is also possible to replace all bits of DBUS at the same time.

Here, the contents of the address setting register and
While the addresses on ABUS do not match, the evaluation C
Even when the WR signal S2a is output from the PU1, the address detection circuit 31 does not output the address coincidence signal S4 as in the first embodiment.

Thus, the bit data switching determination circuit 4
1 does not output the bit switching permission signal S5 corresponding to the address coincidence signal S4, and therefore the write bit data switching multiplexer 43 does not perform the above-described data replacement. That is, a normal operation of writing data from the evaluation CPU 1 to the memory 2 is performed.

According to the present embodiment, the following effects can be obtained. That is, when a match with an address previously set in the address setting register is detected, data originally output from the memory is replaced with arbitrary data in units of bits, that is, by converting read data,
Without stopping the program execution of the evaluation CPU 1,
During runtime, it is possible to easily convert data to be read by the evaluation CPU 1 into data of an arbitrary bit pattern.

Similarly, data written from the evaluation CPU 1 to the memory 2 can be converted into data having an arbitrary bit pattern.

Third Embodiment Hereinafter, a third embodiment of the present invention will be described in detail only with respect to differences from the first and second embodiments with reference to the drawings. In the present embodiment, the data stored at an arbitrary address is added to the emulator having the data conversion circuit according to the first embodiment by further performing data replacement and then incrementing or decrementing the data. Is realized continuously.

FIG. 5 is a block diagram showing a circuit configuration of the data conversion circuit 3 according to the present embodiment. As shown in FIG. 5, the data conversion circuit 3 according to the present embodiment includes an address detection circuit 31, a DBUS output inhibition circuit 32, an RD / WR signal conversion circuit 33, and a data switching circuit 34, which are included in the first embodiment. In addition, it is configured by an increment / decrement circuit 35.

Here, the data switching circuit 34, in addition to the configuration of the first embodiment, further outputs a data output completion signal S6 for notifying DBUS that data has been output.

When the data output completion signal S6 is input, the increment / decrement circuit 35 operates according to the contents of a preset circuit switching register.
+1 or -1 is added to the replacement data set in the data setting register and held internally.

The emulator having the data conversion circuit according to the present embodiment is configured as described above.
The operation will be described.

First, as the initial setting, the data to be replaced and its address are set in the same manner as in the case (1) of the first embodiment. Here, further, the replacement data is set in the circuit switching register as to whether the next increase or decrease, that is, whether the increment or the decrement is performed.

Next, the actual debugging work is performed. At this time, the contents of the address setting register and
When the addresses on the ABUS match, and the RD signal S1a is output from the evaluation CPU 1, the address detection circuit 31 and the DBUS output prohibition circuit 32 operate under the same conditions as in the first embodiment. Works. Here, the data conversion circuit 34 also operates in the same manner as in the first embodiment, but finally, at the timing when the replacement data is output to DBUS, the data conversion circuit 34 further operates the increment / decrement circuit 35. , And outputs a data output completion signal S6.

Increment / decrement circuit 35
When the data output completion signal S6 is inputted, the replacement data stored therein is incremented or decremented according to the contents of the circuit switching register. That is, +1 is added to the value of the replacement data currently held when the increment is set in the circuit switching register, and -1 is added to the value when the decrement is set. Is added.

After outputting the RD signal S1a, the evaluation CPU 1 reads the replacement data output from the data switching circuit 34 to DBUS at a predetermined read timing. Therefore, next, at the timing of detecting the coincidence between the contents of the address setting register and the address on the ABUS, the increment / decrement circuit 35 adds the replacement data set in the data setting register to +1 or -1. Is replaced data, and the data switching circuit 34
The value is output to the US, and the value is read by the evaluation CPU 1.

By repeating the above process, the replacement data can be continuously increased or decreased to adjust the parameter data.

In the increment / decrement circuit 35, when the replacement data is "FF [h]" and the increment function is operated, the replacement data becomes "00 [h]" and the replacement data becomes "00 [h]".
When the decrement function operates in [h] ”, the replacement data becomes“ FF [h] ”.

The function of the present embodiment for continuously replacing data is not limited to the addition to the first embodiment described above, but also to the second embodiment. Similarly, an increment / decrement function can be provided inside the bit data conversion circuit 4. According to such a configuration, it is possible to continuously replace or rewrite data stored at an arbitrary address.

According to the present embodiment, the following effects can be obtained. That is, after the replacement data is output on DBUS in one cycle, the value of the replacement data is incremented or decremented each time the address match signal S4 is next input to the data switching circuit 34. A continuous data conversion operation, in which the replacement data is further continuously increased or decreased and read into the evaluation CPU 1 or, at the same time, written into the memory 2, has become possible.

Fourth Embodiment Hereinafter, a fourth embodiment of the present invention will be described in detail only with respect to differences from the above-described embodiment with reference to the drawings. In the present embodiment, an event function for repeatedly setting replacement data and setting a range is added to the continuous data replacement function provided by the emulator having the data conversion circuit according to the third embodiment. is there.

FIG. 6 is a block diagram showing a circuit configuration of the data conversion circuit 3 according to the present embodiment. As shown in FIG. 6, the data conversion circuit 3 according to the present embodiment includes an address detection circuit 31, a DBUS output inhibition circuit 32, an RD / WR signal conversion circuit 33, a data switching circuit 34, which are included in the third embodiment. Increment / decrement circuit 35
And an address event circuit 36 and a data event circuit 37.

Here, when the address coincidence signal S4 is input, the address event circuit 36 determines how many times the corresponding address set in the address event register is read before replacing the data. The number of address matches, which indicates the number of repetitions, is compared with the value of the number of times the address match signal S4 corresponds to the read, and if the comparison result matches, the address event match signal is set to DBUS output inhibit circuit 32, RD
/ WR signal conversion circuit 33 and data switching circuit 34.

The data event circuit 37 is located between the increment / decrement circuit 35 and the data switching circuit 34 and has a maximum value or a minimum value of the replacement data set in advance in the data event register. Is compared with the data input from the increment / decrement circuit 35, and when the comparison results match, the increment / decrement circuit 35 is instructed to the increment / decrement circuit 35 by the data initialization request signal S8. Requests a reset of the value to its initial value.

The emulator having the data conversion circuit according to the present embodiment is configured as described above.
The operation will be described.

First, as initial settings, data to be replaced and addresses thereof are set in the same manner as in the third embodiment. Here, the number of address matches is set in the address event register as a repetitive setting of how many times the corresponding address is read before data replacement is performed. In the data event register, the maximum value or the minimum value of the data to be continuously replaced is set as the one to set the range of the data to be replaced.

Here, for example, “10 [h]” to “1”
When it is desired to repeat the continuous switching up to F [h] "many times, an increment is set in the circuit switching register and the maximum value" 1F "is set in the data event register.
[H] ”is set, and once is set in the address event register so as to perform switching every time. In addition, after the data at address 100 is read twice, data replacement is performed. If desired, the address 100 is set in the data setting register, and the address event register is set twice.

Next, the actual debugging work is performed. At this time, the contents of the address setting register and
If the addresses on the ABUS match, the address detection circuit 31 outputs an address match signal S4 to the address event circuit 36.

When the address match signal S4 is input, the address event circuit counts the input and compares it with the number of address matches set in the address event register in advance. If the comparison results match, the DBUS output prohibition circuit 32, RD /
An address event match signal S7 is output to each of the WR conversion circuit 33 and the data switching circuit 34.

The DBUS output inhibition circuit 32, the RD / WR conversion circuit 33, and the data switching circuit 34 receive an address event match signal S7 assuming that they perform the same function as the address match signal S4 in the third embodiment. Thus, the operation is performed in the same manner as in the third embodiment. In addition, similarly to the third embodiment, the increment / decrement circuit 35 also receives the replacement data internally held in accordance with the contents of the circuit switching register in response to the input of the data output completion signal S6 from the data switching circuit 34. Is incremented or decremented.

The replacement data thus incremented or decremented is output to the data event circuit 37 here. The data event circuit 37 compares the maximum value or the minimum value data set in the data event register in advance. When the comparison results match, the data initialization request signal S8 is output to the increment / decrement circuit 35 assuming that the maximum value or the minimum value of the replacement data has been reached, and the replacement data is initialized. Instruct The increment / decrement circuit 35 resets the value of the replacement data output on DBUS to the value set in the data setting register according to the data initialization request signal S8.

After outputting the RD signal S1a, the evaluation CPU 1 reads the replacement data output from the data switching circuit 34 to DBUS at a predetermined read timing.

By repeating the above processing, the function of continuously increasing or decreasing the replacement data can be added, and further, the replacement data can be repeatedly set and the range can be set.

According to the present embodiment, the following effects can be obtained. That is, the range of the data to be replaced and the number of repetitions are set in advance, and the continuous switching of the replacement data is controlled by using the data range. Flexible debugging that can be performed repeatedly is now possible.

Fifth Embodiment Hereinafter, a fifth embodiment of the present invention will be described in detail with reference to the drawings, focusing only on the differences from the above-described embodiment. The present embodiment provides a function of replacing a plurality of data when there are a plurality of parameter data to be adjusted at the same time.

FIG. 7 is a block diagram showing a circuit configuration of the data conversion circuit 3 according to the present embodiment. As shown in FIG. 7, the data conversion circuit 3 according to the present embodiment includes an address detection circuit 31, a DBUS output inhibition circuit 32, an RD / WR signal conversion circuit 33, An address selector 38 and a data selector 39 are provided in addition to the data switching circuit 34.

Here, the address selector 38 sequentially selects a register from a plurality of address setting registers, reads the address of the replacement data set in the address setting register, and detects the address. Set in the circuit 31.

Similarly, the data selector 39 sequentially selects a register from a plurality of data setting registers, reads the replacement data set in the data setting register, and switches the data. Set in the circuit 34.

The emulator having the data conversion circuit according to the present embodiment is configured as described above.
The operation will be described.

First, as the initial setting, the data to be replaced and its address are set. Here, the storage addresses of the plurality of replacement data are stored in the address setting register in the order in which the data is to be replaced. 1, the address setting register 2,... Are set in the order of the address setting register n.

Similarly, regarding the contents of the data, the contents of the plurality of replacement data are written in the data setting register 1, the data setting register 2,
... Set in the order of the data setting register n.

During the actual debugging, if the contents of the address setting register and the address on the ABUS match, the address detection circuit 31 outputs the address match signal S4.
Is output to the address selector 38 and the data selector 39 in addition to the DBUS output inhibition circuit 32, the RD / WR signal conversion circuit 33, and the data switching circuit 34.
Here, the operations of the DBUS output inhibition circuit 32, the RD / WR signal conversion circuit 33, and the data switching circuit 34 are the same as those in the first embodiment. Data switching circuit 34
Outputs the contents of the data setting register currently set by the data selector 39 to DBUS.

On the other hand, when the address match signal S4 and the RD signal S1a are input, the address selector
Next, the address of the replacement data set in the register is read out from the address setting register pointed to, and set in the address detection circuit 31.

Similarly, when the address match signal S4 and the RD signal S1a are input, the data selector 39 changes the replacement data set in the register from the data setting register pointed to next. The contents are read out and set in the data switching circuit 34.

After outputting the RD signal S1a, the evaluation CPU 1 reads the data output to the DBUS from the data switching circuit 34 at a predetermined read timing.

By repeating the above processing, a plurality of replacement data can be combined and replaced at the same time.

According to the present embodiment, the following effects can be obtained. In other words, by setting the addresses and contents of a plurality of replacement data in advance by using a plurality of registers, and controlling the replacement data in order, it is possible to debug a peripheral circuit operating by combining some data. ,
Data replacement function can be used. With this function, for example, this data replacement function can be effectively used even for a peripheral circuit that normally operates by replacing the data at address 100 and then replacing the data at address 200.

[0115]

As described above, according to the present invention,
The following effects are obtained. That is, evaluation C
The address bus between the PU and the memory is monitored as needed, and when a match with a preset address is detected, the data originally output from the memory is replaced with arbitrary data, thereby executing the evaluation CPU. Without stopping,
While observing the operating states of the microcomputer and the peripheral circuits in real time, the read data can be easily changed. Therefore, there is an effect that adjustment of parameter data in debugging can be performed efficiently.

Furthermore, since there is a function of simultaneously rewriting the contents of the memory with arbitrary data that has been replaced with the evaluation CPU, the parameter data with a good evaluation is left in the memory, and the operation is checked afterwards. The effect that it can be used as it is is obtained. This makes it possible to easily adjust a plurality of parameter data that are related to each other.

Also, since the function of replacing data with arbitrary data in bit units is provided, an effect is obtained that adjustment of parameter data based on a bit pattern is facilitated.

Further, since there is a function of continuously increasing or decreasing replacement data starting from arbitrary data, an effect that continuous operation confirmation in the vicinity of the parameter data can be performed can be obtained. As a result, even when the value range of the parameter has not been narrowed down yet or when the operation of the peripheral circuit is checked,
It is possible to easily adjust the parameter data.

The present invention can be applied to a wide range of applications, and can be said to be particularly effective in, for example, color adjustment of TVs and peripheral circuits for controlling motors of cars, videos, CDs and the like.

For example, when selecting a color to be displayed on an on-screen display for displaying a character on a CRT, it is basically necessary to grasp not only only red, only blue, and green but also their composite colors by numerical values. In this case, if the apparatus of the present invention is used, the data for actually determining the color can be replaced in real time, and the numerical value can be easily determined while observing the color change appearing on the display.

On the other hand, in adjusting the speed of the vehicle, the motor is controlled by the degree of depression of the accelerator or brake and the gear ratio. Also, when starting the vehicle, it is necessary to ensure the safety of humans, the comfort of ride, and the load on the motor in consideration of the vehicle weight. To satisfy these conditions, when developing a program,
When a person actually gets into a car and controls the motor with various parameter data prepared in advance, debug the program while ensuring human safety, ensuring comfortable riding comfort, and feeling whether there is a load on the motor doing. Especially,
When the speed is adjusted by changing the rotation speed stepwise like a motor, it is essential to change the data in real time. In this case, by using the apparatus of the present invention, data can be easily changed in real time, and the development environment and development efficiency of the program are improved.

As described above, according to the present invention, by improving the efficiency of debugging, the turnaround time from the prototype to the commercialization of an IC product incorporating a microcomputer can be shortened, and the product cost can be reduced. This is an invention that can produce an effect and is extremely effective industrially.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration of an emulator having a data conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration in the data conversion circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a system configuration of an emulator having a bit data conversion circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a circuit configuration in a bit data conversion circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a circuit configuration in a data conversion circuit according to a third embodiment of the present invention.

FIG. 6 is a block diagram illustrating a circuit configuration in a data conversion circuit according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram illustrating a circuit configuration in a data conversion circuit according to a fifth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 evaluation CPU 2 memory 3 data conversion circuit 4 bit data conversion circuit 31 address detection circuit 32 DBUS output inhibition circuit 33 RD / WR signal conversion circuit 34 data switching circuit 35 increment / decrement circuit 36 address event circuit 37 data event circuit 38 Address selector 39 Data selector 41 Bit data switching determination circuit 42 Bit data switching multiplexer (for RD) 43 Bit data switching multiplexer (for WR) S1a RD signal S1b M-RD signal S2a WR signal S2b M-WR signal S3a OE signal S3b M-OE signal S4 Address match signal S5 Bit switching permission signal S6 Data output completion signal S7 Address event match signal S8 Data initialization request signal

Claims (5)

[Claims] 1. An emulator having at least an evaluation bus and a memory connected by an address bus and a data bus between the evaluation CPU and the evaluation CPU, comprising: an address on the address bus; When detecting a match with the address of the data to be replaced, a request is made to prohibit output from the memory to the data bus, and a preset value is set in response to a request from the evaluation CPU. Was
An emulator comprising a data conversion circuit for outputting arbitrary conversion data to be replaced to the data bus. 2. An emulator having at least an evaluation bus and a memory connected by an address bus and a data bus between the evaluation CPU and the evaluation CPU, wherein the emulator is connected to the address bus, An address detection circuit that outputs an address match signal when a match between the above address and a preset address of the data to be replaced is detected, based on the address match signal, An output prohibition circuit for requesting output prohibition to the data bus; and an output prohibition circuit connected to the data bus and outputting preset conversion data to be replaced to the data bus in response to a request from the evaluation CPU. An emulator comprising a data conversion circuit including at least a data switching circuit. 3. The memory according to claim 2, wherein the memory is a rewritable memory, and the data conversion circuit further outputs a read signal output from the evaluation CPU based on the address match signal in accordance with a preset write request. And a signal conversion circuit that converts and outputs a write signal to the memory, wherein the conversion data output from the data switching circuit is
3. The emulator according to claim 2, further comprising a rewrite output to said memory. 4. An emulator having at least a memory connected by an address bus between the evaluation CPU and the evaluation CPU, wherein the emulator is connected to the address bus, and an address on the address bus is determined in advance. An address detection circuit that outputs an address match signal when a match with the set address of the data to be replaced is detected; and based on the address match signal, bit pattern data of a preset conversion. And a bit data switching determination circuit that outputs a bit switching permission signal for a replacement designation bit in the replacement target data, and the evaluation CPU and the memory are respectively connected by a data bus, and the bit switching permission Based on the signal, the input replacement target data, An emulator comprising: a data conversion circuit having at least a bit data switch for performing replacement according to the bit pattern data only for replacement designation bits and outputting the data to the data bus. 5. The data switching circuit or the bit data switch further outputs a data output completion signal after outputting the replaced data, and the data conversion circuit further comprises: Based on the data output completion signal, the conversion data for which a preset replacement is performed, according to a preset value, performs either increment or decrement, and outputs the data to the data switching circuit or the bit data switch. The emulator according to any one of claims 2 to 4, further comprising a circuit for performing: