JPH11143814A - Dma controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To recover an abnormal state that occurs in the case of transferring data in a signal address mode by detecting that elapsed time when access to 1st or 2nd storage devices is executed reaches 1st or 2nd supervisory time and resetting 1st and 2nd transfer controllers. SOLUTION: An elapsed time measuring circuit 1E measures an elapsed time by a counter control circuit 1C at the time of access start the memory that is a 1sst storage device or a hard disk that is a 2nd storage device. A comparator circuit 1G compares the measured elapsed time with supervisory time that is stored in a supervisory time storage circuit 1F, and when the elapsed time exceeds the supervisory time as a result, an interrupt request signal INT is outputted to an interrupt controller, also, an external reset circuit 1H and an I/O reset circuit 1J are started and an external bus controller and an I/O controller are respectively reset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CPU (Central
DMA for controlling direct memory access (DMA) for directly transferring data between two storage devices without going through a processing unit
The present invention relates to a controller, and more particularly, to a DMA controller having a function of recovering from an abnormal state that occurs when data is transferred in a single address mode.

[0002]

2. Description of the Related Art Conventionally, direct memory access has been widely used in computer systems in order to efficiently transfer data between storage devices. DMA is roughly classified into two types according to the type of the storage device. One is a dual address mode and the other is a single address mode. In the former dual address mode, 2
Data is transferred between memories such as one RAM (Random Access Memory). In the latter single address mode, data is mainly transferred between a memory and a storage medium such as a hard disk.

FIG. 6 is a block diagram showing a conventional DMA controller and its peripheral circuits for executing direct memory access using a single mode address. In single address mode,
When data is transferred between the memory 400 and the hard disk 500, the CPU 600 sets a right to use the main bus 800 as a circuit for performing data transfer, that is, D
Delegate to MA controller 100. Even if a failure occurs in one of the circuits of the DMA controller 100, the external bus controller 200, and the I / O controller 300 during the data transfer process, it is necessary to return the right to the CPU 600. Therefore, the CPU 600
When starting the access to 0 or the hard disk 500, a timer for counting a predetermined monitoring time is started. When the access is not completed within the predetermined time, the CPU 600 determines that an abnormality has occurred, and
The processing for recovering from the abnormal situation, that is, resetting the circuits related to the data transfer, regains the right to use the main bus.

[0004]

However, in the conventional DMA controller, the monitoring time is set uniformly regardless of the type of storage device to be accessed. That is, the monitoring time is long (the operation speed is slow) so that the monitoring time can be used for monitoring access to the memory and also for monitoring access to the hard disk. hard·
It is determined based on the time required for accessing the disk. As a result, there is a problem in accessing the memory that it takes more time than necessary to detect an abnormal state. In addition, a load is imposed on the CPU 600 to monitor whether an abnormality has occurred in each circuit and to reset each circuit when an abnormality occurs. For this reason, there is a problem that the CPU 600 has to play a large role in spite of direct memory access which normally should not involve the CPU.

[0005]

In order to solve the above-mentioned problems, a DMA controller according to the present invention employs the following configuration. <Structure 1> Data transfer between the first storage device and the second storage device having different access times is performed by the first transfer control device for accessing the first storage device and the second transfer device. A DMA controller for controlling using a second transfer control device that accesses a storage device, wherein the first monitoring time is longer than a time required for accessing the first storage device, and the second controller A monitoring time storage circuit for storing a second monitoring time longer than a time required for access to the storage device, and an access when executing access to the first storage device or access to the second storage device An elapsed time measurement circuit for measuring an elapsed time substantially elapsed from the start of the operation, and the elapsed time when executing access to the first storage device or access to the second storage device, Real The first corresponding to the access in the
And a reset circuit that is activated by the comparison circuit and resets the first transfer control device and the second transfer control device. A DMA controller.

<Structure 2> The DMA controller according to Structure 1, further comprising an error determining circuit for determining whether the detection is related to the first monitoring time or the second monitoring time. A DMA controller, wherein a reset circuit resets only the transfer control device determined by the error determination circuit.

<Structure 3> The DMA controller according to Structure 1, further comprising a reset prohibition circuit for setting permission / prohibition of the operation of the reset circuit.
controller.

[0008]

Embodiments of a DMA controller according to the present invention will be described below with reference to the drawings.
Prior to the description of the embodiment, a conventional DMA controller will be described from the viewpoint of clarifying the difference from the conventional DMA controller.

FIG. 7 is a block diagram showing the configuration of the DMA controller. Hereinafter, data transfer in the single address mode will be described. As shown in FIG.
The DMA controller 100 includes a transfer setting register 100
A, a read start address counter 100B, a counter control circuit 100C, and a transfer data number register 100D.

FIG. 8 is a flowchart showing the data transfer operation. Hereinafter, it is assumed that data is transferred from the memory 400 to the hard disk 500 shown in FIG.

Step S100: The CPU 600 confirms that it is in the single address mode,
The transfer setting register 100A is set to indicate that the transfer is a DMA transfer between 0 and the hard disk 500. Also, C
The PU 100 sets the read start address of the memory 400 to:
The value is set in the read start address counter 100B, and the number of data to be transferred (hereinafter, referred to as "the number of data to be transferred") is set in the data number register 100D. Here, it is assumed that 3000h is set as the read start address and 56h is set as the number of transfer data. By these settings, the right to use the main bus 800 is granted from the CPU 600 to the DMA
Move to controller 100. Further, the DMA controller 100 notifies the external bus controller 200 and the I / O controller 300 that the DMA transfer is to be started. Step S110: The DMA controller 100 passes the read start address 3000h set in the read start address 100B to the external bus controller 200.

Step S120: The external bus controller 200 reads data corresponding to the read start address from the memory 400. Here, data 12h
It is assumed that has been read. At the same time as this read timing, the counter control circuit 100C sets the address in the read start address counter 100B to 3001h.
Count up to Step S130: The I / O controller 300 sends a data transfer request signal REQ for requesting data transfer to the DM
Output to A controller 100.

Step S140: In response to the data transfer request signal REQ, the DMA controller 100 converts the data 12h read by the external bus controller 200 into I
Output to the / O controller 300. The I / O controller 200 stores the data 12h in the hard disk 50
Write to 0. Step S150: The I / O controller 200
A data reception completion signal ACK indicating normal reception of data transfer is returned to the MA controller 100. This allows
The transfer of the data 12h corresponding to the address 3000h is completed.

Step S160: When the transfer of 56h data is completed by repeating the above steps, the DMA controller 100 notifies the interrupt controller 700 of an interrupt signal INT indicating that the transfer of all data has been completed. I do. Step S170: In response to the interrupt signal INT, the interrupt controller 700 notifies the CPU 600 of the fact, and the CPU 600 regains the right to use the main bus 800.

As described above, the right to use the main bus 800 is separated from the CPU 600 during data transfer. Should data transfer fail,
Data transfer may not be completed, and as a result, a situation may occur in which the right to use the main bus 800 is not returned to the CPU 600. Therefore, it is necessary to know whether or not an abnormality has occurred while accessing the memory or the hard disk. Therefore, the CPU 600 has a function for monitoring whether or not the access has been completed within a predetermined monitoring time (hereinafter, simply referred to as “monitoring time”) longer than the time required for accessing the storage devices. The timer 600A is activated when starting access to the storage device. Hereinafter, the operation of this monitoring will be described.

FIG. 9 is a time chart showing an operation of monitoring data transfer. As shown in FIG.
A controller 100 outputs a read address of memory 400 and a strobe signal STB indicating that the read address is valid. This strobe signal ST
Immediately after B is output, the CPU 600
Start 0A. After the activation, the timer 600A continues counting up.

Based on these address signal ADRS and strobe signal STB, external bus controller 200
Is the data DATA corresponding to the address ADRS.
Is read from the memory 400. When the data DATA can be read normally, the external bus controller 200 outputs to the interrupt controller 700 an access response signal RDY indicating that the access to the memory 400 has been normally completed. The CPU 600
The access response signal R from the interrupt controller 700
By receiving DY, the timer 600A stops counting up and clears the count value, that is, sets the count value to zero.

In the unlikely event that the external bus controller 200 fails to access the memory 400, the access response signal R
If DY cannot be output, the timer 600A reaches the monitoring time. In that case, the CPU 600
After outputting an operation stop signal ABT for stopping the operation of the MA controller 100 to the DMA controller 100, the state of the main bus 800 and the like is checked, and then the DMA controller 100 and the external bus controller 200 are reset by using the reset signal RST. , I / O controller 300
Reset the controller. When reset,
Each controller initializes an internal register and the like, and can execute data transfer again.

As described above, in the conventional DMA controller, the monitoring time is uniquely determined regardless of the access target, and the monitoring time is counted by the CPU. Therefore, as described above, the CPU spends more time than necessary before detecting an abnormal state.
There is a problem that the load on the device increases.

Therefore, a specific example of the DMA controller according to the present invention is configured and operates as follows. Hereinafter, embodiments of a DMA controller according to the present invention will be described with reference to the drawings.

Embodiment 1 <Configuration of Embodiment 1> FIG. 1 is a block diagram showing the configuration of a DMA controller according to Embodiment 1. In the following description,
The peripheral circuits of the DMA controller in the specific example are referred to using the reference numbers of the conventional peripheral circuits. The DMA controller 1 of the specific example 1 includes a transfer setting register 1A, a read start address counter 1B, a counter control circuit 1C, a transfer data number register 1D, an elapsed time measurement circuit 1E, a monitoring time storage circuit 1F, a comparison circuit 1G, and an external reset circuit. 1H, I
/ O reset circuit 1J.

The configuration and operation of the transfer setting register 1A, read start address counter 1B, counter control circuit 1C, and transfer data number register 1D are shown in FIG.
The transfer setting register 100A, read start address counter 100B, counter control circuit 100
C and the configuration and operation of the transfer data number register 100D.

The elapsed time measuring circuit 1E is a circuit that is permitted to start measuring the elapsed time by the counter control circuit 1C when the access to the storage device is started.
The monitoring time storage circuit 1F is a circuit that stores a time longer than a time required for accessing the storage device as a monitoring time. The comparison circuit 1G compares the elapsed time measured by the elapsed time measurement circuit 1E with the monitoring time stored in the monitoring time storage circuit 1F, and interrupts the interrupt controller 700 when the elapsed time exceeds the monitoring time. This circuit outputs the request signal INT and activates the external reset circuit 1H and the I / O reset circuit 1J. When activated by the comparison circuit 1G, the external reset circuit 1H
The I / O reset circuit 1J is a circuit for resetting the external bus controller 200 and the I / O controller 300, respectively.

Here, the configuration of the monitoring time storage circuit 1F will be described. The monitoring time storage circuit 1F includes a monitoring time register 1F-a for storing a monitoring time, a shift register 1F
-B, the multiplexer 1F-c. A monitoring time for monitoring access to the hard disk 500 is set in the monitoring time register 1F-a. The access time of the hard disk 500 is longer than the access time of the memory 5. Therefore, this monitoring time is too long to be used as a monitoring time for monitoring the memory 400. Therefore, when accessing the hard disk 500, the monitoring time is used as it is, but when accessing the memory 400, the monitoring time is not used as it is, and the shift register 1F-b is used instead of using the monitoring time. Use after shortening to 1/4 etc. Original monitoring time (hereinafter referred to as “hard
Disk monitoring time. " ) Or a monitoring time shortened by half (hereinafter referred to as “memory monitoring time”) is used depending on whether the access target is the memory 400 or the hard disk 500. It depends on whether Therefore, one of the monitoring times is selected by the multiplexer 1F-c based on the signal regarding the access target.

<Operation of Embodiment 1> Hereinafter, the DM of Embodiment 1 will be described.
The operation of the A controller 1 will be described with reference to FIGS. It should be noted that the hard disk 5
Assume data transfer to 00.

<First half of transfer> Step S10: The CPU 600 sets the single address mode and the effect of the DMA transfer from the memory 400 to the hard disk 500 in the transfer setting register 1A in the DMA controller 1. In addition, the CPU 600
The read start address of the memory 400 is set in the read start address counter 1B, and the monitoring time is set in the monitoring time storage circuit 1F. The DMA controller 1
Notifies the external bus controller 200 and the I / O bus controller 300 of the start of the DMA transfer. Thereafter, the right to use the main bus 800 is
Transferred to MA controller 1.

Step S11: As shown in FIG.
The MA controller 1 has a read start address counter 1
The read address ADRS set to B is output to the memory 400 via the external bus controller 200, and at the same time, the strobe signal STB indicating that the output address ADRS is valid is made valid. Step S12: When the DMA controller 1 outputs the read address ADRS and the strobe signal STB,
Immediately, the elapsed time measurement circuit 1E is started. After this,
The elapsed time measuring circuit 1E synchronizes with the clock CLK,
That is, the counting is performed at every rising edge or falling edge of the clock signal.

Step S13: After finishing reading data from the memory 400, the external bus controller 200 outputs an access response signal RDY indicating completion of access to the memory 400 to the DMA controller 1. Step S14: The DMA controller 1 sets the access response signal RDY before the end of the monitoring time for the memory.
Is received, the counter control circuit 1C clears the elapsed time measurement circuit 1E. As a result, the elapsed time measurement circuit 1E does not reach the monitoring time for the memory, so that the comparison circuit 1G does not activate the external reset circuit 1H and the I / O reset circuit 1J. At the same time as this clear operation, the DMA
Controller 1 receives data read from external bus controller 200.

Step S15: DMA controller 1
However, when the access response signal RDY is not received before the memory monitoring time ends, the elapsed time measurement circuit 1
E reaches the monitoring time for the memory. When this is detected,
The comparison circuit 1G includes an external reset circuit 1H and an I / O
In addition to activating the reset circuit 1J, the reset circuit 1J outputs to the interrupt controller 700 a timeout, that is, an interrupt request signal INT indicating that the memory monitoring time has expired.

Step S16: External reset circuit 1H
The I / O reset circuit 1J resets the external bus controller 200 and the I / O bus controller 300, respectively. Step S17: Reception of the interrupt request signal INT, the external reset circuit 1H and the I / O reset circuit 1
By resetting J, CPU 600 regains the right to use the main bus.

<Second half of transfer> Step S18: When read data is received, DMA
The controller 1 makes the strobe signal STB valid again and activates the elapsed time measuring circuit 1E. Thereafter, the elapsed time measurement circuit 1E counts and synchronizes with the clock CLK.
Continue up. Step S19: In response to the data transfer request signal REQ from the I / O controller 300, the DMA controller 1 outputs read data to the I / O controller 300. Further, the I / O controller 300
The data is written to the disk 500. Step S20: The I / O controller 300 outputs an access response signal RDY indicating completion of access to the hard disk 500 to the DMA controller 1.

Step S21: DMA controller 1
Receives the access response signal RDY before the end of the hard disk monitoring time, the counter control circuit 1
C clears the elapsed time measurement circuit 1E. As a result, the elapsed time measurement circuit 1E does not reach the hard disk monitoring time, so the comparison circuit 1G does not activate the external reset circuit 1H and the I / O reset circuit 1J. Step S22: The DMA controller 1
If the access response signal RDY is not received before the disk monitoring time ends, the elapsed time measuring circuit 1E
Reaches the monitoring time. When this is detected, the comparison circuit 1
G activates the external reset circuit 1H and the I / O reset circuit 1J, and the interrupt controller 700
, An interrupt request signal INT indicating that the hard disk monitoring time has expired is output.

Step S23: External reset circuit 1
H and the I / O reset circuit 1J reset the external bus controller 200 and the I / O bus controller 300, respectively. Step S24: Receiving the interrupt request signal INT, the external reset circuit 1H and the I / O reset circuit 1
By the reset by J, the CPU 600 regains the right to use the main bus 800.

<Effects of Embodiment 1> As described above, the DMA controller of Embodiment 1 sets a monitoring time corresponding to an access target, that is, a memory monitoring time,
Also, a monitoring time for the hard disk is set. This eliminates the need to wait for as long a time as monitoring the access to the memory, as in the case of monitoring the access to the hard disk, unlike the conventional case. As a result, even if an error occurs in accessing the memory, the right to use the main bus can be returned to the CPU earlier than in the conventional case. Further, unlike the conventional case, the external reset circuit and the I / O
The signal for resetting the O reset circuit is output not by the CPU but by the DMA controller. As a result, the load on the CPU can be reduced.

The DMA controller of the present invention can be applied to data transfer between various storage devices having different access times. The elapsed time measurement circuit
It is only necessary to have a function of measuring the time required for access by the first transfer control device or the second transfer control device,
The configuration can be realized by software or hardware. The monitoring time storage circuit can store the monitoring time for the memory and the monitoring time for the hardware, respectively.

<< Specific Example 2 >> Hereinafter, a DMA controller of a specific example 2 will be described. The main feature of the DMA controller of the specific example 2 is that the circuit in which the abnormality has occurred is a memory or a hard disk, and only the circuit in which the abnormality has occurred is reset.

FIG. 4 is a block diagram showing the configuration of the DMA controller according to the second embodiment. The main configuration of the DMA controller of the specific example 2 is the same as the configuration of the DMA controller of the specific example 1. Hereinafter, the characteristic circuit will be mainly described.

<Configuration of Specific Example 2> In the DMA controller of specific example 2, an error determination circuit 1K is added to the DMA controller of specific example 1. This error determination circuit 1K
Are read / write signal R / W, strobe signal ST
B and the data transfer request signal REQ. The error discriminating circuit 1K, based on these signals,
0 and the hard disk 500 are currently accessed, whether the access is read or write, and whether an error has occurred during the access.

<Operation of Specific Example 2> Hereinafter, as in the case of Specific Example 1, description will be made assuming that DMA transfer is performed from the memory 400 to the hard disk 500. Memory 400
When the access response signal RDY is not input within the monitoring time for the memory when the access is made, the comparison circuit 1G outputs the interrupt request signal INT to the CPU 600. On the other hand, error determination circuit 1K determines that an error has occurred in the read operation from memory 400 based on the absence of access response signal RDY and the fact that read / write signal R / W indicates a read. . Based on this determination, the error determination circuit 1K activates only the external reset circuit 1H and does not activate the I / O reset circuit 1J. As a result, the external reset circuit 1H resets the external bus controller 200.

Unlike the above case, if the access response signal RDY is not input within the hard disk monitoring time while accessing the hard disk 500,
The comparison circuit 1G outputs the interrupt request signal INT to the CPU 600
Output to On the other hand, based on the absence of the data transfer request signal REQ, and the fact that the read / write signal R / W indicates writing,
It is determined that an error has occurred in the write operation to the disk 500. Based on this determination, the error determination circuit 1K
Only the O reset circuit 1J is activated and the external reset circuit 1
Do not start H. As a result, the I / O reset circuit 1J
Resets the I / O controller 300.

<Effects of the Second Embodiment> As described above, the DMA controller of the second embodiment resets only a circuit in which an abnormality has occurred during operation. As a result, since a circuit that does not need to be reset is not reset, it is possible to avoid wasting power for the reset operation.

It should be noted that a signal input to the error detection circuit can be substituted with such a signal as long as it is a signal useful for determining which transfer control device is to be accessed. .

<< Specific Example 3 >> The DMA controller of the specific example 3 will be described below. The main feature of the DMA controller of the specific example 3 is that the reset inhibit register
This is to inhibit the operation of the external reset circuit 1H and the I / O reset circuit 1J. FIG. 5 is a block diagram illustrating the configuration of the DMA controller according to the third embodiment. The configuration of the DMA controller of the specific example 3 is substantially the same as the configuration of the DMA controllers of the specific examples 1 and 2. Hereinafter, the characteristic configuration will be mainly described.

<Configuration of Specific Example 3> In the DMA controller of specific example 3, a reset prohibition circuit 1L is added to the DMA controller of specific example 1. This reset prohibition circuit 1L is set by the CPU 600 to permit or prohibit the operation of the external reset circuit 1H and the I / O reset circuit 1J at the start of the DMA transfer. According to the setting, when the monitoring time has elapsed, the external reset circuit 1H and the I / O reset circuit 1J perform the conventional operation, that is, the operation of notifying the CPU 600 of only the interrupt request signal INT, or the present invention. , Ie, the operation of notifying the interrupt request signal INT and the operation of resetting the external bus controller 200 or the I / O controller 300.

<Operation of Specific Example 3> Reset Prohibition Circuit 1L
Are the external reset circuit 1H and the I / O reset circuit 1J
Is set to permit the operation of the external reset circuit 1H, the reset inhibit circuit 1L
And activating the I / O reset circuit 1J. Therefore, when the measured elapsed time exceeds the monitoring time, as described above, the comparison circuit 1G outputs the interrupt request signal INT to the CPU, and simultaneously outputs the external reset circuit 1H and the I / O reset circuit 1J. to start. As a result, the external bus controller 200 and the I / O controller 300 are reset.

On the other hand, when the reset inhibit circuit 1L is set to inhibit the operation of the external reset circuit 1H and the I / O reset circuit 1J, the reset inhibit circuit 1L
Prohibits the comparison circuit 1G from activating the external reset circuit 1H and the I / O reset circuit 1J. Therefore, when the elapsed time that has been measured exceeds the monitoring time, the comparison circuit 1G outputs the external reset circuit 1H and the I / O
An interrupt request signal INT is output to the CPU 600 without activating the O reset circuit 1J. Thereby, the CP
U600 is either memory 400 or hard disk 50
0, the external reset circuit 1
H and the I / O reset circuit 1J are reset.

<Effect of Specific Example 3> As described above, the DMA controller of the specific example 3 is different from the specific example 1 or the specific example 2.
And the conventional operation can be selected. As a result, a recovery process when an abnormality occurs, that is,
It is possible to switch between leaving the reset operation to the CPU side and leaving it to the DMA controller side.

The reset prohibition circuit only needs to be able to set the permission or rejection of the reset circuit.
It is possible to use a register or a DIP switch for holding a signal for setting permission / denial.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a DMA controller according to a first embodiment.

FIG. 2 is an operation flowchart of a DMA transfer of a specific example 1;

FIG. 3 is a time chart illustrating a data transfer monitoring operation of a specific example 1;

FIG. 4 is a block diagram illustrating a configuration of a DMA controller according to a specific example 2.

FIG. 5 is a block diagram illustrating a configuration of a DMA controller according to a third embodiment;

FIG. 6 is a block diagram showing a circuit configuration of a conventional DMA controller.

FIG. 7 is a block diagram showing a configuration of a conventional DMA controller.

FIG. 8 is an operation flowchart of a conventional DMA transfer.

FIG. 9 is a time chart showing a conventional data transfer monitoring operation.

[Explanation of symbols]

 1E Elapsed time measurement circuit 1F Monitoring time storage circuit 1G Comparison circuit 1H External reset circuit 1J I / O reset circuit

Claims (3)

[Claims] 1. A data transfer between a first storage device and a second storage device having different access times is performed by a first transfer control device that accesses the first storage device and a second transfer device that accesses the first storage device.
A second transfer control device that accesses the first storage device, wherein the first transfer time is longer than the time required to access the first storage device; A monitoring time storage circuit for storing a second monitoring time longer than a time required for accessing the storage device; and performing access to the first storage device or access to the second storage device. An elapsed time measuring circuit that measures an elapsed time substantially elapsed from the start of the access, and the elapsed time when executing access to the first storage device or access to the second storage device, A comparison circuit for detecting that the first monitoring time or the second monitoring time corresponding to the access being executed has been reached; and a first transfer activated by the comparison circuit and the first transfer A DMA controller comprising a reset circuit for resetting a control device and a second transfer control device. 2. The DMA controller according to claim 1, further comprising an error determination circuit that determines whether the detection is related to the first monitoring time or the second monitoring time. A DMA controller, wherein a reset circuit resets only the transfer control device determined by the error determination circuit. 3. The DMA controller according to claim 1, further comprising a reset prohibition circuit for setting whether or not the reset circuit operates.