JPH11143774A - Cache control mechanism - Google Patents

Abstract

(57) [Problem] To provide a cache control mechanism for improving performance by performing cache control according to a memory access pattern. Kind Code: A1 A cache control mechanism in a processor having a cache and one or more registers, and using the registers to specify addresses of a cache, a main memory, and the like, wherein cache control information is set in advance in correspondence with the registers. When the address is specified using the register and when the value of the register is updated, the cache control is performed according to the set cache control information. For example, when the cache control information corresponding to the register is an address mask, as shown in the figure, X, which is a part of the cache column address, and P and M of the address mask are input to the replacement circuit, and X is changed to Y. Has been replaced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cache control mechanism for a processor in a computer system.

[0002]

2. Description of the Related Art There are the following problems (1) to (3) in the cache of a processor, and in the conventional cache configuration and cache control mechanism, various measures have been taken to solve the respective problems. I have. (1) There is data to be allocated to the same cache column, and a conflict occurs among the plurality of data,
When new data is allocated to a cache column, required data that has already been allocated to the cache column is evicted from the cache, and the performance of memory access is reduced. In order to solve this problem, the conventional technology increases cache associativity, uses a separate cache for each application, switches it for each processor mode, uses it explicitly, and solves thrashing. In order to solve this problem, we have a temporary buffer with high associability.

(2) When the data to be accessed is not in the cache, the latency of the main memory access is longer than that of the cache, so that a waiting time of the processor occurs.
Regarding this problem, in the related art, there is a prefetch that caches data earlier than actually loading the data. The prefetch includes a software control prefetch that is explicitly performed by designating an address in a program, and a hardware prefetch that is performed when hardware detects address continuity and other conditions. An example of the latter is the Hewlett-Packard journal 1996
Hewlett-Packard Microprocessor PA-7200 has an instruction to update the register used for addressing after memory access to the instruction set. The hardware determines that prefetch is possible, and performs prefetch using the value of the register as an address.

(3) A storage device and a device other than the storage device (for example, an I / O device) are mapped in the address space.
However, if a value read from a device other than a storage device is cached, correct operation may not be expected. If it is necessary to immediately reflect the result of the store, the store-in operation must not be performed. With regard to this problem, in the conventional technology, for each unit (page) managed by the memory management mechanism, the attribute of whether or not the cache can be cached at the time of loading and the store-through operation or the store-in operation at the time of a store cache hit are determined. It has an attribute of whether to perform a write allocate operation or a write no allocate operation when a store cache miss occurs, and correct cache control can be performed by following this attribute.

[0005]

The conventional cache configuration and cache control mechanism have the following problems. (1) In a cache configuration in which the contention is reduced by increasing the associativity of the cache, the number of bits for simultaneous reading from the cache increases. Operating frequency is limited. Further, the area on the chip required to realize a cache having the same capacity also increases. Also, it is not possible to cope with a case where other data is evicted due to cache overflow of large-scale data. Configurations with separate caches for different uses are less versatile. Even a configuration having a temporary buffer with high associativity to eliminate thrashing cannot cope with a case where large-scale data causes cache overflow and other data is evicted.

(2) The number of instructions increases when software-controlled prefetch is performed. Hardware control prefetches required data much faster than it is actually used,
In addition, it is difficult to reduce unnecessary issuance of prefetch. In the example of the Hewlett-Packard Microprocessor PA-7200, the prefetch valid condition that can be detected by hardware is limited to the execution of a specific instruction, and the address to be prefetched is also the value of the register after the instruction is executed. Limited to For this reason, performance degradation may be caused by excessive cache reference,
Large latencies cannot be effectively concealed.

(3) Cache control according to the cache attribute of each page can guarantee correct operation, but is not necessarily advantageous in performance.

For example, it is effective to always cache data of a page having a cacheable attribute, which is effective for access to continuous addresses, but reads data not to be accessed for stride and discrete addresses from a main memory. Unnecessary data transfer increases memory access traffic. Although it is effective to reduce the memory access traffic to not immediately write to the main storage for a page with the store-in attribute, it is necessary to control coherence with other devices sharing the main storage. Requires a flush of the cache and has a large overhead.
Also, when a store for a page with a write allocate attribute causes a cache miss, caching the line containing that data is effective in reducing memory access traffic when the processor loads or stores the line, but immediately If the line is flushed, the traffic will increase,
When memory copy of large-scale data is performed, there is a problem that useless data enters the cache and other data is evicted.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a cache control mechanism which has a high operating frequency and is suitable for a large-capacity cache configuration and which has means for avoiding competition of a plurality of data for the same cache column and performance degradation due to cache overflow of large-scale data. Is to provide. It is another object of the present invention to provide a cache control mechanism having hardware-controlled prefetch means suitable for a processor having a main memory having a relatively large latency and capable of supporting various memory access patterns. Still another object of the present invention is to provide a cache control mechanism having means for obtaining optimum main storage access performance according to load and store access patterns.

[0010]

In order to achieve the above object, the present invention provides a cache in a processor having a cache and one or more registers, and using the registers to specify addresses of a cache, a main memory, and the like. A control mechanism having cache control information that can be set in advance in correspondence with the register, and performing an address designation using the register and, when the value of the register is updated, performing cache control according to the cache control information. To do.

[0011] Further, there is provided means for having an address mask as the cache control information, and replacing a part of an address used for selecting a column of the cache with an address mask corresponding to a register for specifying an address when the processor accesses the cache. The cache is accessed by the address replaced by the means.

The cache control information may include a set associative cache row number.
When the processor needs to replace the cache line, the processor is provided with a means for replacing the cache line with the cache line of the row number corresponding to the register for which the address is specified.

The cache control information includes a prefetch valid condition, and when the value of the register is updated, a detecting means for detecting the establishment of the prefetch valid condition corresponding to the register is provided. In this case, data is read from the main memory to the cache using the updated register value as a start address.

The cache control information has a prefetch index, and the value of the register is updated. When the detection means detects that the prefetch valid condition corresponding to the register is satisfied, the updated value of the register is And the prefetch index corresponding to the register is used as a start address to read data from the main memory into the cache.

Further, the cache control information has a prefetch size, the value of the register is updated, and when the prefetch valid condition corresponding to the register is satisfied by the detecting means, the value of the updated register is Is used as a start address, and data of a prefetch size corresponding to the register is read from the main memory into the cache.

Further, the cache control information has a prefetch index and a prefetch size, and the value of the register is updated. When the detection means detects that a prefetch valid condition corresponding to the register is satisfied, The sum of the value of the register and the prefetch index corresponding to the register is used as a start address, and data corresponding to the prefetch size corresponding to the register is read from the main memory to the cache.

Further, the cache control information has a load operation mode, and when the processor performs a load operation, whether or not to perform a line transfer to the cache at the time of a cache miss in accordance with the load operation mode corresponding to the register for specifying an address. Is provided.

The cache control information has a store operation mode. When the processor performs a store operation, a store-in operation and a store-through operation are selected when a cache hit occurs in accordance with a store operation mode corresponding to a register for specifying an address. Means are provided for selecting a write allocate operation and a no-write allocate operation when a cache miss occurs.

The cache control information includes a load operation mode and a store operation mode. When the processor performs a load, a line transfer to the cache is performed at the time of a cache miss in accordance with the load operation mode corresponding to the register for specifying an address. Or not, and when the processor does the store,
According to a store operation mode corresponding to a register for which an address is specified, a means for selecting a store-in operation and a store-through operation when a cache hit occurs, and a means for selecting a write allocate operation and a no-write allocate operation when a cache miss occurs.

The cache control information has a copy, and when the cache control information is set, a copy of the cache control information is also set at the same time, and the value of another register or the value of another register is used for the register. When the calculated operation result is written, the cache control information corresponding to the register is updated based on the reserved cache control information. When the value read from the cache or main memory is written to the register, the reserved cache control information is updated. The control information is set again as cache control information corresponding to the register.

[0021]

Embodiments of the present invention will be described below in detail. FIG. 1 is a flowchart showing an embodiment of the operation of the present invention. FIG. 9 is a flowchart showing details of step 155 in the flowchart of FIG. 1, and FIGS. 13 and 14 are flowcharts showing details of step 120 in the flowchart of FIG. FIG.
8 is a schematic block diagram showing a configuration of a processor and a main memory according to the present invention, and FIG. 19 is a list of cache control information that the processor of FIG. 18 has for registers. FIG. 2 is a block diagram showing a part of the configuration of the conventional cache control mechanism, and shows that when accessing the cache, a column of the cache is selected using a part of the address. FIG. 3 is a block diagram showing a configuration when the mechanism of the present invention that operates based on the address mask of FIG. 19 is applied to the cache control mechanism of FIG. FIG. 4 is a truth table showing an example of a logical operation of the replacement circuit of FIG. 3, and FIG. 5 is a schematic diagram showing an example of cache control enabled when the replacement circuit shown in the truth table of FIG. 4 is used. It is.

FIG. 6 is a block diagram showing a part of the configuration of a conventional cache control mechanism. If a result of accessing a cache having a set associative structure is a miss, the LRU information of the column is used as a basis. This indicates that a row to be replaced is determined. FIG. 7 is a block diagram showing a configuration when the mechanism of the present invention that operates based on the row numbers shown in FIG. 19 is applied to the cache control mechanism of FIG.
FIG. 8 is a block diagram showing the configuration of an embodiment of the present invention that operates based on the prefetch valid condition, prefetch index, and prefetch size shown in FIG. FIG.
9 is a table showing an example of the prefetch valid condition in FIG. 8, and FIG. 9 is a flowchart showing the operation of FIG.

FIG. 11 is a block diagram showing a part of the configuration of a conventional cache control mechanism. In loading or storing, a cache attribute for each page is read and cache control is performed based on the read attribute. . FIG. 12 is a block diagram showing a configuration in which the mechanism operating based on the load operation mode in FIG. 19 and the mechanism of the present invention operating based on the store operation mode are applied to the cache control mechanism in FIG. FIG. 13 and FIG. 14 are flowcharts showing the operation of FIG. FIG. 15 is a block diagram showing a partial configuration of an embodiment of the cache control mechanism of the present invention. FIG.
6 and 17 are diagrams showing the operation of FIG.

In FIG. 18, the processor 10 has one or more registers 200, and has cache control information corresponding to each register 200. Then, the value of the register 200 is updated based on the result of the instruction execution. When the processor 10 needs to access the cache 210 or the main memory 50 when executing an instruction, the processor 10 specifies an address using the register 200. The processor 10 has a control device 30, and the control device 30
Has a cache control mechanism 70, and the cache control mechanism 70
The processor 10 operates based on the cache control information 1500 corresponding to each register 200 when the processor 10 updates the value of the register 200 and specifies an address using the register 200. The cache control information 1500 can be set by software.
Each of the 1500s is individually configurable.

FIG. 2, FIG. 3, FIG. 6, FIG. 7, FIG.
The address calculation circuit 201 calculates an address based on the value of the register 200. 2, 6, and 7, a part of the address obtained by the address calculation circuit 201 is used as a cache column address 202 for column selection when accessing the cache 210. In FIG. 3, the replacement circuit 310 replaces a part of the same address with the address mask 300 to replace the cache column address 2.
02. The address mask 300 includes a P field 301 and an M field 302, and the logical operation of the replacement circuit 310 follows the truth table 400. In FIG. 6 showing a conventional mechanism,
The replacement row selection circuit 600 determines a replacement row based on the LRU information 610 read from the cache at the time of a cache miss. In FIG. 7 showing the mechanism of the present invention, the replacement row selection circuit 710 determines a row to be replaced based on the LRU information 610 and the row number 700 read from the cache at the time of a cache miss. In FIG. 8, a prefetch control circuit 890 performs prefetch when the condition detection circuit 810 detects that the prefetch enable condition 800 is satisfied. In the prefetch valid condition 800, each condition listed in the example 1000 of the prefetch valid condition in FIG. 10 can be individually set.
The condition satisfaction detection circuit 810 includes, among the set conditions,
If any one of the conditions is satisfied, the condition detection is detected and reported to the prefetch control circuit 890.

In FIGS. 11 and 12, another part of the address obtained by the address calculation circuit 201 is used as a page selection address 1110 for page selection when accessing the page table 1100. FIG. 11 showing a conventional mechanism.
In, the load / store control circuit 1150 determines the load / store operation based on the page cache attribute 1130 read from the page table. In FIG. 12 showing the mechanism of the present invention, the load / store control circuit 1250 has a cache attribute 1130 of the page read from the page table.
The load / store operation is determined based on the load operation mode 1200 and the store operation mode 1220.

In FIGS. 15 and 17, the register 200 has cache control information 1500 and a cache control information copy 1510 as corresponding cache control information. When setting cache control information 1500 with software,
At the same time, the same content is set in the copy cache control information 1510. In FIG. 16, a register 200 is a register 160
Updated based on 0 value.

Next, based on the flowcharts of FIGS. 1, 9, 13, and 14, the truth table of FIG. 4, the schematic diagram of FIG. 5, the table of FIG. 10, and the list of FIG. 7, 8 and 1
2, FIG. 15, FIG. 16, FIG. 17, and FIG. 18 will be described. In the flowchart of FIG. 1, first, the processor 10 executes an instruction (step 100). This instruction is a memory access instruction for specifying an address using the register 200 (step 105), and an address mask 300 corresponding to the register 200 shown in FIG. 3 is set (step 11).
0), the address calculation circuit 201 registers
4 (in the case of the example of FIG. 4, consisting of three bits of X (0), X (1), and X (2)), the replacement circuit 310 M field 301 (M
In the example of FIG. 4, M (0), M (1), and M (2) consist of three bits) and the P field 302 (P is P (0), P (0)
(1), a part of the address replaced based on the truth table 400 shown in FIG. 4 based on the three bits P (2) Y (in the example of FIG. 4, Y (0), Y (1) , Y (2)) (step 115). Here, by changing the contents of the address mask 300 corresponding to each register, data specifying an address using the register can be assigned to another column in the cache 210. In FIG. 4, M (0), Y (0), X (0), and P (0) are upper bits, and M (2), Y (2), X (2), and P (2) are Each is a lower bit. According to such a configuration, for example, as shown in FIG. 5, the cache 210 is stored in the area A501, the area B502, and the area C50.
3. The area D504 can be divided into four areas having different capacities. That is, in the case of the area A501, M = "110", P
= "00-", Y = "00X (2)" according to the truth table of FIG. 4, and in the case of the area B502, M = "111",
P is set to “010”, and according to the truth table of FIG. 4, Y is set to “010”. In the case of the area C503, M is set to “111” and P is set to P.
= "011", Y = "011" according to the truth table of FIG. 4, and in the case of the area D504, M = "100", P
= 100, and Y = 1X (1) X (2) "according to the truth table of FIG. Stack on area A501, area B
Two floating point data arrays in area 502 and area C503, area D504
Can be used, for example, by assigning integer data to each other and eliminating competition between data assigned to different areas.

Next, when load or store is executed,
(Step 120, the detailed flow is less than or equal to step 1300 in FIG. 13. The configuration of the cache control mechanism for that is as shown in FIG. 12.) The load / store control circuit 1250 shown in FIG. If loading (step 1300), the loading operation is performed. If it is a cache hit (step 1305), it is loaded from the cache 210 (step 1305).
310).

If it is a cache miss (step 1305),
A part of the address obtained by the address calculation circuit 201 is referred to the page table 1100 as the page selection address 1110 (step 1315), and the cache attribute 1130 of the page is read. If the cache attribute 1130 is a cacheable attribute (step 1320) and the load operation mode 1200 corresponding to the register 200 is not "not performing line transfer" (step 1325), a line transfer from the main memory 50 to the cache 210 is performed. (Step 1330). If the cache attribute 1130 is not the cacheable attribute (step 1320), or if the load operation mode 1200 corresponding to the register 200 is "do not perform line transfer" (step 1325), the data is loaded from the main memory 50.
No line transfer is performed to the cache 210 (step 133
Five).

According to such a configuration, for example, when accessing a discrete address, it is necessary to set the load operation mode 1200 so that line transfer to the cache is not performed at the time of a cache miss, so that it is included in the same line. You can prevent the transfer of data without the data. Also, when performing access to a continuous address, a load / store control circuit that can transfer necessary data to the cache 210 at a time by setting the line operation to the cache 210 in the case of a cache miss in the load operation mode 1200 In step 1250, if the instruction is a store (step 1300), a store operation is performed (step 1400).
If it is a cache hit (step 1405), a part of the address obtained by the address calculation circuit 201 is referred to the page table 1100 as the page selection address 1110 (step 1410).
Then, the cache attribute 1130 of the page is read. The cache attribute 1130 is the store-in attribute (step 141
5) If the store operation mode 1220 corresponding to the register 200 is store-in (step 1420), a store-in operation is performed to write to the cache 210 but not to the main memory 50 (step 1425). Cache attribute 1130
Is not a store-in attribute (step 1415) or register 20
If the store operation mode 1220 corresponding to 0 is not store-in (step 1420), a store-through operation of writing data to the main memory 50 together with the cache 210 is performed (step 1430).

If it is a cache miss (step 1405),
A part of the address is referred to the page table 1100 as the page selection address 1110 (step 1450), and the cache attribute 1130 of the page is read. Cache attribute 1130 is the write allocate attribute (step 1455), and register 20
If the store operation mode 1220 corresponding to 0 is a write allocate (step 1460), the cache 210
Then, a write allocate operation for writing to the cache 210 is performed after the line transfer (step 1465). The cache attribute 1130 is not the write allocate attribute (step 1455), or the store operation mode 12 corresponding to the register 200
If 20 is not a write allocate (step 1460), a write no allocate operation of writing only to the main memory 50 is performed.
(Step 1470).

According to such a configuration, for example, when performing a memory copy or the like, the store operation mode 1220 is set with the store-through and no-write allocate operations, thereby reducing the coherence control overhead and eliminating the allocate operation overhead. And other data is cached
You can avoid being kicked out of 210. Also, when accessing non-shared data or data that is not frequently updated or referred to by another processor, the memory access traffic can be reduced by setting the store-in and write-allocate operations in the store operation mode 1220.

If a cache miss occurs when executing a load or store, the cache line may be replaced (step 125). That is, the above-mentioned step 1330
In the case of `` performing a line transfer from the main storage to the cache 210 '' in the above, or the case of `` performing the line allocation from the main storage to the cache 210 and then performing a write allocate operation to write to the cache 210 '' in the above-mentioned step 1465 When valid data is cached in the cache line of the line transfer destination or the cache line of the write allocate destination, the cache line is replaced. At this time, the replacement row determination circuit shown in FIG.
710, if the row number 700 corresponding to the register 200 is set (step 130), the row of the row number 700 is replaced (step 135), and if the row number 700 is not set (step 130), LR read from cache 210
Determine the Row to be replaced based on the U information (Step 14
0). Here, by changing the content of the corresponding row number for each register, it is possible to selectively assign data specifying an address using the register to a specific row in the cache 210. For example, in numerical operations, when accessing a continuous address of specific large-scale data, cache overflow causes other data to be cached.
It can be evicted from 210, but by assigning that data to a specific row, other data is cached.
It can prevent you from being kicked out of 210.

When the value of the register 200 is updated as a result of the execution of the instruction (step 145), the condition satisfaction detection circuit 810 determines whether the prefetch valid condition 800 corresponding to the register 200 is satisfied (step 150). ), And notifies the prefetch control circuit 890. Upon receiving the notification from the condition satisfaction detection circuit 810, the prefetch control circuit 890 starts prefetch (step 155). The detailed flow of Step 155 is Step 910 and subsequent steps shown in FIG. In the example of FIG. 8, a 4-bit value is set in the prefetch validity condition 800. Also, an example of the prefetch valid condition in FIG. 10 (1000)
Shows a prefetch valid condition that occurs. For example, the 4-bit value of the prefetch enable condition 800 is "1000"
At this time, if the prefetch valid condition of reference numeral 1010 corresponding to the leftmost bit of the 4-bit value has occurred, the output of the condition satisfaction circuit 810 becomes true. Also, the 4-bit value of the prefetch valid condition 800 is "0100",
At this time, if the prefetch valid condition of reference numeral 1020 corresponding to the second bit from the left of the 4-bit value has occurred, the output of the condition satisfaction circuit 810 becomes true. If the 4-bit value of the prefetch valid condition 800 is “0010” and the prefetch valid condition of the reference numeral 1030 corresponding to the third bit from the left of the 4-bit value is generated, the condition The output of the establishment circuit 810 is true. If the 4-bit value of the prefetch valid condition 800 is "0001" and the prefetch valid condition of reference numeral 1040 corresponding to the rightmost bit of the 4-bit value is generated at this time, the condition satisfaction circuit The output of 810 is true. However, the 4-bit value of the prefetch valid condition 800 is "1000".
If the prefetch valid condition of reference numeral 1020 corresponding to the second bit from the left of the 4-bit value has occurred, the output of the condition satisfaction circuit 810 becomes false. The prefetch valid condition 8004 bit value is "1111". At this time, if any of the prefetch valid conditions denoted by reference numerals 1010, 1020, 1030, and 1040 has occurred, the output of the condition satisfaction circuit 810 is true. Become. However, when the prefetch valid condition 8004 bit value is “0000”, reference numerals 1010, 1020, 1030, and 1040
Even if any of the prefetch enable conditions for
The output of the condition satisfaction circuit 810 is false.

As for the prefetch operation, first, the prefetch size 850, the size holding means 855, and the counter 860
And comparator 880, prefetch index 820 and adder 83
The operation of the configuration including 0 and the start address holding means 840 will be described, and then other configurations will be described. When the prefetch starts, the counter 860 is cleared to 0.
(Step 910) The value of the prefetch size 850 is held in the size holding means 855 (Step 915). The adder 830 calculates the sum of the value of the register 200 and the value of the prefetch index 820 and sets the sum as a start address.
It is held at 840 (step 920). The value of the counter 860 is compared with the value of the size holding means 855 (step 925).
The sum of the values of 0 is obtained as the prefetch address, and the transfer of the data in the main memory 50 corresponding to the prefetch address to the cache line of the cache 210 corresponding to the prefetch address is started (step 930).
Then, if the value of the size holding means is positive, the counter is incremented by one.
If it is negative, subtract 1 from the counter (step
935, step 940, step 945), and return to the counter and size comparison (step 925).

According to such a configuration, for example, "when a value read from the cache or the main memory is written" 1010 of the prefetch valid condition 800 corresponding to the register storing the pointer variable in the C language is valid. By doing so, the operation can be sped up. Also, for example, when the main memory 50 is accessed for a continuous address in the inner loop of the double loop, and the base address is updated by the size of the area accessed in one inner loop in the outer loop, The prefetch validity condition 800 corresponding to the register 200 storing the address, "when the immediate value is added to or subtracted from the register value and written back to the original register" 1020 is valid, and the prefetch index 820 and prefetch size 850 are set to 1 By setting the size of the area to be accessed in the inner loop, the main memory access latency for one inner loop can be hidden. Naturally, by setting the prefetch index 820 to a multiple of the size of the area accessed in one inner loop, it is possible to hide the latency of several times of one inner loop. Also, for example, in the prefetch enable condition 800 corresponding to the program counter, the immediate value is added to the value of the register, the value is written back to the original register, the value ignoring the lower N bits of the original value, and the lower N bits of the result value If the value ignoring is different, "1030 is valid and the prefetch size 850 is 2
By setting to the Nth power, the penalty at the time of a code cache miss can be reduced. Also, for example, the prefetch validity condition 800 corresponding to a certain register, “when the value of the address register changes due to execution of an instruction to update the address register simultaneously with main memory access” 1040 is made valid, and the prefetch index 820 is set to an appropriate size. By setting to the above, Hewlett
Similar to the Hewlett-Packard Microprocessor PA-7200 shown on page 30 of the t-Packard journal, February 1996, it can be prefetched without increasing the number of instructions, and it is much larger than the known technology. The storage access latency can be hidden.

In the above configuration, only the prefetch address counter is provided instead of the start address holding means 840, the counter 860 and the adder 870, and the size holding means 85
A configuration having prefetch end address holding means instead of 5 is also possible. In the case of this configuration, the sum of the value of the register 200 and the value of the prefetch index 820 is set in the prefetch address counter, and the sum of the value of the register 200, the value of the prefetch index 820, and the prefetch size is set in the prefetch end address holding means. . Then, the prefetch address counter is incremented (or decremented) while the prefetch is being performed, and the prefetch ends when the value of the prefetch address counter matches the value of the prefetch end address holding means.

In the above-described configuration, a configuration in which some elements are omitted by limiting functions is also possible. The prefetch size 850 can be omitted by limiting the value to 1 or a fixed multiple of the size of the cache line. The prefetch index can be omitted by limiting the value to 0 or a fixed multiple of the cache line size.

When the value of the register 200 is updated by the value read from the cache 50 or the main memory 210,
(Step 160), the preset cache control information 1510 shown in FIG. 15 is reset to the cache control information 1500 (Step 165). In addition, the register 200 shown in FIG.
The value of other register 1600 or register 1600 as shown in
When the operation result using the value of
The reserved cache control information 1610 corresponding to 00 is read and written to the cache control information 1500 (step 1).
70).

[0041]

According to the present invention, cache control according to a memory access pattern, which has been conventionally difficult, can be performed by performing cache control in accordance with cache control information corresponding to a register. Also, by accessing a cache by replacing a part of an address used for selecting a column of a cache with an address mask corresponding to a register used for specifying an address, only a part of the columns of the cache determined by the address mask is used. Therefore, by changing the address mask for each data, it is possible to eliminate contention of a plurality of data for the same column, and the number of bits read from the cache at the same time is smaller than when the number of rows is increased in the related art. It is possible to increase the speed.Also, a memory with a small bit width and a large word length can be used as the memory constituting the cache, so that the amount of wiring required to realize a cache of the same capacity can be reduced. is there. Also, by replacing the cache line of the row number corresponding to the register used for address specification, a part of the rows of the cache determined by the row number is selectively used, so that the specific large-scale data is stored in the specific row. By allocating numbers exclusively, it is possible to prevent cache overflow due to large-scale data from eviction of other data. Also, the data is read into the cache with the updated register value as the start address only when the prefetch valid condition is satisfied by the prefetch valid condition corresponding to the register used for address specification, so that the prefetch valid condition is appropriately set. Data can be read into the cache without adding a prefetch instruction. In addition, the prefetch validity condition and prefetch index corresponding to the register used for address specification make it possible to read data into the cache using the sum of the updated register value and prefetch index as the start address only when the prefetch validity condition is satisfied. By appropriately setting the conditions and the prefetch index, data can be read into the cache sufficiently sooner than actually used without adding a prefetch instruction. In addition, the prefetch validity condition and prefetch size corresponding to the register used for address specification determine that the prefetch validity condition is satisfied. By appropriately setting the condition and the prefetch size, necessary data can be read into the cache without adding a prefetch instruction. Only when the prefetch valid condition is satisfied, the sum of the updated register value and the prefetch index is used as the start address, and only the prefetch valid data corresponding to the register used for address specification is used as the start address. Is read into the cache, and by appropriately setting the prefetch valid condition, the prefetch index, and the prefetch size, necessary data can be read into the cache sufficiently quickly without adding a prefetch instruction, as compared with actually using the data. Also, according to the load operation mode corresponding to the register used for addressing,
It is possible to select whether or not to perform line transfer to the cache at the time of a cache hit and cache miss, respectively.Therefore, by setting the line transfer not to be performed for access to discrete data, unnecessary data transfer can be eliminated. it can. In addition, according to the store operation mode corresponding to the register used for address designation, a store-in operation and a store-through operation at the time of a cache hit are selected, and a write allocate operation and a no-write allocate operation at the time of a cache miss are selected. By setting a store-through operation for access to shared data that requires frequent coherence control with other processors or other devices to be shared, cache flush is not required and coherence control overhead can be reduced. In addition, when performing a memory copy, by setting a no-write allocate operation, the overhead of the allocate operation can be eliminated, and other data can be prevented from being evicted due to useless data entering the cache. If strike It is possible to reduce the traffic of memory access by setting the in and write allocate operation. Also, since the cache control information corresponding to the register is automatically set as the reserved cache control information according to the source of the value of the register, it is possible to suppress an increase in the number of instructions for cache control.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an embodiment of the operation of the present invention.

FIG. 2 is a block diagram showing a part of the configuration of a conventional cache control mechanism.

FIG. 3 is a block diagram showing a configuration when a replacement circuit that operates based on an address mask is applied to FIG. 2;

FIG. 4 is a truth table showing a logical operation example of the replacement circuit in FIG. 3;

FIG. 5 is a schematic diagram showing an example of cache control enabled when the cache control mechanism of FIG. 3 is used.

FIG. 6 is a block diagram showing a part of the configuration of a conventional cache control mechanism.

FIG. 7 is a block diagram showing a configuration when the replacement row determination circuit is applied to FIG. 6;

FIG. 8 is a block diagram illustrating a configuration of an embodiment of a cache control mechanism that performs prefetch control.

FIG. 9 is a flowchart showing the operation of the cache control mechanism of FIG. 8;

FIG. 10 is a diagram illustrating an example of a prefetch valid condition.

FIG. 11 is a block diagram showing a part of the configuration of a conventional cache control mechanism.

FIG. 12 is a block diagram illustrating a part of a configuration of a cache control mechanism to which a load operation mode and a store operation mode are applied;

FIG. 13 is a flowchart showing an operation related to loading in the configuration of FIG. 12;

FIG. 14 is a flowchart showing an operation relating to a store in the configuration of FIG. 12;

FIG. 15 is a block diagram showing a relationship between a register, cache control information, and a copy of cache control information according to the present invention.

16 is a diagram illustrating an operation when a result of an operation is written in the register of FIG. 15;

17 is a diagram illustrating an operation when load data is written in the register of FIG. 15;

FIG. 18 is a schematic block diagram showing a configuration of a processor and a main storage according to the present invention.

FIG. 19 is a diagram showing a list of cache control information in FIG. 18;

[Explanation of symbols]

10 Processor 30 Controller 50 Main Memory 70 Cache Control Mechanism 200 Register 202 Cache Column Address 210 Cache 300 Address Mask 310 Replacement Circuit 700 Row Number 800 Prefetch Valid Condition 810 Condition Satisfaction Detection Circuit 820 Prefetch Index 850 Prefetch Size 890 Prefetch Control Circuit 1200 Load Operation mode 1220 Store operation mode 1500 Cache control information 1510 Reserved cache control information reset at the time of loading

Claims (7)

[Claims] 1. A cache control mechanism in a processor having a cache and one or more registers, and using the registers to specify an address of a cache, a main memory, or the like, the cache control mechanism comprising: A cache control mechanism having register correspondence, wherein cache control is performed in accordance with the cache control information when address designation is performed using the register and when the value of the register is updated. 2. The cache control mechanism according to claim 1, further comprising an address mask as said cache control information,
Means for replacing a part of an address used for selecting a column of a cache with an address mask corresponding to a register for specifying an address when the processor accesses the cache, and accessing the cache by the address replaced by the means; A cache control mechanism, characterized in that: 3. The cache control mechanism according to claim 1, wherein the cache control information has a row number of a cache in a set associative configuration, and corresponds to a register for specifying an address when the processor needs to replace a cache line. A cache control mechanism comprising means for replacing a cache line of a row number to be executed. 4. The cache control mechanism according to claim 1, further comprising a prefetch valid condition as said cache control information, and detecting, when the value of the register is updated, a satisfaction of the prefetch valid condition corresponding to the register. A cache control mechanism for reading data from a main memory into a cache using the updated register value as a start address when the establishment is detected by the means. 5. The cache control mechanism according to claim 4, wherein said cache control information has a prefetch index and a prefetch size, and a value of a register is updated. When the data is detected in the above, the data of the prefetch size corresponding to the register is read from the main memory to the cache using the sum of the updated register value and the prefetch index corresponding to the register as a start address. Cache control mechanism. 6. The cache control mechanism according to claim 1, wherein the cache control information includes a load operation mode and a store operation mode, and when the processor performs a load operation, the processor operates in accordance with a load operation mode corresponding to a register for specifying an address. Select whether or not to perform line transfer to the cache at the time of a cache miss. When the processor performs a store, select the store-in operation and store-through operation at the time of a cache hit according to the store operation mode corresponding to the register that specifies the address. And a means for selecting between a write allocate operation and a no-write allocate operation when a cache miss occurs. 7. The cache control mechanism according to claim 1, further comprising a copy of said cache control information, wherein said copy of said cache control information is simultaneously made when setting the cache control information. When a value of another register or an operation result using a value of another register is written to the register, the cache control information corresponding to the register is used as a basis based on the cache control information corresponding to the other register. And when the value read from the cache or main memory is written to the register, the reserved cache control information is set again as cache control information corresponding to the register.