JPH11146021A - Signal transmission circuit, cmos semiconductor device and printed circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the signal transmission characteristic of a signal line formed in a large scale integrated circuit with a large capacitance of a capacitive component due to presence of many driven circuits connecting to the integrated circuit or a long signal line formed in the large scale integrated circuit. SOLUTION: An additional circuit that provides a medium point voltage of a power supply voltage of a drive circuit DR and a driven circuit RC and has a low output impedance connects to a signal line LIN to keep a voltage of the signal line LIN to be a medium point voltage of the power supply voltage. Then a drive signal outputted from the drive circuit DR is excited with a small amplitude around the medium point voltage (threshold voltage of the driven circuit RC) and the driven circuit RC is driven by the driving signal with the limited small amplitude.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission circuit,
More particularly, the present invention relates to a signal transmission circuit having an additional circuit, a CMOS semiconductor device, and a circuit board.

[0002]

2. Description of the Related Art As the scale of a semiconductor integrated circuit device increases, the shape of a semiconductor chip for forming the same increases.
Wiring lengths of signal lines formed inside (for example, signal lines for distributing clocks, signal lines forming bus lines, and the like) tend to be long.

FIG. 1 shows various forms of signal lines formed in an integrated circuit device. Large-scale integrated circuit devices have approximately one side
It is formed on a square semiconductor chip CP of about 5 to 20 mm. Therefore, the line length of the signal line LIN formed inside is long and often reaches 20 mm or more.

A shown in FIG. 1 shows a wiring configuration in which the line length of a signal line LIN between a drive circuit DR and a driven circuit RC is 100 μm or less. B shows the wiring form when the line length is 20 mm or more. C indicates a wiring configuration when a large number of driven circuits RC are connected to the signal line LIN, such as a bus line or a clock distribution line.

FIG. 2 shows an electrical equivalent circuit of each of these wiring forms A, B and C.

A wiring capacitance CL is generated on a signal line LIN connecting the driving circuit DR and the driven circuit RC, and an input capacitance CG is formed at an input terminal of the driven circuit RC. The wiring capacitance CL and the input capacitance CG have different values depending on the wiring configurations A, B, and C. The input capacitance CG has a value proportional to the number of the driven circuits RC connected, and the wiring capacitance CL has a value proportional to the length of the signal line LIN.

[0007] Looking at the wiring configurations A, B and C from this viewpoint,
The wiring form A has the smallest capacitance value connected to the signal line LIN, and then the wiring form B and the wiring form C have larger capacitance values in this order. Big differences occur.

[0008]

FIG. 3 shows a step response waveform when a step pulse is applied to the signal lines of these various wiring forms A, B and C. 3A shows a step response waveform of the wiring configuration A shown in FIG. 1, FIG. 3B shows a step response waveform of the wiring configuration B shown in FIG. 1, and FIG. 3C shows a step response waveform of the wiring configuration C shown in FIG. As is apparent from FIG. 3, the delay of the rising of the step waveform is hardly seen in the line length of the wiring configuration A shown in FIG. 1, but the step waveforms become large in the wiring configurations B and C, and a large response delay occurs. I do. In particular, the tendency appears remarkably in the wiring form C in which the signal line LIN is long and a large number of driven circuits RC are connected.

FIG. 4 shows a pulse response waveform. Wiring form A
Although the input pulse is almost normally transmitted to the driven circuit RC, the pulses are hardly transmitted to the driven circuit RC in the wiring configurations B and C. That is, it is understood that a pulse having a narrow pulse width cannot be transmitted through a signal line having a large capacitance. This is a factor that hinders the enlargement of the semiconductor chip.

The same phenomenon applies to a signal line that connects integrated circuit elements mounted on a circuit board (printed wiring board).

In order to increase the degree of integration of semiconductor integrated circuit elements, the processing dimensions of elements such as transistors have been reduced.
The line width of the wiring must be formed thin. At this point, the capacitance value generated in the signal line is considered to be small. However, since the line width is reduced and the thickness of the insulating layer is also reduced, the wiring capacitance C of the signal line is consequently reduced.
L and the input capacitance CG of the driven circuit RC do not greatly decrease even if the formation area is reduced to improve the degree of integration.

On the other hand, to solve this inconvenience, for example, FIG.
In the circuit for distributing clock pulses to a large number of circuit areas MAP as shown in FIG.
₁ , the middle capacity drive circuit DR ₂ and the small capacity drive circuit DR ₃ may be connected to each other.
When the drive circuits DR ₁ , DR ₂ , DR ₃ are connected to N, the number of circuits in the integrated circuit increases, and the power consumption also increases. Further, since the number of circuits to be passed increases, the timing accuracy also deteriorates.

An object of the present invention is to propose a signal transmission circuit capable of reliably transmitting a signal even on a long signal line without increasing the degree of integration in the integrated circuit.

Accordingly, an object of the present invention is to provide a signal transmission circuit, a CMOS semiconductor device, and a circuit board which can solve the above-mentioned problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.

[0015]

SUMMARY OF THE INVENTION The present invention proposes a signal transmission circuit having a structure in which an additional circuit for outputting a voltage at a middle point of a power supply voltage is connected to any one of signal lines. .

According to the signal transmission circuit of the present invention, an additional circuit for outputting a potential at a middle point of the power supply voltage is connected to a signal line having a large wiring capacitance or a large input capacitance. The potential of the signal line is driven around the midpoint potential of the power supply voltage. That is, the driven circuit is driven around its own threshold voltage.

Since the output impedance of the additional circuit is low, the amplitude of the signal is suppressed to a small amplitude. However, since the driven circuit is driven around its own threshold, even if the amplitude of the applied signal is small, it can be turned on and off reliably and receive the signal. Further, since the output impedance of the additional circuit is low, the time constant for determining the transition time of the transmission signal (in this case, the product of the resistance and the capacitance) becomes small, so that a high-speed signal can be passed.

Therefore, even in the case of a signal line in which the sum of the wiring capacitance and the input capacitance is large, the input pulse can be transmitted without giving waveform distortion.

In addition, since the amplitude of the transmission signal becomes smaller,
Transient charging / discharging current to the wiring capacitance and input capacitance is reduced, and power consumption during operation can be reduced.

In order to solve the above problems, one mode of the present invention is to provide a driving circuit for transmitting a transmission signal, a signal line for transmitting the transmission signal, and two power supply voltages V _SS and V _{SS.
In a} signal transmission circuit including a driven circuit driven by _DD (V _DD > V _SS ) and taking in the transmission signal propagated through the signal line, the signal transmission line is higher than the power supply voltage V _SS for the signal line. A signal transmission circuit including an additional circuit that outputs a predetermined voltage lower than the voltage V _DD .

In one aspect of this embodiment, in the signal transmission circuit, the driven circuit has a digital circuit that outputs one of binary output voltages in accordance with an input voltage, and A circuit that outputs a voltage substantially equal to a threshold voltage at which the output of the digital circuit is inverted from one of the binary output voltages to the other.

In another aspect of the present embodiment, in the above signal transmission circuit, the additional circuit includes a power supply voltage _Vss and a power supply voltage Vss.
Outputs the voltage approximately at the midpoint of _DD .

According to still another aspect of the present invention, in the signal transmission circuit, the additional circuit has an output impedance lower than an output impedance of the drive circuit.

According to still another aspect of the present invention, in the signal transmission circuit, the output impedance of the additional circuit is 1/2 to 1/4 of the output impedance of the drive circuit.

In another aspect of the present invention, in the signal transmission circuit, the additional circuit has a first inverter and a feedback circuit connecting an input terminal and an output terminal of the first inverter.

In still another aspect of the present invention, in the above signal transmission circuit, the driven circuit has a second inverter, and the first inverter has a beta ratio substantially equal to the second inverter. Have.

In still another aspect of the embodiment, in the signal transmission circuit, the additional circuit has a P-type FET and an N-type FET, and the P-type FET and the N-type FET
Are applied with a forward bias voltage.

According to still another aspect of the present invention, in the signal transmission circuit, the additional circuit includes the power supply voltage V.
A voltage source that outputs a predetermined voltage that is higher than _{SS and} lower than the power supply voltage V _DD .

[0029] In still another aspect of the present embodiment, in the signal transmission circuit, the additional circuit further includes a low impedance buffer circuit for lowering an output impedance of the voltage output by the voltage source.

[0030] In still another aspect of the present embodiment, the signal transmission circuit includes a cutoff means for cutting off a current flowing between the signal line and the additional circuit.

In another aspect of the present embodiment, in the signal transmission circuit, the additional circuit includes a NAND gate and a feedback circuit connecting one input terminal and an output terminal of the NAND gate.

According to still another aspect of the present invention, in the signal transmission circuit, the NAND gate has a control terminal to which a control signal for interrupting a current flowing between the signal line and the additional circuit is input. .

In still another aspect of the present invention, in the signal transmission circuit, the additional circuit has a NOR gate and a feedback circuit connecting one input terminal and an output terminal of the NOR gate.

In still another aspect of the present invention, in the signal transmission circuit, the NOR gate has a control terminal to which a control signal for interrupting a current flowing between the signal line and the additional circuit is input. .

In another aspect of the present embodiment, in the signal transmission circuit, the additional circuit is connected to an end of the signal line.

Further, in order to solve the above-mentioned problems, the present invention
Another embodiment of the present invention is a driving circuit for transmitting a transmission signal,
A signal line for transmitting a transmission signal, and two power supply voltages V_SSPassing
And V _DD(V_DD> V_SS) Driven by the signal line
Having a driven circuit for capturing the propagated transmission signal
CMOS semiconductor devices with signal transmission circuits
The signal transmission circuit, for the signal line, the
Power supply voltage V_SSGreater than the power supply voltage V_DDLess than
It has an additional circuit for outputting a predetermined voltage.
CMOS semiconductor device is provided.

In one embodiment of the present embodiment, the CM
In the OS semiconductor device, the additional circuit has an output impedance lower than an output impedance of the driving circuit.

In another aspect of the present embodiment, the CMO
In the S semiconductor device, a beta ratio of the additional circuit is substantially equal to a beta ratio of the driven circuit.

In order to solve the above problems, the present invention
Has a driving circuit for transmitting a transmission signal.
First semiconductor device and two power supply voltages V_SSAnd V_DD
(V _DD> V_SS) Driven to capture the transmission signal
A second semiconductor device having a driven circuit
A signal for transmitting a signal from the driving circuit to the driven circuit.
A circuit board having a signal line pattern.
Power supply voltage V_SSLarger, the power supply
Voltage V_DDAn additional circuit that outputs a smaller predetermined voltage is provided.
And a circuit board characterized by the following.

In one embodiment of the present invention, the additional circuit has an output impedance lower than the output impedance of the drive circuit.

Note that the above summary of the present invention does not list all of the necessary features of the present invention, and sub-combinations of these features may also constitute the present invention.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the claimed invention and have the features described in the embodiments. Not all combinations are essential to the solution of the invention.

FIG. 6 shows an embodiment of the signal transmission circuit according to the present invention. DR, RC, LIN, CL, C shown in FIG.
G indicates a driving circuit, a driven circuit, a signal line, a wiring capacitance, and an input capacitance, respectively, as described in the drawing.

In the present invention, an additional circuit is connected to one of the signal lines LIN. The additional circuit can be configured by connecting an all feedback circuit NF to an inverter IV (polarity inverting circuit) formed of, for example, a CMOS circuit.

When high-speed signal transmission is performed, a signal propagated on a signal line is reflected by a driven circuit, and an overshoot and an undershoot may occur in a signal waveform captured by the driven circuit. In order to reduce such overshoot and undershoot, an additional circuit may be connected to the end of the signal line LIN.

FIG. 7 shows an example of the specific circuit structure.
In this example, an example is shown in which the driving circuit DR and the driven circuit RC also use inverters formed of CMOS circuits. The additional circuit can also be configured by connecting an all feedback circuit NF to an inverter having a CMOS circuit structure. According to the circuit structure of the adding circuit, it is possible to stabilize the potential of the common connection point J inverter input terminal and the output terminal to approximately the midpoint potential of the power supply voltage V _DD -V _SS. The reason will be described with reference to FIG.

In FIG. 8, a curve Y indicates a DC transfer characteristic of the inverter IV (a relationship between an input voltage and an output voltage).

Since the inverter has the function of logical inversion (negation), it exhibits a right-down characteristic near the logical threshold.

Here, in order to constitute the additional circuit according to the present invention, when the input and output terminals are short-circuited (or connected by an element such as a resistor) and full feedback is applied, the input and output voltages have the same value. Therefore, Vin = Vo is superimposed on the curve Y.
When the straight line X of ut is drawn, it is understood that the output voltage of this circuit becomes equal to the intersection of the straight line X and the curve Y.

This intersection is exactly the point at which the output voltage is inverted in the DC transfer characteristic, ie equal to the logical threshold of the inverter.

P-type FET and N-type F constituting an inverter
If the on-resistances of ET are equal, this intersection is exactly the midpoint of the power supply voltage.

Although the term on-resistance is used here for simplicity, it actually has nonlinearity. For a more accurate expression, a number called a drain coefficient β will be used as an index indicating the ease of flow of the drain current of the FET.

Drain current coefficient β: a proportional constant determined by the size, aspect ratio, etc. of the MOSFET.

Β of N-type FET and P-type FET is β
n, βp,

Βn = (W / Leff) · (εox / To
x) · μn, eff

Βp = (W / Leff) · (εox / To
x) · μp, eff

W: gate width, Leff: effective gate length,
Tox: gate oxide film thickness, εox: gate oxide film dielectric constant, μn, eff; effective electron mobility, μp, eff;
Effective mobility of holes

If β is used, the drain current of the MOSFET can be simply expressed as follows. Id = β ｛(Vgs−Vt) Vds− (1/2) (Vd
s ² )｝

(Vds ≦ Vgs−Vt) Id = (１ ／) β (Vgs−Vt) ² (Vds> Vgs−Vt)

In the case of silicon, since the mobility of holes is about half of the mobility of electrons, if the N-type FET and the P-type FET are formed in the same shape (assuming that the threshold voltages are equal), (1) N-type FET The current of the FET flows twice as much as that of the P-type FET. (2) The ON resistance of the N-type FET is half that of the P-type FET. It can be said.

In a normal device, it is usual that the β of the N-type FET and the P-type FET are made equal or the shape (W, H) is made equal.

When the ratio of βp of the P-type FET to βn of the N-type FET (βR = βn / βp, beta ratio) is changed by about 10 times, the change in the curves Y1 and Y2 shown in FIG. Become. Here, Y1 is, for example, βn> βp, (βR
= 10), and Y2 can satisfy βn <βp, (βR = 0.1) (βn and βp are drain current coefficients of N-type FET and P-type FET, respectively).

[0063] The case, by setting as with additional circuit beta ratio of the inverter IV is also N-type FETs Q _N and P-type FETs Q _P which constitutes the driven circuit RC, the threshold voltage of the driven circuit RC is inverted operation it can be matched to the midpoint voltage of the power supply voltage V _DD -V _SS. Accordingly, by setting the relationship between the inverter IV forming the additional circuit and the inverter forming the driven circuit RC to the above-described relationship (generally, it is said that the beta ratio is assumed to be equal), the driven circuit RC becomes self-controlled. Will be received from the drive circuit DR centering on the threshold voltage.

FIG. 9 shows an equivalent circuit of this signal transmission circuit. The drive circuit DR can be equivalently represented by a switch SW. R _OUT indicates the output impedance of the drive circuit DR. In FIG. 9, the DC resistance of the signal line LIN is omitted. RM represents an equivalent resistor equal to the output impedance of the additional circuit. That is, the additional circuit can be represented as a circuit connected to the midpoint voltage V _C through an equivalent resistor RM having a resistance value of R _T.

When the switch SW is switched to the contact A side in the drive circuit DR, the positive voltage V _DD is applied to the signal line LIN through the output impedance R _OUT . Voltage E biasing positive than the midpoint voltage V _C at this time the equivalent resistor RM impedance R _T to the current I ₁ flows connection point J
₁ (FIGS. 10A and B) occur. This voltage _{E 1} is

E ₁ = (V _DD -V _C ) _RT / ( _RT + R _OUT )

On the other hand, in the drive circuit DR, the switch S
When W is switched to the contact point B, the power supply voltage V _SS is applied to the signal line LIN. Therefore the current I ₂ flows through the impedance R _T of this time additional circuit, the voltage at the node J swings to the negative side by E ₂ than the midpoint potential V _C. This voltage _{E 2} is

E ₂ = (V _SS -V _C ) _RT / ( _RT + _ROUT )

The resistance value R of the equivalent resistor RM of the additional circuit_TIs
As described above, a small value of R_T<< R _OUTIt becomes the relationship.
Therefore, the amplitude E of the signal generated at the connection point J₁And E₂Is minute
Value. Of course, the driven circuit RC has the midpoint potential V_CAnti
Occurs at the connection point J because it operates as a threshold value
Voltage E₁And E₂E within the amplitude range of_AAnd E_B
(FIG. 10B), the inversion operation is reliably performed. Therefore the driven circuit
RC is the potential at the node J at the midpoint voltage V_CCrosses slightly
And immediately inverts the wiring capacitance CL and the input capacitance CG.
The sum value is large and there is a delay in the potential change of the signal line LIN.
However, the output of the driven circuit RC is as shown in FIG.
Can be transmitted with almost no waveform distortion.
You.

The relationship between the output impedance R _T and the output impedance R _OUT will be described. Voltages E ₁ and E ₂
Is a function of R _T and R _OUT , as shown in the above equation.
The smaller the value of R _T, the voltage _{E 1} and _{E 2} is a very small value. However, the driven circuit RC has a threshold voltage, and the value of R _T must be determined within the sensitivity range of the signal of the driven circuit RC. The maximum input voltage at which the driven circuit RC can output a stable L or H value when the input is L is V _thL, and when the input is H, the driven circuit RC has a stable H or The minimum input voltage at which the value of L can be output is _VthH . When the input is gradually increased from L, the input voltage when the output of the driven circuit RC starts to substantially change is set to V _thL, and when the input is gradually reduced from H, the driven circuit R
The input voltage at which the output of C begins to change substantially is V
_It may be _thH . For example, the input voltage V _thH of the driven circuit RC is about V _C + (V _DD −V _C ) × 0.2, and similarly, the input voltage V _thL is about V _C + (V _SS −V _C ) × 0.2. From the equations for the voltages E ₁ and E ₂ , the ratio of R _T to R _OUT is
(1): (4 or less) is preferable. More preferably, the value obtained by dividing R _T by R _OUT is between １ ／ and ４.

In this specification, the term “midpoint voltage” does not necessarily mean only the center voltage between the power supply voltages V _DD and V _SS . As described with reference to FIG. 8, the midpoint voltage means any voltage between the power supply voltages V _DD and V _SS depending on the value of the beta ratio, and can vary from the center voltage.

Therefore, as shown in FIG.
N, a signal line L in which a number of driven circuits RC are connected
Even if it is IN, by connecting an additional circuit to this signal line LIN, each driven circuit RC operates following a change in the output voltage of the driving circuit DR.
C can be given clock pulses of the same timing (no time lag).

FIG. 12 shows a modified embodiment of FIG. This embodiment shows that the circuit operates normally regardless of where the additional circuit is connected to the signal line LIN.

The above description has been made with reference to the signal line LIN formed in the same semiconductor chip. When the present invention is applied to a signal line LIN formed outside an integrated circuit, for example, as shown in FIG.
_In the case of the signal line LIN connected between the signal line ₁ and the LSI ₂ , an additional circuit must be connected to the end of the signal line LIN. That is, for the signal line LIN formed outside the integrated circuit element, a distributed constant circuit such as a microstrip line is generally used to match the characteristic impedance to a predetermined impedance. Since the distributed constant circuit partially exhibits inductive and capacitive characteristics, as a result, it is desirable to connect an additional circuit to the end of the signal line LIN as shown in FIG.

FIG. 13 shows a circuit board according to an embodiment of the present invention. This circuit board has patterns of LSI ₁ and LSI ₂ and a signal line LIN. On the signal line LIN,
An additional circuit is connected. The LSI ₁ has a driving circuit that sends out the transmission signal, and the LSI ₂ has a driven circuit that takes in the transmission signal. The additional circuit, as described above,
It is connected to the end of the signal line LIN. This additional circuit outputs a predetermined voltage that is higher than the power supply voltage V _{SS and} lower than the power supply voltage V _DD , as in the previous embodiments. The additional circuit has an output impedance lower than the output impedance of the drive circuit of the LSI ₁ .

FIGS. 14 and 15 show a modified embodiment of the additional circuit. Adding circuit shown in FIG. 14 is a P-type FETs Q _P and N
To the gates of the mold FETs Q _N shows a case of a structure giving a forward bias voltage directly. With this configuration, the P-type FETs Q _P, N-type FETs Q _N maintains a state of always-on, maintaining the potential of the connection point J to the midpoint voltage of the voltage V _DD and V _SS, a low impedance Operates as a midpoint voltage source.

FIG. 15 shows a low impedance buffer circuit L
The case where an additional circuit is configured by combining the OW and the midpoint voltage source EJV is shown. Configuration of the low-impedance buffer circuit LOW The positive voltage V _DD side in exactly the reverse inverter N-type FE
A drain connected to the TQ _N, P-type FE in the anode voltage V _SS side
A drain connected to the TQ _P, connects the gate and the source in common, respectively, the midpoint voltage source to the common connection point of the gate EJ
A midpoint voltage V _C is applied from V.

FIG. 16 shows the low impedance shown in FIG.
4 shows an equivalent circuit of the buffer circuit LOW. As shown in FIG.
N-type FE constituting impedance buffer circuit LOW
TQ _NAnd P-type FET Q_PIs seen as a unity gain voltage buffer.
Output impedance as shown in FIG.
Resistance R equal to_UEquivalent resistor RM with
It can be expressed by the pressure source EJV.

[0079] Accordingly, in a state in which the driving circuit DR is outputting logic L, the current I ₁ flows toward the signal line LIN from the equivalent resistor RM, the potential of the connection point J from the midpoint potential slightly negative It is biased in the direction of the potential V _SS (L logic).
Therefore, at this time, the driven circuit RC is in a state of outputting H logic.

[0080] On the other hand, when the driving circuit DR is inverted to the state of outputting the H logic, current flows _{I 2} flows from the signal line LIN in the midpoint voltage source EJV the equivalent resistor RM. The potential at the connection point J by the current I ₂ flows is biased proximally Nuisance direction slightly positive voltage V _DD from the middle point potential V _C. Therefore, in this state, the driven circuit RC is inverted to a state of outputting L logic.

The resistance value R of the equivalent resistor RM shown in FIG.
_U is greater than the resistance value R _T of the equivalent resistor shown in FIG. 9, R _OUT >> relationship R _U can suppress the potential change of the maintained connection point J to slight amplitude variation. Therefore, as described with reference to FIG. 9 and FIG.
From the inverted timing of the output state of the driven circuit RC
Can be shortened (because the voltage change is small), and the response speed of the driven circuit RC can be increased also by the embodiment shown in FIG.

Although the embodiment shown in FIG. 15 shows the case where the midpoint voltage source EJV is constituted by a resistance dividing circuit, the midpoint voltage source EJV is connected to the additional circuit shown in FIG. Alternatively, an additional circuit may be used. When an additional circuit is configured by the midpoint voltage source EJV and the low impedance buffer circuit LOW, as shown in FIG.
Given midpoint voltage V _C to the plurality of low-impedance buffer circuit LOW by number of midpoint voltage source EJV, it can also be configured to connect an additional circuit for a plurality of signal lines.

By the way, in the semiconductor integrated circuit having the CMOS structure, the current consumption converges to a value close to zero when the active element is maintained in the stationary state. Therefore, when testing a semiconductor integrated circuit device, there is usually an item for measuring the current at rest and testing whether the current value is equal to or less than a specified value. On the other hand, if the additional circuit described above is incorporated in a semiconductor integrated circuit device, the additional circuit consumes current even in a stationary state. As a result, the integrated circuit device in which the additional circuit is incorporated is a device in which the quiescent current cannot be measured.

In the embodiments shown in FIGS. 18 to 21, in order to solve this inconvenience, an interruption circuit CUT is added to the additional circuit, a control signal is supplied to the interruption circuit CUT, and a current flowing through the additional circuit is supplied as necessary. It is configured so as to be able to shut off and to measure the quiescent current.

FIG. 18 shows an example in which a cutoff means CUT is added to the additional circuit shown in FIG. Cut-off means CUT
Has a control terminal CT. In this example, the additional circuit is maintained in an operating state by applying H logic to the control terminal CT, and is switched to a non-operating state by applying L logic, and the additional circuit consumes no current. An example is shown in which control is performed so as not to be performed.

That is, when H logic is applied to the control terminal CT, the FETs Q ₁ and Q ₃ are turned off, and the Q ₂ and Q ₄ are turned on. FETs Q ₂ is turned on, _{since Q 1} is controlled to the OFF state, FETs Q ₅ is turned on, _{Q 6} is controlled to the OFF state. As a result, FETs Q ₄ and _{Q 5} are controlled to ON-state, the gate mutual FETs Q _P and Q _N through these FETs Q ₄ and _{Q 5} is operated as an additional circuit is maintained in the connected state.

When L logic is given to control electronic CT, FET
Q₁, Q₃Is on, FETQ₂, Q ₄Is turned off
Is controlled. FETQ₁Is on, FETQ₂Is off
FETQ₅Is off, Q₆Is on
The state is controlled. That is, FETQ₄And Q₅Is off
And the FET Q₃And Q₆Is turned on
FETQ_PAnd Q_NIs controlled to the off state
You. Where FET Q₁, Q₃, Q₆Is controlled to ON
However, the FET Q connected in series to these₂,
Q₄, Q₅Is controlled to the off state,
Power supply current will not flow. Therefore, the control terminal CT
Quiescent current measurement if L logic is given
Can be.

The embodiment shown in FIG. 19 shows a case where the cutoff means CUT is constituted by a switch element ANS generally called an analog switch or the like. Switch terminal AN
By controlling the S in the off state, FETs Q _P and Q _N constituting an additional circuit is controlled to the OFF state.

FIG. 20 shows a case where a cutoff means CUT is added to the additional circuit shown in FIG. The difference from FIG. 18 is FE
The point is that the source electrode of TQ ₄ is connected to the negative power supply V _SS , and the point that the source electrode of FET Q ₅ is connected to the positive power supply V _DD . By controlling these FETs Q ₄ and _{Q 5} on state by applying a logical H to the control terminal CT, the gates of the P-type FETs Q _P and N-type FETs Q _N forward bias voltage V _SS and V _DD Given, P-type FE
TQ _P and N-type FET Q _N are controlled to be on, and operate as additional circuits.

When L logic is given to the control terminal CT, the FET
Q ₄ and Q ₅ are controlled to be off and Q ₃ and Q ₆ are controlled to be on. In this state, the P-type FET Q _P and the N-type FET Q _N are controlled to be off, and the current consumption is reduced to almost zero. Controlled.

FIG. 21 shows a configuration in which an additional circuit is formed by combining the low impedance buffer circuit LOW and the midpoint voltage source EJV shown in FIG. In this embodiment, a case is shown in which the additional circuit shown in FIG. 7 is used for the midpoint voltage source EJV. CUT1 is composed of a P-type FET Q _P1 and an N-type FET Q constituting a midpoint voltage source EJV.
Cutoff means for controlling _N1 to a cutoff state, CUT2
Denotes a shut-off means for controlling the N-type FET Q _N2 and the P-type FET Q _P2 constituting the low impedance buffer circuit LOW to a cut-off state.

When H logic is given to the control terminal CT,
In the stage CUT1, the FET Q_4-1And Q _5-1Is on
And the P-type FET Q constituting the midpoint voltage source EJV
_P1And N-type FET Q_N1Each gate of these FET Q
_4-1And Q_5-1Connected through. As a result, FIG.
The same circuit as that shown in FIG.
Outputs the point voltage.

On the other hand, in the cut-off means CUT2, the input terminal CT
Is given H logic, the FET Q _4-2 and the F
ETQ _5-2 is controlled to be on. As a result, the N-type FE constituting the low impedance buffer circuit LOW
TQ _N2 and the P-type FETs Q _P2 has a gate commonly connected through _{FETs Q 4-2} and _{FETs Q 5-2,} the midpoint voltage is applied from the midpoint voltage source EJV to the common connection point. Therefore, in this state, the N-type FET Q _N2 and the P-type FET Q _P2 have the same circuit structure as the low impedance buffer circuit LOW shown in FIG. 15, and a signal potential is applied to the connection point J2 from the drive circuit DR. The operation is the same as described in the above.

[0094] When the L logic is applied to the input terminal CT, _{FETs Q 3-1} and _{Q 6-1} in blocking means CUT1 is on,
Since Q _4-1 and Q _5-1 are turned off, the P-type FET Q _P1 and the N-type FET Q _N1 constituting the intermediate voltage source EJV are turned off.

In the cutoff means CUT2, the FET Q_4-2And F
ETQ_5-2Is off, Q_3-2And Q _6-2Is on
, The low impedance buffer circuit LO
N-type FET Q constituting W_N2And P-type FET Q_P2Is off
The state is controlled.

Therefore, in the additional circuit shown in FIG. 21, when the L logic is applied to the control terminal CT, all the currents are cut off, and the static current can be measured.

In the above embodiments, the additional circuit is
The configuration in which the all feedback circuit NF is connected to the inverter IV has been described. Below, circuits other than the inverter IV,
For example, an embodiment in which an additional circuit is formed using a NAND gate and a NOR gate will be described.

FIG. 22 shows another embodiment of the signal transmission circuit according to the present invention. Compared to the embodiment shown in FIG.
While the additional circuit shown in FIG. 6 has an inverter IV, the additional circuit according to the present embodiment has a NAND gate. The additional circuit shown in FIG. 22 is configured by connecting an all feedback circuit NF to a NAND gate. Also, N
Since the AND gate has a plurality of input terminals, one terminal can be used as the control terminal CT as shown in the figure.

FIG. 23 shows an example of a specific configuration of an additional circuit using a NAND gate. In this circuit configuration, the operation of the additional circuit can be turned on / off by switching the input signal of the control terminal CT between H logic and L logic. In this embodiment, when the H logic is applied to the control terminal CT, the additional circuit is maintained in the operating state and can output the midpoint potential, and when the L logic is applied to the control terminal CT, the additional circuit is inactive. State and the output is set to H.

Referring to the circuit diagram of FIG.
Given a logical H, FETs Q ₁ is turned on, FETs Q ₄ is controlled to the OFF state to. Therefore, FET Q ₂ and FET
Drains of the Q ₃ is maintained in the connected state, additional circuitry is maintained in the operating state, and outputs a midpoint potential. As described above, by setting as with additional circuit beta ratio of N-type FETs Q _N and P-type FETs Q _P which constitutes the driven circuit, a power supply voltage threshold voltage driven circuit RC is reversed operation V _DD - The midpoint voltage of V _SS can be matched, and the driven circuit RC can receive a signal sent from the driving circuit DR around its own threshold voltage.

On the other hand, when L logic is given to the control terminal CT,
FETs Q ₁ is off, FETs Q ₄ is controlled to ON-state. Therefore, the potential of the common connection point J is always H. At the time of a leakage current test (quiescent current test) of a semiconductor integrated circuit element, it is necessary to set the output of the transmission side (drive circuit DR) equal to the potential of the common connection point J.

As described above, by controlling the input of the control terminal CT, the operation of the additional circuit formed using the NAND gate can be turned on / off.

FIG. 24 shows still another embodiment of the signal transmission circuit according to the present invention. Compared with the embodiment shown in FIG. 6, the additional circuit shown in FIG. 6 has an inverter IV, whereas the additional circuit according to the present embodiment has a NOR gate. The additional circuit shown in FIG. 24 is configured by connecting an all feedback circuit NF to a NOR gate. Also, N
Since the OR gate has a plurality of input terminals, one terminal can be used as a control terminal CT as shown in the figure.

FIG. 25 shows an example of a specific configuration of an additional circuit using a NOR gate. In this circuit configuration, the operation of the additional circuit can be turned on / off by switching the input signal of the control terminal CT between H logic and L logic. In this embodiment, when the L logic is applied to the control terminal CT, the additional circuit is maintained in the operating state and can output the midpoint potential. When the H logic is applied to the control terminal CT, the additional circuit is not operated. State and the output is set to L.

Referring to the circuit diagram of FIG. 25, control terminal CT
Is given L logic, the FET Q₁Is off, FET Q₂But
It is controlled to be on. FETQ₃Drain is FE
TQ ₂FETQ₂Is on
FETQ ₃And FETQ₄Drain of
They are kept connected and operate as additional circuits.
It is maintained in a working state and outputs a midpoint potential. As mentioned above
The N-type FET Q constituting the driven circuit_NAnd P-type FET
Q_PTo set the beta ratio of
The threshold voltage at which the driven circuit RC performs an inversion operation is
Pressure V_DD-V_SSTo the midpoint voltage of
The driving circuit RC is driven from the driving circuit DR around its own threshold voltage.
It is possible to receive the transmitted signal.

On the other hand, when H logic is given to the control terminal CT,
FETs Q ₁ is turned on, FETs Q ₂ is controlled to the OFF state. Since FETs Q ₁ is turned on, the potential of the common connection point J becomes always L. During the leakage current test (quiescent current test) of the semiconductor integrated circuit device, the transmission side (drive circuit DR)
Must be set equal to the potential of the common connection point J.

As described above, by controlling the input of the control terminal CT, the operation of the additional circuit formed using the NOR gate can be turned on / off.

The terms used in describing the embodiments of the present invention will be described.
The “midpoint voltage” has been used, but the “midpoint voltage”
Power supply voltage V_DDTo V_SSOnly the voltage at the center between
Not to taste. As described with respect to FIG.
The point voltage is the power supply voltage V according to the value of the beta ratio._DDOr
Ra V_SSMeans any voltage between and from the center voltage
Can fluctuate. For example, the "midpoint voltage source" shown in FIG.
Is not necessarily the power supply voltage V _DDTo V_SSIt's the center voltage between
Instead of outputting the threshold voltage of the driven circuit RC,
A corresponding voltage can be output.

As described above, the present invention has been described using the embodiments. However, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is apparent to those skilled in the art that various changes or improvements can be added to the above embodiment. It is apparent from the description of the appended claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

[0110]

As described above, according to the present invention, by connecting the additional circuit to the signal line LIN, the signal line LIN is excited with a small amplitude around the midpoint voltage of the power supply voltage. In addition, the transition time is shortened by inserting a low resistance in parallel with the capacitance that degrades the response speed.
As a result, the driven circuit RC performs the inversion operation at a timing when the voltage slightly changes from the inversion timing of the signal of the driving circuit DR, and detects the inversion timing of the signal sent from the driving circuit DR with a slight time delay. be able to.
That is, the response speed of the driven circuit RC can be increased. As a result, even if a pulse having a narrow pulse width is output from the drive circuit DR, this pulse can be reliably detected and reproduced on the output side of the driven circuit RC. Further, in the present invention, even if the power supply voltage fluctuates, the midpoint voltage V _C output by the additional circuit changes following the fluctuation. And can always operate normally.

Therefore, in a large-scale semiconductor integrated circuit having a large shape of the semiconductor chip CP, even if the total length of the signal line for clock distribution becomes long, for example, the clock is reliably transmitted to the terminal side of the signal line for clock distribution. Can be sent.

Also, not only the clock distribution line but also a data line such as a bus line to which a data receiving circuit is connected at various places and a large number of input capacitances are connected to a data line, the data receiving circuit is connected to all the data receiving circuits. Can be sent.
Therefore, a large-scale integrated circuit can be realized by applying the present invention.

An additional circuit having a beta ratio equal to the beta ratio of the driven circuit and having a full feedback circuit can automatically generate a voltage that matches the logical threshold voltage of the driven circuit. In particular, when both the driven circuit RC and the additional circuit are formed on the same device (semiconductor chip), the driven circuit RC
, The output voltage of the additional circuit also fluctuates following the logical threshold voltage, thereby enabling highly accurate transmission. When the driven circuit RC and the additional circuit are both formed on the same device, transmission of signals in the device is not affected by manufacturing deviation.

Further, in the present invention, a cut-off terminal CUT is added to a circuit such as the additional circuit and the midpoint voltage source, and the current flowing through the circuit such as the additional circuit and the midpoint voltage source can be controlled to be in a cutoff state by the breaking means. Since the configuration has been proposed, even if the additional circuit and the midpoint voltage source are in a static state and consume the idling current, the idling current can be removed by controlling the circuit to the cutoff state.

As a result, when an integrated circuit device incorporating the additional circuit or the midpoint voltage source is manufactured, and when the semiconductor integrated circuit device is tested, there is an advantage that the quiescent current can be easily measured.

[Brief description of the drawings]

FIG. 1 is an enlarged plan view of a semiconductor chip for explaining inconvenience of a conventional technique.

FIG. 2 is a connection diagram for explaining a conventional technique.

FIG. 3 is a waveform chart for explaining an operation state of FIG. 2;

FIG. 4 is a waveform chart for explaining another state of the operation of FIG. 2;

FIG. 5 is an enlarged plan view of a semiconductor chip for explaining one method for solving a problem that occurs in the related art.

FIG. 6 is a block diagram for explaining an outline of the present invention.

7 is a specific connection diagram of each part of the block diagram shown in FIG. 6;

FIG. 8 is a graph for explaining the operation of the embodiment shown in FIG. 7;

FIG. 9 is an equivalent circuit diagram for explaining the operation of the embodiment shown in FIG. 7;

FIG. 10 is a waveform chart showing waveforms at various parts of the equivalent circuit shown in FIG. 9;

FIG. 11 is a block diagram for explaining a practical example of the present invention.

FIG. 12 is a block diagram for explaining another practical example of the present invention.

FIG. 13 is a block diagram showing still another practical example of the present invention.

FIG. 14 is a connection diagram for explaining a modification of the additional circuit used in the present invention.

FIG. 15 is a connection diagram for explaining still another modification of the additional circuit used in the present invention.

FIG. 16 is an equivalent circuit diagram of FIG.

FIG. 17 is a block diagram for explaining a practical example of the embodiment shown in FIG. 15;

FIG. 18 is a connection diagram for explaining an example in which a blocking means is added to the additional circuit used in the present invention.

FIG. 19 is a connection diagram for explaining another example of the blocking means shown in FIG. 18;

20 is a connection diagram for explaining a configuration in which a blocking means is added to the additional circuit shown in FIG.

FIG. 21 is a diagram for explaining a configuration in which, when the additional circuit shown in FIG. 15 and the additional circuit shown in FIG. 7 are used as a midpoint voltage source, a cutoff means is added to these additional circuits and the midpoint voltage source; FIG.

FIG. 22 is a block diagram showing another embodiment of the signal transmission circuit according to the present invention.

FIG. 23 illustrates an example of a specific configuration of an additional circuit using a NAND gate.

FIG. 24 is a block diagram showing still another embodiment of the signal transmission circuit according to the present invention.

FIG. 25 illustrates an example of a specific configuration of an additional circuit using a NOR gate.

[Explanation of symbols]

 DR drive circuit RC driven circuit LIN signal line CL line capacitance CG input capacitance EJV midpoint voltage source CUT cutoff means

Claims (21)

[Claims] 1. A driving circuit for transmitting a transmission signal, a signal line for transmitting the transmission signal, and two power supply voltages V _SS and V _DD (V _DD > V _SS ), and the signal is transmitted on the signal line. in the signal transmission circuit comprising a driven circuit incorporating the transmission signal, to the signal line, the greater than the power supply voltage V _SS, and characterized in that it comprises an additional circuit for outputting the power supply voltage V _DD is less than a predetermined voltage Signal transmission circuit. 2. The circuit according to claim 1, wherein the driven circuit has a digital circuit that outputs one of binary output voltages in accordance with an input voltage, and the additional circuit outputs an output signal of the digital circuit from the binary circuit. 2. The signal transmission circuit according to claim 1, wherein the signal transmission circuit outputs a voltage substantially equal to a threshold voltage inverted from one of the output voltages to the other. 3. The power supply voltage V _SS and the power supply voltage V _DD
3. A voltage substantially at the midpoint of the output is output.
2. The signal transmission circuit according to 1. 4. The signal transmission circuit according to claim 1, wherein the additional circuit has an output impedance lower than an output impedance of the drive circuit. 5. An output impedance of the additional circuit,
1/2 to 1/4 of the output impedance of the drive circuit
The signal transmission circuit according to claim 4, wherein the signal transmission circuit has a size of: 6. The circuit according to claim 1, wherein the additional circuit includes: a first inverter;
The signal transmission circuit according to claim 1, further comprising a feedback circuit that connects an input terminal and an output terminal of the first inverter. 7. The signal transmission according to claim 6, wherein the driven circuit has a second inverter, and the first inverter has a beta ratio substantially equal to the second inverter. circuit. 8. The P-type FET and the N-type F
The signal transmission circuit according to claim 1, wherein the signal transmission circuit has ET, and a forward bias voltage is applied to each of the gates of the P-type FET and the N-type FET. 9. The signal transmission circuit according to claim 1, wherein the additional circuit has a voltage source that outputs a predetermined voltage higher than the power supply voltage V _{SS and} lower than the power supply voltage V _DD . 10. The signal transmission circuit according to claim 9, wherein the additional circuit further includes a low impedance buffer circuit that lowers an output impedance of the voltage output from the voltage source. 11. The signal transmission circuit according to claim 1, further comprising an interruption unit that interrupts a current flowing between the signal line and the additional circuit. 12. The method according to claim 12, wherein the additional circuit includes a NAND gate,
The signal transmission circuit according to claim 1, further comprising a feedback circuit that connects one input terminal and an output terminal of the NAND gate. 13. The signal transmission circuit according to claim 12, wherein the NAND gate has a control terminal to which a control signal for interrupting a current flowing between the signal line and the additional circuit is input. . 14. The signal transmission circuit according to claim 1, wherein the additional circuit has a NOR gate and a feedback circuit connecting one input terminal and an output terminal of the NOR gate. 15. The control circuit according to claim 1, wherein the NOR gate has a control terminal to which a control signal for interrupting a current flowing between the signal line and the additional circuit is input.
5. The signal transmission circuit according to 4. 16. The signal transmission circuit according to claim 1, wherein the additional circuit is connected to a terminal of the signal line. 17. A drive circuit for transmitting a transmission signal, a signal line for transmitting the transmission signal, and two power supply voltages V _SS
And V _DD (V _DD > V _SS ), wherein the signal transmission circuit includes a driven circuit that has a driven circuit that captures the transmission signal propagated through the signal line. CM having an additional circuit for outputting a predetermined voltage higher than the power supply voltage V _{SS and} lower than the power supply voltage V _DD to the signal line.
OS semiconductor device. 18. The CMOS semiconductor device according to claim 17, wherein the additional circuit has an output impedance lower than an output impedance of the driving circuit. 19. The CMOS semiconductor device according to claim 17, wherein a beta ratio of said additional circuit is substantially equal to a beta ratio of said driven circuit. 20. A first semiconductor device having a drive circuit for transmitting a transmission signal, and two power supply voltages V _SS and V _SS
A second semiconductor device having a driven circuit driven by _DD (V _DD > V _SS ) to capture the transmission signal; and a signal line pattern for transmitting the transmission signal from the driving circuit to the driven circuit. in the circuit board, with respect to the signal line, the greater than the power supply voltage V _SS, the circuit board characterized in that it comprises an additional circuit for outputting the power supply voltage V _DD is less than a predetermined voltage. 21. The circuit board according to claim 20, wherein the additional circuit has an output impedance lower than an output impedance of the driving circuit.