JPH11145808A - Power-on reset circuit and semiconductor integrated circuit device using the same - Google Patents

Abstract

[PROBLEMS] To provide a power-on reset circuit capable of supplying a reset signal after normal operation of a circuit is started even when power is continuously turned on and off. An NMO is provided between a power supply voltage VDD and a node N1.
The S transistor Msw is connected, and the potential of the gate terminal thereof is lower than the node N1 when the power is turned on, Msw is turned off, and when the power is turned off, Msw is turned on at a high potential. Enable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION With the increase in the scale of integrated circuits,
Circuits such as flip-flops are increasingly used. These circuits have indefinite values when the power is turned on, which may adversely affect circuit operation. The present invention relates to a power-on reset circuit for determining an indefinite value to a constant value at the start of operation of a circuit, and a semiconductor integrated circuit device using the same.

[0002]

2. Description of the Related Art FIG. 2 shows a basic configuration of a conventional power-on reset circuit. R1 is a resistor, C1 is a capacitor, I
nv1 is an inverter circuit. The resistor R1 and the capacitor C1 are connected in series between the power supply voltage VDD and the ground, and the connection point N1 is connected to the input terminal of the inverter Inv1 to obtain the reset signal OUT.

When power is turned on, a reset signal OUT is "H". Thereafter, a current of (VDD-V1) / R1 flows to C1, and the potential V1 of the connection point N1 is changed to the inverter Inv1.
Signal OU exceeds the logical threshold value Vt of
T becomes "L". In this manner, the reset signal OUT is obtained only for a certain period of time after the power is turned on.

[0004]

As described in Japanese Patent Application Laid-Open No. Sho 58-6623, as the scale of integrated circuits increases, circuits such as flip-flops have been used more and more. When the power is turned on, these circuits have indefinite values, which may adversely affect circuit operation.
Therefore, a power-on reset circuit is required to fix the undefined value to a constant value when the circuit starts operating.

FIG. 3A shows a circuit which normally operates when the power supply voltage VDD becomes equal to or higher than Va. Here, the alternate long and short dash line indicates a change in the logical threshold value Vt of the inverter Inv1 accompanying a change in VDD. FIG.
In the case of using the circuit of the conventional example, the reset signal must be output after the reset voltage becomes equal to or higher than Va.
Thereafter, it must be adjusted so that V1 exceeds the logical threshold value Vt of Inv1. In order to adjust the rise time of N1, it is necessary to reduce the current Iin flowing into the capacitor by increasing R1.

However, in this case, the following two problems occur.

(1) When the power is turned off, if R1 is increased, the charge stored in C1 is not discharged instantaneously,
The potential remains at N1 for a while. When the power is turned on again in this state, V1 is set to I before the circuit operates.
The reset exceeds the logical threshold value Vt of nv1, and the reset is released before the time ta0, that is, while the power supply voltage does not operate properly.

Here, as shown in FIG.
There is also a method in which a diode D1 for discharging the electric charge stored in 1 only when the power is turned off is reverse-biased between the power supply voltage VDD and N1. However, as shown in FIG. 3B, the forward voltage VD1 of the diode remains in N1 and cannot be completely discharged.

When the continuous power on / off is considered in this manner, the conventional circuit configuration is not sufficient, and a circuit configuration capable of completely discharging C1 is required.

(2) Since the configuration uses a resistor, it depends on the process and is not suitable for an integrated circuit. As shown in FIG. 5, there is a method in which a transistor M01 is inserted instead of R1 and a bias voltage is applied to its gate terminal to use M01 as a resistor. However, the same problem as described above remains.

SUMMARY OF THE INVENTION It is an object of the present invention to completely discharge a capacitor remaining when a power supply is turned off, thereby canceling a reset after a normal operation of a circuit is started even when the power supply is continuously turned on and off. It is in.

[0012]

In order to achieve the above object, according to the present invention, an electric charge of a capacitor is discharged by inserting an NMOS transistor between a power supply and N1 and operating the transistor only when the power is off. . Also, M
The drain and source ends of the OS transistor are determined by the level of the potential. In the NMOS transistor to be inserted,
By utilizing this property, by controlling the potential of the gate end in accordance with the change in the potential of the drain end and the potential of the source end, it is possible to flow a current only in a certain direction.

[0013]

FIG. 1 shows a basic configuration of a power-on reset circuit according to the present invention. This is because the PMOS transistor M01 and the current source I are connected between the power supply voltage VDD and the ground.
The PMOS transistor M11 whose gate terminal is biased by 0 and the capacitor C1 are connected in series, and the connection point N1 is connected to the input terminal of the inverter Inv1. Further, an NMOS transistor Msw is inserted between N1 and the power supply voltage. The following voltage is applied to the gate terminal of Msw.

When the power is turned on, the current flows into C1, and when the potential V1 of N1 exceeds the logical threshold Vt of the inverter Inv1, Inv1 outputs "L". Here, in order to turn off the transistor Msw, a voltage V2 that satisfies the condition of Equation 1 is applied to the gate terminal.

[0015]

V2-V1 <Vth (Equation 1) Next, when the power supply is turned off, Msw must be turned on in order to discharge the electric charge accumulated in the capacitor. give.

[0016]

V2−VDD ≧ Vth (Expression 2) Here, the power supply voltage VDD changes, but it is not always necessary to satisfy Expression 2. This is because the electric charge stored in C1 may be discharged until the power supply voltage is completely cut off, and the condition of Equation 2 may be satisfied only for the necessary time.

Generation of V2 that satisfies Equations 1 and 2 can be achieved by connecting the transistor M21 and the capacitor C2 to the gate terminal of Msw as shown in FIG. However, Equation 3 must be satisfied as a condition for satisfying Equations 1 and 2.

[0018]

C1 ≦ C2 or (W / L) M11 ≧ (W / L) M21 (Equation 3) The transistor M21 and the capacitor C2 satisfying this condition
Is connected to the gate terminal of the transistor Msw, when power is turned on, V1 rises faster than V2, so that Equation 1 is always satisfied, and Msw is turned off. Therefore, C1 keeps storing electric charges and outputs "L" when the voltage exceeds the logical threshold value Vt of Inv1.

When the power is turned off, V1 and V2 are set to VD
It starts to fall later than D. Therefore, the node N1 having a higher potential than VDD in Msw becomes the drain end,
The gate-source voltage is equal to the potential difference between N2 and VDD (V2-
VDD), when this satisfies Equation 2, the transistor Msw is turned on, discharging the electric charge of C1 and lowering N1 to the ground level. Here, in order to discharge in a shorter time, it can be said that Msw (W / L) should be increased.

FIG. 7 is a circuit diagram showing a main part of an embodiment of a specific semiconductor integrated circuit according to the present invention. FIG.
(A) shows the change in the power supply voltage VDD, and (B) shows the node N
1, the potential V1 of the node N2 is shown in FIG.
2 is indicated by a solid line, and changes in the logical threshold value Vt of the inverters Inv1 and Inv2 are indicated by dashed lines.

As shown in FIG. 8, at the time of turning on the power supply φon, a current flows into the capacitors C1 and C2 after the time ta when the circuit starts operating, and the potentials V1 and V2 of N1 and N2 rise. Here, since Equation 3 is satisfied, V1 rises faster than V2. Therefore, V1 first exceeds the logical threshold value Vt of the inverter Inv1, and outputs a reset signal "L". Subsequently, V2 exceeds the logical threshold value Vt of the inverter Inv2, and outputs an output signal “L”.
Here, by inputting the output signal of Inv2 to the gate terminal of the transistor M01, the transistors M01, M02, M
No current flows in the bias circuit composed of the transistors 03, M04, M05, and M06, which leads to low power consumption. However, in this state, the potentials of V1 and V2 begin to drop below the logical threshold value Vt of the inverter, and the reset signal cannot be fixed at "L". In order to prevent such a situation, the transistors M12 and M22 are connected as shown in FIG. 7, and a reset signal is input to the gate terminal. This makes it possible to raise V1 and V2 to the power supply voltage and fix the reset signal to "L".

When the power is turned off, N3 and N1,
Since current leaks from M11 and M21 due to the potential difference between N3 and N2, V1 and V2 drop quickly at the same time, and the expression 2 is not satisfied. Thus, in order to completely prevent the current from leaking, the transistors Ms1 and Ms1
2 is inserted and the output of the inverter Inv1 is connected to the gate terminal, so that when the output of Inv2 is "L", it can be completely turned off.

Similarly, in the transistors M12 and M22, a current leaks when the power supply is turned off, and V1,
V2 drops at the same time. However, the drop of V2 is
1, the size (W / L) of the transistor M22 is made much smaller than that of the transistor M12, so that the current leaking from the transistor M22 is reduced.
Can be slowed down.

[0024]

As described above, according to the present invention, the reset signal can be supplied after the normal operation of the circuit is started even when the power supply is continuously turned on and off.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic configuration of a power-on reset circuit of the present invention.

FIG. 2 is a circuit diagram showing a basic configuration of a conventional power-on reset circuit.

3A is a waveform diagram of a power supply voltage in a power-on reset circuit, and FIG. 4B is a waveform diagram of a node N1 in FIG.

FIG. 4 is a circuit diagram showing a power-on reset circuit in which a diode is inserted in the circuit of FIG. 2;

FIG. 5 is a circuit diagram showing a conventional power-on reset circuit that does not use a resistor.

FIG. 6 is a circuit diagram showing a power-on reset circuit that satisfies a condition of a node N2 according to a power supply voltage.

FIG. 7 is a circuit diagram of a semiconductor integrated circuit device according to one embodiment of the present invention.

8 is a waveform diagram of a power supply voltage in FIG. 7 (A), a waveform diagram of a node N1 in FIG. 7 (B), and a node N in FIG. 7;
2 is a waveform diagram (C).

[Explanation of symbols]

M01, M11: PMOS transistors, Msw: NMO
S transistor, C1, C2: capacitor, R1: resistor, I0: constant current source, Inv1, Inv2: inverter, D
1 ... Diode, VDD ... Power supply voltage, Vt ... Logical threshold value of the inverter.

Claims (4)

[Claims] 1. A first constant current source is connected between a power supply voltage and a first connection point, and a first capacitor is connected between the first connection point and ground. An input terminal of the inverter is connected, an NMOS transistor is connected between the power supply voltage and the first connection point, and a gate terminal of the NMOS transistor is connected to the NMOS transistor when power is turned on. A power-on reset circuit for controlling the voltage to be lower than the threshold voltage of the transistor, and controlling the potential difference between the gate terminal and the power supply voltage to be equal to or higher than the threshold voltage of the NMOS transistor when the power is off. . 2. The power-on reset circuit according to claim 1, further comprising a second constant current source and a second capacitor for controlling a gate terminal of the NMOS transistor. A second capacitor is connected between the power supply voltage and the gate terminal of the NMOS transistor.
The capacitor of the second capacitor is connected between the gate terminal of the OS transistor and the ground so that the rise and fall of the gate terminal of the NMOS transistor are delayed more than the rise and fall of the potential at the first connection point. A power-on reset circuit for setting a value and a current value of the second constant current source. 3. The power-on reset circuit according to claim 1, wherein when a terminal of said NMOS transistor connected to a first connection point is higher than a power supply voltage, said NMOS transistor is turned on, and A power-on reset circuit including an NMOS transistor that operates to turn off the NMOS transistor when the voltage is lower than the voltage. 4. A semiconductor integrated circuit comprising a power-on reset circuit according to claim 1 and at least one latch circuit, wherein at least one of reset inputs of the latch circuit is controlled by said power-on reset circuit. A semiconductor integrated circuit device.