JPH11145479A - Semiconductor device manufacturing method, semiconductor device, liquid crystal panel substrate, and liquid crystal panel - Google Patents

Abstract

[PROBLEMS] To accurately etch a polysilicon layer deposited by CVD or the like. SOLUTION: Before depositing a polysilicon layer, a substrate 1 is formed.
Light etching is performed on the surface of the gate insulating film 12 and the surface of the gate insulating film 12 formed thereon. As a result, the damaged portion, dirt, and the like are removed, so that the adhesion between the substrate 10 or the gate insulating film 12 and the polysilicon layer 2 is improved. The amount is reduced and the etching accuracy is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a thin film transistor (hereinafter, referred to as a TFT) formed on a glass substrate, and more particularly to a technique for improving the etching accuracy of a deposited layer. About.
Further, the present invention relates to the semiconductor device, a liquid crystal panel substrate and a liquid crystal panel using the same.

[0002]

2. Description of the Related Art Conventional semiconductor device manufacturing methods, for example,
In the method for manufacturing a TFT, the gate electrode 2a is formed as follows. That is, in FIG.
After depositing polysilicon, amorphous silicon, or the like on the substrate 10, patterning is performed to form an active layer 1a serving as a source / drain / channel. Second, the surface of the active layer 1a is subjected to thermal oxidation or the like. Thirdly, a gate insulating film 12 is formed, and thirdly, a conductive layer is deposited and then patterned to form a gate electrode 2a.

In a semiconductor device, for example, a TFT, it is necessary to provide a contact hole in order to secure connection of each electrode.
It is formed as follows. That is, in FIG. 12, first, the first interlayer insulating film 13 deposited on the entire substrate 10 is made to penetrate at a position corresponding to the source region, and the contact hole 5 for securing the connection of the source electrode is formed. A data line 3a as a conductive layer is formed thereon,
After the second interlayer insulating film 15 is entirely deposited, the connection between the second interlayer insulating film 15 and the first interlayer insulating film 13 is made to pass through at a position corresponding to the drain region. Contact hole 4 is formed to secure the thickness.

[0004]

However, as shown in FIG. 11, the gate electrode 2a formed by the above-described method tends to be over-etched, and thus has a problem that it cannot be fixed to a desired shape. .

Further, as shown in FIG. 12, the contact hole 4 formed by the above-mentioned method is overhang-etched between the first interlayer insulating film 13 and the second interlayer insulating film 15, and Therefore, similarly to the gate electrode 2a, there is a problem that the shape cannot be fixed to a desired shape.

The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the etching accuracy of a deposited layer so that the above-described gate electrode and contact hole can be formed into a desired shape. It is an object of the present invention to provide a method of manufacturing a semiconductor device, a semiconductor device, a substrate for a liquid crystal panel using the element, and a liquid crystal panel using the substrate.

[0007]

According to the present invention, in order to solve the above-mentioned problems, a step of forming a second layer on a first layer, and further depositing and etching a third layer is provided. And a step of etching at least one surface of the first or second layer before depositing the third layer.

Usually, CVD or sputtering is used to deposit the layer, so that the surface of the first or second layer is not significantly damaged, and stains such as photoresist adhere to the surface of the first or second layer. there is a possibility. Even if a third layer is further deposited on the first or second layer in such a state, it is considered that the adhesion is reduced due to damage or dirt received on the surface. However, according to the present invention, since the surface of the first or second layer is etched before the deposition of the third layer, the damaged portion is removed, and dirt attached to the surface is also removed. Since it is removed, the adhesion between the first or second layer and the third layer is improved.

According to a method of manufacturing a liquid crystal panel of the present invention, a plurality of data lines formed on a substrate, a plurality of scanning lines intersecting the plurality of data lines, and the plurality of data lines and the scanning lines are connected. A plurality of thin film transistors, and a method of manufacturing a liquid crystal panel having a plurality of pixel electrodes connected to the plurality of thin film transistors, a step of depositing and patterning a silicon layer to be an active layer of the thin film transistor on the substrate, Forming a gate insulating film to cover the silicon layer, light etching the gate insulating film, and forming a gate electrode on the lightly etched gate insulating film. I do.

The method of manufacturing a liquid crystal panel according to the present invention is characterized in that a plurality of data lines formed on a substrate, a plurality of scanning lines intersecting the plurality of data lines, and the plurality of data lines and the scanning lines are connected. A method of manufacturing a liquid crystal panel having a plurality of thin film transistors and a plurality of pixel electrodes connected to the plurality of thin film transistors, wherein a silicon layer serving as an active layer of the plurality of thin film transistors is deposited and patterned on the substrate Forming a gate insulating film so as to cover the silicon layer; forming a gate electrode on the gate insulating film; and forming a first interlayer insulating film on the silicon layer, the gate insulating film, and the gate electrode. Forming a contact hole in the first interlayer insulating film and connecting to the silicon layer through the contact hole. Forming an electrode, light etching the source electrode and the first interlayer insulating film, and forming a second interlayer insulating film on the lightly etched first interlayer insulating film and the source electrode; ,
Forming a contact hole on the first interlayer insulating film and the second interlayer insulating film; and forming a pixel electrode connected to the silicon layer through the contact hole. .

By having the light etching step as described above, it is possible to form a film having good adhesion without causing any problem such as damage or dirt on the surface.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

<Embodiment> In this embodiment, as a semiconductor device, a polysilicon type TFT for driving each pixel of an active matrix type liquid crystal display device is used. FIG. FIG. 3 is a plan view showing a layout for one pixel on a liquid crystal panel substrate. Also,
FIG. 1B is a cross-sectional view showing the structure of the TFT along the line AA in FIG.

First, in FIG. 1A, reference numeral 1a denotes a first polysilicon layer, which constitutes an active layer (source / drain / channel region) of a TFT. Reference numeral 2a denotes a scanning line, which becomes a gate electrode in a TFT. Reference numeral 3a denotes a data line, and a TF disposed so as to intersect the scanning line 2a.
A voltage to be applied to the source region of T is supplied. here,
The scanning line 2a is formed by a second polysilicon layer,
The data lines 3a are each formed by a conductive layer such as an aluminum layer.

Further, the contact hole 4 is made of ITO
(Indium-Tin Oxide) film is provided to connect a pixel electrode 6a made of a film and a drain region (or a source region) of the TFT in the polysilicon layer 1, and a contact hole 5 is provided between the data line 3a and the polysilicon layer. It is provided to connect to the source region of the TFT in 1a.

Next, in FIG. 1B, the substrate 10
It is composed of an insulating substrate such as a glass substrate (for example, a non-alkali substrate) or a quartz substrate. The gate insulating film 12 is formed on the surface of the polysilicon layer 1 serving as an active layer of the TFT by subjecting the polysilicon layer 1 to thermal oxidation or the like. Further, the first interlayer insulating film 13 and the second interlayer insulating film 15 are made of a SiO ₂ film (NSG film) or a BP film, respectively.
SG film (silicate glass film containing boron and phosphorus)
And formed by CVD as described later.

A manufacturing process of the TFT having such a configuration will be described with reference to FIGS.

First, in the step (1), a polysilicon layer 1 is deposited on the upper surface of the substrate 10 to a thickness of 500 to 2,000 angstroms, preferably a little less than 1000 angstroms by, for example, a low pressure CVD method.

In the step (2), the polysilicon layer 1 is patterned by a photolithography step, an etching step and the like to form an island-shaped active layer 1a in the TFT.

In the step (3), the surface of the active layer 1a is thermally oxidized to form a gate insulating film 12 on the surface of the active layer 1a. By this step, the active layer 1a finally has a thickness of 300 to 1500 angstroms, preferably 350 to 450 angstroms, and the gate insulating film 12 has a thickness of about 600 to 1500 angstroms.

Here, the extension portion 1b (see FIG. 1A) of the polysilicon layer forming the active layer 1a, which extends upward along the data line 3a to form a storage capacitor, has an impurity. (For example, phosphorus) to an appropriate dose (for example, 3 × 10
¹⁴ [atms / cm ² ]) to lower the resistance of the polysilicon layer at that portion. The lower limit of the dose is determined from the viewpoint of securing the conductivity necessary for forming the storage capacitor of the polysilicon layer, and the upper limit is determined from the viewpoint of suppressing the deterioration of the gate oxide film.

Next, in step (4), the surface of the substrate 10 with the gate insulating film 12 formed on the surface of the active layer 1a of the semiconductor device and the surface of the gate insulating film 12 are slightly etched (hereinafter, referred to as "below"). , Light etching). Here, the light etching in the step (4) includes:
For example, it is effective to use a mixture of hydrofluoric acid and pure water. The etching amount is determined by changing the concentration to hydrofluoric acid: pure water =
When the treatment time was set to 10 [seconds] and about 13 Å, the concentration was set to hydrofluoric acid: pure water = 1: 10 and the processing time was set to 5 [seconds]. In some cases, it is about 32 Å.

By such a light etching, the surface portion of the substrate 10 damaged in the step (1) is removed, so that the inherent properties of the substrate 10 can be brought out. Further, by this light etching, impurities and residues adhering to the surfaces of the substrate 10 and the gate insulating film 12 are also removed.

In the step (5), a low-resistance polysilicon layer 2 to be a gate electrode and a scanning line is formed on the gate insulating film 12 and the substrate 10 in the TFT.
Is deposited by a low pressure CVD method or the like. Here, as a material of the gate electrode, in addition to polysilicon, Mo, Ta, T
Refractory metals such as i and W, or metal silicides thereof can be used.

Turning now to FIG. 3, in step (6), the polysilicon layer 2 is patterned by chemical dry etching to form a gate electrode 2a including a scanning line of a TFT. The conditions of this chemical dry etching were as follows: O ₂ : 100 [sccm], CF ₄ : 300 [scc]
m], power: 700 [W], time: 50 to 90 [seconds], and if the light etching in the step (4) is omitted, the undercut amount of the patterned gate electrode 2a is 2.5 ± When light etching is performed, the undercut amount falls within 2.0 ± 0.5 [μm] while the value is 1.0 [μm].

The reason is that the substrate 10 or the gate insulating film 12 and the polysilicon layer 2 deposited in the step (5) are formed by the light etching in the step (4).
This is considered to be due to the fact that the adhesion between the layers is improved, so that the reactive gas does not easily enter between the layers.

Therefore, in the present embodiment, in addition to the removal of impurities and residues adhering to the surfaces of the substrate 10 and the gate insulating film 12, the etching accuracy of the gate electrode 2a is further improved.

In the step (7), ions of an impurity (for example, phosphorus) are implanted using the gate electrode 2a as a mask, and the self-aligned high-concentration semiconductor region serving as a source region and a drain region in the active layer 1a of the TFT. To form Note that the source / drain region is lightly doped with an impurity (phosphorus) at a dose of 1 × 10 ^{13 to} 3 × 10 ¹³ [atms / cm ² ] to form a low-concentration region. A wide mask layer is formed on the scanning line 2a, and impurities (phosphorus) are further added to 1 × 10 ^{15 to} 3 × 10 ¹⁵ [a
tms / cm ² ], the masked region is exposed to a lightly doped drain (LD
D) The structure may be adopted. Alternatively, the offset is performed by forming a pattern using a mask wider than the width of the gate electrode 2a without performing lightly doping, and then performing ion implantation to form a source / drain and then over-etching the gate electrode. You may make it become a structure.

In the step (8), the gate electrode 2a
The first interlayer insulating film 13 so as to cover the
5000 to 15000 at a temperature of 800 degrees by the method
Deposits to a thickness of Angstrom.

In the step (9), a contact hole 5 is formed in the first interlayer insulating film 13 at a position corresponding to the source region of the TFT by dry etching or the like.

Here, the contact hole 5 is formed so as to penetrate the laminated film of the gate insulating film 12 and the first interlayer insulating film 13.

Turning now to FIG. 4, in step (10), a low-resistance conductive layer 3 of aluminum or the like to be a data line also serving as a source electrode is deposited by sputtering. This low resistance conductive layer 3 is connected to the source region of the active layer 1a at the contact hole 5 of the TFT.

In the step (11), the low-resistance conductive layer 3 is patterned by photoetching to form a data line 3a also serving as a TFT source electrode.

Next, in step (12), the surface of the data line 3a as a source electrode of the semiconductor device and the exposed surface of the first interlayer insulating film 13 are light-etched. here,
In the light etching in the step (12), for example, it is effective to use a mixed solution of hydrofluoric acid, ammonium fluoride, and acetic acid. The etching amount is 20 to 50 angstroms when the concentration is set to hydrofluoric acid: ammonium fluoride: acetic acid = 1: 10: 5 and the processing time is set to 20 seconds.

By such a light etching, the surface portion of the first interlayer insulating film 13 damaged by the sputtering method of the low-resistance conductive layer 3 in the step (10) is removed, and the insulating film is originally removed. It is possible to bring out the properties possessed. Further, along with the light etching, impurities and residues adhering to the surface are also removed.

In the step (13), the data line 3
a, the second interlayer insulating film 15 is, for example, CV
According to the D method, at a low temperature such as 500 degrees
It is formed to a thickness of 00 angstroms.

Turning now to FIG. 5, in the step (14), the stacked film composed of the second interlayer insulating film 15, the first interlayer insulating film 13 under the second interlayer insulating film 15, and the gate insulating film 12 is formed. Then, at a position corresponding to the drain region, first, dry etching is performed to form a hole by anisotropic etching, and second, the hole is penetrated to the active layer 1a by wet etching, A contact hole 4 for the TFT is formed.

Here, the light etching in the step (12) removes the surface portion of the first interlayer insulating film 13 and further removes impurities and residues adhering to the surface. The adhesion between the first interlayer insulating film 13 and the second interlayer insulating film 15 is improved.

Therefore, when light etching is performed as in the present embodiment, an etching solution, a reactive gas or the like hardly enters between the first interlayer insulating film 13 and the second interlayer insulating film 15. Therefore, the contact hole 4 is formed with high accuracy.

In the step (15), an ITO film 6 to be a pixel electrode is formed to a thickness of, for example, 1500 angstroms by a sputtering method. At this time, the TFT
The ITO film 6 is connected to the drain region of the active layer 1a through the contact hole 4.

In the step (16), the ITO film 6 is patterned by photoetching,
The pixel electrode 6a of the TFT is formed.

In practice, a plurality of such TFTs are formed on the substrate 10 corresponding to each pixel.

As described above, according to the semiconductor manufacturing method of the present embodiment, the active layer 1 a
In the case where the polysilicon layer 2 is further deposited and etched to form the gate electrode 2a after forming the gate oxide film 12, the substrate 10 and the gate oxide film 12 are deposited before the polysilicon layer 2 is deposited. By performing the light etching, the etching accuracy of the gate electrode 2a can be improved.

Similarly, when the data line 3a is formed on the first interlayer insulating film 13 and the second interlayer insulating film 15 is deposited and etched to form the contact hole 4, the second interlayer insulating film 15 is formed. Before depositing the insulating film 15, the first
By lightly etching the inter-layer insulating film 13, a contact hole can be formed with high accuracy.

In this embodiment, the TFT has been described as an example of the semiconductor device, but the present invention is not limited to this. That is, the present invention can be widely applied to a case where an active layer of a semiconductor device is formed by patterning on an insulating substrate, or a case where a conductive layer is formed on a certain insulating layer and then another insulating layer is deposited.

In this embodiment, the step (4)
Although the light etching is performed in both of the steps and the step (12), the light etching may be performed in only one of the steps.

<Application Example> Next, an application example in which the TFT formed by this embodiment is applied to an active matrix type liquid crystal panel will be described.

FIG. 6 is a block diagram showing a configuration of a substrate 10 on which a TFT is formed, of a liquid crystal panel according to an application example.

In the drawing, reference numerals 90, 90,... Each denote a pixel, which is arranged corresponding to the intersection of the scanning line 2 and the data line 3 which are arranged to cross each other. Each pixel 90 includes a pixel electrode 6a made of ITO or the like, and a TFT 91 for applying a voltage corresponding to an image signal on the data line 3 to the pixel electrode 6a. The TFTs 91 in the same row have their gate electrodes connected to the same scanning line 2 and their drains connected to the corresponding pixel electrodes 6a. Also,
The source electrodes of the TFTs 91 in the same column are connected to the same data line 3. In this application example, peripheral circuits (X, Y shift registers and sampling means) 50,
60 is a TFT that drives a pixel
In the same manner as described above, it is constituted by a so-called polysilicon TFT using a polysilicon layer as an operation layer. Therefore, the transistors constituting the peripheral circuits 50 and 60 are provided with the pixel driving T
It is formed simultaneously with the FT by the same process.

In the figure, a shift register (hereinafter referred to as an X shift register) for sequentially selecting the data lines 3 is provided at one upper end of the display area (pixel matrix) 20.
On the other hand, a shift register (hereinafter, referred to as a Y shift register) 61 for sequentially selecting and driving the scanning lines 2 is provided at one left end of the pixel matrix. A buffer 63 is provided at the next stage of the Y shift register 61 as necessary.

At one end of each data line 3, a sampling switch 52 composed of a TFT is provided. These sampling switches 52 are connected to the image signals VID1 input to the external terminals 74, 75, 76.
.. Connected to video signal lines 54, 55, and 56, which are sequentially turned on / off by a sampling signal output from the X shift register 51. The X shift register 51 has a terminal 72,
73, a clock signal CLX input from outside through
, Xn for selecting all the data lines 3 one by one in order during one horizontal scanning period based on CLK2, and control terminals of the sampling switch 52. To supply. On the other hand, the Y shift register 61 is operated in synchronization with clock signals CLY1 and CLY2 input from the outside via terminals 77 and 78, and sequentially drives each scanning line 2. Also, the terminal 72
To 78 and the like are arranged as a pad electrode group in a line along the periphery of the substrate 10 as described later.

Next, the configuration of the entire liquid crystal panel will be described. FIG. 7A is a cross-sectional view illustrating a configuration of a liquid crystal panel to which the substrate in FIG. 6 is applied, and FIG. 7B is a plan view illustrating a layout thereof.

First, as shown in FIG. 7 (a), the liquid crystal panel 30 is composed of a substrate 10 on which TFTs and pixel electrodes are formed.
A transparent conductive film such as TO or the like is formed with a counter electrode (common electrode) 33.
And a counter substrate 31 having a TN (Twisted Nematic) in the gap between the electrodes so that the electrodes face each other and at an appropriate interval. ) Type and SH (Super H)
A liquid crystal 37 of an omeotropic type or the like is filled. Here, on the upper surface (lower side in the figure) of the counter electrode 33 of the counter substrate 31, a black matrix layer that shields the portion other than the portion corresponding to the pixel electrode on the substrate 10 and a color filter layer as necessary are provided. (Not shown).

The upper part of the peripheral circuits 50 and 60 is configured to be shielded from light by, for example, a black matrix layer provided on the counter substrate 31. Reference numeral 38 denotes a liquid crystal injection port provided on the counter substrate 31 side; In addition, as necessary for the liquid crystal panel,
Although a polarizing plate for selecting the polarization direction of the incoming and outgoing light, an alignment film for determining the molecular arrangement of the liquid crystal 37, a spacer for keeping the gap between the substrate 10 and the counter substrate 31 constant over the entire surface, and the like, are omitted. I decided to.

As shown in FIG. 7B, since the counter substrate 31 has a shape slightly smaller than the substrate 10 on which the TFT is formed, the pad electrode group 70 disposed on the periphery of the substrate 10 is formed. Is exposed outside the counter substrate 31,
This is convenient for use as an external input terminal for inputting signals such as a clock signal, a start signal, and a video signal to the peripheral circuits 50 and 60 described above.

In addition to the pad electrode group 70 on the peripheral portion of the substrate 10, the pad electrode group 1 as an inspection terminal used for inputting / outputting a signal at the time of inspection by a probe is provided.
70 are provided. On the other hand, a pad electrode group 270 as an inspection terminal is also provided on the counter substrate 31. These pad electrode groups are used for input / output of signals for inspecting a short circuit of a data line, a defect of a pixel electrode, and the like. Is done.

Reference numeral 80 denotes the substrate 1 on which the TFT is formed.
0 to the counter electrode 33 of the counter substrate 31 is a terminal for conduction between the upper and lower substrates for applying a common potential, and a conductive adhesive having a predetermined diameter is interposed between the substrate 10 and the counter substrate 31.
It is configured so as to achieve electrical continuity with.

Next, an example of connection between the liquid crystal panel and an external circuit will be described with reference to FIG. As shown in this figure, one pad electrode 71 of the pad electrode group 70
And an FPC (Film Pric) connected to an external circuit and supplying signals such as a clock signal, a start signal, and a video signal.
The terminal electrode 103 of the nted circuit 102 is physically fixed and held by an adhesive 101, and is electrically connected by conductive particles 100 dispersed in the adhesive 101.

Here, the conductive particles 1 in the adhesive 101
If the concentration of P.00 is properly set, conduction is allowed in the vertical direction of the adhesive layer (the direction connecting the pad electrode 71 and the terminal electrode 103), but conduction is not allowed in the planar direction of the adhesive layer. A conductive junction is realized. According to the anisotropic conductive joint, a large number of terminals having a small interval can be connected collectively, which is efficient.

The FPC 102 is formed, for example, by patterning a copper foil laminated on a polyimide film by a well-known photolithography step, etching step, or the like. Further, as the conductive particles 100, metal particles such as solder nickel or metal-plated plastic balls are used.

<Application Example of Liquid Crystal Panel> Next, an example in which a liquid crystal panel according to an application example is used as a display device will be described.

First, a video projector using this liquid crystal panel as a light valve will be described. FIG.
1 is a plan view showing a configuration example of a video projector.

As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside a video projector 1100. The projection light emitted from the lamp unit 1102 is transmitted to a plurality of mirrors 1106, 1 arranged in the light guide 1104.
.. And two dichroic mirrors 1108
Liquid crystal panels 1110R and 1110 as light valves corresponding to the three primary colors of RGB.
B and 1110G.

The configurations of the liquid crystal panels 1110R, 1110B and 1110G are as described above, and are driven by R, G and B primary color signals supplied from a video signal processing circuit (not shown). Now, the light modulated by these liquid crystal panels is transmitted to the dichroic prism 1112.
Is incident from three directions. This dichroic prism 1
At 112, the R and B lights are refracted at 90 degrees, while the G light travels straight. Therefore, as a result of combining the images of each color, a color image is projected on a screen or the like via the projection lens 1114.

<Application Example of Liquid Crystal Panel> Next, an example in which the liquid crystal panel according to the application example is applied to a personal computer will be described. FIG. 10 is a front view showing the configuration of this personal computer. In the figure, a personal computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display 1206. This liquid crystal display 1206 is
It is configured by adding a color filter and a backlight to the liquid crystal panel according to the application example described above.

As an application example of the liquid crystal panel, the video projector 1100 and the personal computer 12
Although 00 has been described, it is needless to say that the present invention can be applied to various other various electronic devices.

[0067]

As described above, according to the present invention, according to the present invention, the surface of the first or second layer is etched before the deposition of the third layer, resulting in a damaged portion. Is removed, and dirt and the like attached to the surface are also removed, so that the adhesion between the first or second layer and the third layer is improved, and the penetration of reactive ions, etching solution, and the like is prevented. . Therefore, it is possible to improve the etching accuracy of the third layer.

[Brief description of the drawings]

FIG. 1A is a plan view showing a layout for one pixel of a liquid crystal panel substrate to which a TFT is applied by a method of manufacturing a semiconductor device according to an embodiment of the present invention;
(B) is a cross-sectional view taken along the line AA.

FIGS. 2 (1) to 2 (5) are diagrams showing steps of manufacturing a TFT according to the same embodiment.

FIGS. 3 (6) to (9) are views showing steps of manufacturing the TFT according to the same embodiment.

FIGS. 4A to 4F are diagrams showing a manufacturing process of the TFT according to the same embodiment.

FIGS. 5A to 5C are diagrams showing a manufacturing process of the TFT according to the same embodiment.

FIG. 6 is a block diagram illustrating a configuration of a liquid crystal panel substrate having a TFT to which the method of manufacturing a semiconductor device according to the embodiment is applied.

7A is a cross-sectional view illustrating a configuration of a liquid crystal panel having a TFT to which the method of manufacturing a semiconductor device according to the embodiment is applied, and FIG. 7B is a plan view illustrating the configuration of the liquid crystal panel; It is.

FIG. 8 is a cross-sectional view showing an anisotropic conductive bonding structure between the liquid crystal panel and an external circuit.

FIG. 9 is a plan view showing a configuration of a video projector using the liquid crystal panel for a light valve.

FIG. 10 is a plan view showing a configuration of a personal computer using the liquid crystal panel for a display device.

FIG. 11 is a diagram showing inconvenience in a conventional process.

FIG. 12 is a diagram showing inconvenience in a conventional process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Polysilicon layer, 1a ... Active layer, 2a ... Scan line (gate electrode), 3a ... Data line (source electrode), 4,5 ...
Contact hole, 6: ITO film, 6a: pixel electrode, 1
0: substrate, 12: gate insulating film, 13: first interlayer insulating film, 15: second interlayer insulating film, 20: display area, 30 ...
Liquid crystal panel, 31 ... counter substrate

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: forming a second layer on a first layer, and further depositing and etching a third layer, wherein the third layer is deposited. Etching a surface of at least one of the first and second layers before performing the method. 2. The method according to claim 1, wherein the first layer is an insulating substrate, the second layer is an insulating layer covering an active layer of a semiconductor device formed on the insulating substrate, and the third layer is 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a conductive layer constituting an electrode of the semiconductor device. 3. The first layer is an insulating layer that is opened in one electrode and the other electrode of the semiconductor device, and the second layer is a conductive layer connected to the one electrode. 2. The method according to claim 1, wherein the third layer is an insulating layer opened in another electrode of the semiconductor device. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a thin film transistor connected to a plurality of scanning lines and a plurality of data lines arranged in a matrix, and formed corresponding to each pixel. 4. The method for manufacturing a semiconductor device according to item 2 or 3. 5. In a semiconductor device in which a third layer is further deposited and etched after the second layer is formed on the first layer, and before the third layer is deposited, The first or second
Wherein at least one surface of the layer is etched. 6. A liquid crystal panel substrate comprising the semiconductor device according to claim 5. 7. A liquid crystal panel substrate according to claim 6, and a counter substrate having a counter electrode are arranged at an appropriate distance, and a liquid crystal is disposed in a gap between the liquid crystal panel substrate and the counter substrate. A liquid crystal panel characterized by being sealed. 8. A plurality of data lines formed on a substrate,
Manufacturing of a liquid crystal panel having a plurality of scanning lines intersecting the plurality of data lines, a plurality of thin film transistors connected to the plurality of data lines and the scanning lines, and a plurality of pixel electrodes connected to the plurality of thin film transistors A method comprising: depositing and patterning a silicon layer to be an active layer of the thin film transistor on the substrate; forming a gate insulating film so as to cover the silicon layer; and lightly etching the gate insulating film. And forming a gate electrode on the light-etched gate insulating film. 9. A plurality of data lines formed on a substrate, a plurality of scanning lines intersecting the plurality of data lines, a plurality of thin film transistors connected to the plurality of data lines and the scanning lines, and A method of manufacturing a liquid crystal panel having a plurality of pixel electrodes connected to thin film transistors, wherein a step of depositing and patterning a silicon layer to be an active layer of the plurality of thin film transistors on the substrate and patterning the silicon layer is performed. Forming a gate insulating film on the gate insulating film; forming a gate electrode on the gate insulating film; forming a first interlayer insulating film on the silicon layer, the gate insulating film and the gate electrode; Forming a contact hole in one interlayer insulating film and forming a source electrode connected to the silicon layer through the contact hole; Lightly etching the first electrode and the first interlayer insulating film; forming a second interlayer insulating film on the lightly etched first interlayer insulating film and the source electrode; A liquid crystal panel comprising: a step of forming a contact hole on the second interlayer insulating film; and a step of forming a pixel electrode connected to the silicon layer via the contact hole.